FOR IMMEDIATE RELEASE
XILINX ANNOUNCES RECORD-BREAKING DEMONSTRATION
Run-time reconfiguration pushes FPGA performance past ASICs SAN JOSE, Calif., April 28, 2000—Xilinx, Inc. (NASDAQ:XLNX) today announced it has achieved 10.7 Gigabits per second performance in a Virtex™ FPGA implementation of the Data Encryption Standard (DES). Xilinx® JBits™ software was used to produce a circuit that surpasses the performance and consumes less power than a recently announced record-breaking ASIC implementation of this algorithm. Xilinx presented a paper detailing the work this month at the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000) in Napa, California. "While this is a demonstration and not a product, it highlights the ability of FPGAs to take on ASIC designs, even for challenging applications. The size, speed and power consumption is superior to any existing ASIC solutions,"said Rich Sevcik, Senior Vice-President and General Manager of Intellectual Property, Services, and Software at Xilinx. "It also demonstrates the power of JBits technology, which permits design upgrades in systems installed in the field, and supports new designs and algorithms without replacing hardware." The DES project is part of a DARPA-sponsored research effort with VirginiaTech to explore new tools, techniques and applications for FPGAs. In particular the research explored run-time reconfiguration using the JBits software. Xilinx JBits software provides direct support for fast compilation, fast circuit generation and run-time reconfiguration. These capabilities have previously been unavailable in FPGA design software. About Xilinx
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