FOR IMMEDIATE RELEASE
XILINX ESTABLISHES LEADERSHIP DIRECTION
On tap are LDT, POS-PHY4, 3.125Gbit, Infiniband, XAUI, RapidIO,
Virtex-II architecture to break 10 Gb/sec barrier next year SAN JOSE, Calif., September 25, 2000—Xilinx, Inc. (NASDAQ:XLNX), the leader in programmable logic, today announced an aggressive plan to provide high-bandwidth interconnect technologies for its FPGAs that will break the critical 10 Gigabits per second (Gb/sec) bandwidth barrier within the next year. Users can anticipate implementing these high-bandwidth interconnect technologies in the next generation VirtexTM-II architecture. High bandwidth interconnect technology is becoming increasingly necessary as FPGAs are used more and more as critical components in communications equipment. In addition to enabling much higher device performance, high bandwidth I/Os free-up package pins that were traditionally used as parallel I/Os. They also minimize switching related problems and drastically reduce power dissipation thereby enhancing device reliability in high bandwidth applications. "The integration of very high bandwidth interconnects and the previously announced IBM PowerPC processor core within our Virtex-II architecture will offer customers the most flexible, fastest time-to-market development platform in the industry," said Dennis Segers, senior vice president and general manager of the Xilinx Advanced Products Group. "The Internet economy has accelerated the need for these high-bandwidth interconnect standards. The breadth of standards that will be supported by Xilinx will ensure that system architects have flexible solutions for their emerging networking applications." The Xilinx direction includes physical layer support for the following popular high-bandwidth interconnect standards and applications:
High-bandwidth I/Os have traditionally been developed using high performance processes such as gallium arsenide. By contrast, the Xilinx direction of its high-bandwidth interconnects will be developed using CMOS process technology. By using the established CMOS technology, Xilinx FPGAs can meet the performance requirements of the emerging high-bandwidth interconnect standards, while consuming much less power than solutions implemented in other process technologies. "Interconnect bandwidth needs are outpacing Moore’s Law relative to current I/O standards, so we anticipate a dramatic shift to the new, higher bandwidth interconnect technologies," said Bruce Weyer, senior marketing director of the Xilinx Advanced Products Group. "The flexibility of Xilinx FPGA architectures have proven to be an enabling technology for our customers as they transition to new standards." Xilinx FPGAs are often used to translate differing I/O standards—a grand central station for I/O switching. System architects must integrate these I/O standards while maximizing performance and minimizing board real estate and cost. Xilinx FPGAs address this with support for 20 different I/O standards today. For example, Xilinx Virtex FPGAs support the SSTL I/O standard used in SDRAMs, the HSTL I/O standard used in SRAMs, the GTL+ I/O standard used in the backplane of Pentium-based systems, and LVDS, the I/O standard used in low EMI networking applications. About Xilinx Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, California, Xilinx invented the field programmable gate array (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com. —30— #0074
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