FOR IMMEDIATE RELEASE
SAN JOSE, Calif., December 11, 2000 - Xilinx, Inc. (NASDAQ:XLNX) today announced the immediate availability of its 64-bit, 66MHz Real PCI-X solution developed for its Virtex-E and next generation Virtex-II FPGA devices. The solution includes IP, silicon, software and support to enable the design of fully compliant, high performance and flexible PCI-X v1.0 systems on a single chip. As a result, designers are now provided with an alternative to Application Specific Standard Products (ASSPs) and benefit from the flexibility and cost reduction of a FPGA. Sam Locke, product development manager at VIEO, Inc., a leading builder, operator, and manager of flexible, high-speed I/O networks, chose the Xilinx Real PCI-X solution for a smart PCI-X adapter device. "The Xilinx PCI-X core, together with the Xilinx multi-million gate Virtex series FPGA, is enabling VEIO's design of high-performance smart PCI-X adapters that can meet the time-to-market demands and lower development costs required by an ever increasing number of today's applications like Gigabit/10 Gigabit Ethernet and Infiniband Network Interface Cards (NICs)." Xilinx expects its Real PCI-X solution to be used primarily in communication systems and storage area network products such as clustered servers, Ultra 3 SCSI and Fibre Channel based RAID arrays, and multi-port Gigabit devices. "Xilinx released its first PCI core more than four years ago, since then our PCI solutions have been used in more than 2000 customer designs." said Babak Hedayati, director of intellectual property marketing and business development at Xilinx. "This rich PCI heritage has enabled us to develop design and verification processes necessary to build and support high-quality PCI and PCI-X. And when our customers need more efficiency and higher bandwidth offered by PCI-X, they will have a reliable and easy migration path from existing Xilinx PCI solutions to next generation Xilinx PCI-X." The Real PCI-X solution enables customers to design fully compliant, high-performance systems by using Xilinx Smart-IP technology to ensure that the critical minimum, maximum and hold timing required for operation at 66 MHz are satisfied. The solution also verifies compliance with PCI-X v1.0 specification through hardware and regression testing, and device characterization using the Xilinx internal test bench that simulates more than six million unique combinations of PCI transactions. License price and availability
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