SAN JOSE, Calif., August 21, 2000—Xilinx Inc., (NASDAQ:XLNX) announced that their complete Foundation Series ISE FPGA design environment will include Xilinx® editions of StateCAD and HDL Bencher^TM from Visual Software Solutions (VSS). Foundation ISE software delivers a variety of customized tools that facilitate HDL-based design using Xilinx FPGAs. StateCAD brings a robust state machine design into Foundation ISE software, while HDL Bencher simplifies design verification of multi-million gate FPGAs.

Visual Software Solutions' StateCAD® Xilinx Edition and HDL Bencher Xilinx Edition are offered as part of the Xilinx EDA ALLiance STARter (ALLSTAR) program. StateCAD delivers powerful state diagram entry, while HDL Bencher simplifies the creation of HDL test benches. Standard editions of these tools are available from Visual Software Solutions with special pricing for Xilinx customers starting at $1495 for StateCAD and $1195 for HDL Bencher.

"With our multi-million gate devices, Xilinx designers are requiring tools from EDA companies for specific functionality. The Xilinx ALLSTAR program with our EDA partners allows us to deliver powerful tools like StateCAD and HDL Bencher to our customers," said Rich Sevcik, Xilinx senior vice president of, IP, service, and software.

"Membership in the Xilinx ALLSTAR program facilitates the delivery of VSS' solutions to FPGA designers. We see this pivotal membership turning our products into industry-leading tools for FPGA verification and state machine design," said Ricky Escoto, president of Visual Software Solutions.

HDL Bencher

HDL Bencher allows complete, timing constrained VHDL and Verilog test benches to be developed, validated, and simulated in minutes. No knowledge of HDL or scripting is required. The HDL Bencher WaveTable^TM spreadsheet entry quickly draws a waveform of the expected behavior and then exports a complete, self-checking test bench. The test benches are automatically updated as the design changes, eliminating stale test cases. The test benches include component instantiations, generic specifications, stimulus, output check procedures, and assertions. HDL Bencher automatically updates behavioral test benches for post-synthesis timing validation and creates "golden models" for regression testing and future design validation. 

StateCAD

StateCAD automates state machine development in VHDL, Verilog, and Abel. Using the FSM wizard, complex, concurrent state machines are specified graphically. Random logic and Mealy/Moore outputs can be embedded within state machines. To meet difficult product requirements, StateCAD optimizes the code it generates for speed, area, loading and more. StateCAD automatically analyzes designs for over 200 logic and syntax problems. Errors are detected before code generation and are eliminated before simulation to reduce development 
costs.

For additional information call 954-370-9030, or visit the web sites www.statecad.com (StateCAD), and www.testbench.com (HDL Bencher).

About Xilinx

Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquarters in San Jose, Calif., Xilinx invented field programmable gate arrays (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to significantly reduce the time required to develop products for the computer, peripheral, telecommunication, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com.

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Editorial contact:	Product Marketing contact:
Ann Duft	Craig Willert
Xilinx, Inc.	Xilinx, Inc.
(408) 879-4726	(303) 413-3237
publicrelations@xilinx.com	craig.willert@xilinx.com