2.1i Setup
Schematic Design
In this example, The Xilinx 2.1i Core Tools have been installed for
Solaris 2.6 in /tools/xilinx_21i. The Mentor Graphics Interface
is part of the Xilinx 2.1i tree under $XILINX/mentor. The Mentor
Graphics vendor software (where Design Manager and
Design Architect are located) has
been installed in /tools/mentor_C2. Please substitute the
appropriate directory paths that apply to your own system. Also, if
you are running the tools under HP-UX, please
substitute hp or sun for sol where
appropriate.
To run Xilinx 2.1i software with the Mentor Graphics Interface, the
following environment variables must be set:
setenv XILINX /tools/xilinx_21i
setenv LCA $XILINX/mentor/data
setenv SIMPRIMS $LCA/simprims
set path = ( $path $XILINX/mentor/bin/sol $XILINX/bin/sol )
In addition, the following variables must be set for the Mentor
Graphics third-party software. Consult the appropriate Mentor
Graphics documentation for more information.
setenv MGC_HOME /tools/mentor_C2
setenv MGC_GENLIB $MGC_HOME/gen_lib
setenv MGC_LOCATION_MAP /usr/local/data/mentor/mgc_location_map
setenv MGLS_LICENSE_FILE /usr/local/data/license/mentor_license.dat
setenv LD_LIBRARY_PATH $MGC_HOME/shared/lib:$MGC_HOME/lib:/usr/openwin/lib
set path = ( $path $MGC_HOME/bin )
# MGC_LOCATION_MAP: Substitute path to MGC location map.
# MGLS_LICENSE_FILE: Substitute path to FlexLM-format license file.
# LD_LIBRARY_PATH: Remove /usr/openwin/lib for HP-UX.
# For HP-UX 10.x, use SHLIB_PATH variable instead.
The LCA, SIMPRIMS, and MGC_GENLIB environment variables must also be
added to the file referenced by $MGC_LOCATION_MAP so that the Mentor
Graphics Software can recognize them. A location-map file may look
like:
MGC_LOCATION_MAP_1
$LCA
$SIMPRIMS
$MGC_GENLIB
Consult the Mentor Graphics documentation for more information on
location maps.
Verilog and VHDL Design
To perform timing or post-synthesis functional HDL simulation in M1,
the Verilog and/or VHDL (VITAL) simprim
models must be compiled for use in ModelSim/QuickHDL. If instantiated LogiBLOX
and/or Unified library components are to be behaviorally simulated,
the LogiBLOX and/or
Unisim libraries must be compiled, as
well.
Using the automatic compile scripts
2.1i includes the following scripts that automatically compile the
Verilog and VHDL simulation models for your particular version of
ModelSim or
QuickHDL:
$XILINX/mentor/data/verilog/compile_verilog_libs_modelsim.sh
$XILINX/mentor/data/vhdl/compile_vhdl_libs_modelsim.sh
and
$XILINX/mentor/data/verilog/compile_verilog_libs_quickhdl.sh
$XILINX/mentor/data/vhdl/compile_vhdl_libs_quickhdl.sh
For more information on using these scripts, see the accompanying README
files. These scripts should be run by your system administrator.
To compile the Unisim manually or to compile libraries for other device
families, see the next section.
Compiling the HDL libraries manually
ModelSim
To compile the Verilog and VHDL libraries for Model Technology ModelSim
please see:
Solution 1923 - MODELSIM: How to
compile the Simprim, LogiBLOX, Unisim, and Coregen libraries (VHDL and Verilog)?
QuickHDL
To compile the Verilog and VHDL libraries for QuickHDL please see:
Solution 2478 - M1 QuickHDL: How to compile
the HDL simprim, LogiBLOX, Unisim, and Coregen libraries (VHDL and Verilog)
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2.1i Setup
