ModelSim Interface - Documentation

Design Flow

• ModelSim EE User Manual
  The complete details on the usage and options of ModelSim EE 5.x
• ModelSim PE User Manual
  The complete details on the usage and options of ModelSim PE 5.x
• ModelSim FPGA Flow
  A general overview of a generic FPGA flow.
• ModelSim 5.2 With Xilinx Alliance 2.1
  A general overview of a using ModelSim PE with Alliance 2.1i.

Design files


• ModelSim Design Files, .zip format
• ModelSim and Foundation

A general overview of setting up the Alliance HDL libraries, and generating the gate-level netlist with SDF back-annotation for timing simulation.
• ModelSim and Synplicity Synthesis
  A general overview of using a post-synthesis/pre-Alliance simulation netlist from Synplify with ModelSim
• Synplify/ModelSim Tutorial Guide for Alliance 2.1i, 7/99 (197 KB)
  The Watch Design Synplicity Tutorial is a flow based tutorial taking the Verilog/VHDL Design files through Synplicity Synplify 5.1.x for synthesis. The tutorial includes pre-synthesis Functional Simulation, and a post place and route (PAR) Timing Simulation, both using the Model Technology ModelSim 5.2x simulator.
  Design files
  
  • Synplify/ModelSim Design Files, tar.Z format, 07/99 (186 KB)
  • Synplify/ModelSim Design Files, ZIP format, 07/99 (103 KB)
• ModelSim, Exemplar, Xilinx FPGA Design Methodology
  A general overview of using pre-synthesis RTL simulation, post-place and route gate-level timing simulation with SDF back-annotation of timing.
• Exemplar Leonardo Spectrum 1998.2e/ModelSim Watch Tutorial, 7/99 (516 KB)
  The Watch Design Exemplar Tutorial is a flow based tutorial taking the Verilog/VHDL Design files through Exemplar Leonardo Spectrum 1998.2e for synthesis. The tutorial includes presynthesis Functional Simulation, and a post place and route (PAR) Timing Simulation, both using the Model Technology ModelSim simulator.

  Design files
  

  • Exemplar/ModelSim Design Files, tar.Z format, 07/99 (768 KB)
  • Exemplar/ModelSim Design Files, ZIP format, 07/99 (446 KB)
• XAPP108: HDL Simulation Using the Xilinx Alliance Series Software , 05/2000
  Application Note describing the basic flow and issues to be aware of when performing HDL simulation of a Xilinx device using a Verilog or VHDL simulator.

Tools

• TCL and ModelSim EE