Synopsys FPGA Compiler Interface Journal - Glossary of Terms

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CONFIGURATION

A configuration is a VHDL design element. A configuration explicitly binds VHDL design entities together. Most commonly, a configuration is used to bind a testbench top-level entity to the testbench top-level architecture. Additionally, a configuration can be used to pass generics to an instantiated component. Passing of generics via a configuration lets a design use the same code for synthesis and simulation via the UNISIM libraries.

DESIGN_ANALYZER

Synopsys graphical interface to the synthesis tools.

DC_SHELL

Synopsys UNIX command line interface for entering commands, arguments, and options to the synthesis tools.

DC2NCF

This program translates a Synopsys DC file to an NCF (Netlist Constraints File) file. The DC file is a Synopsys file containing your design constraints.

EDIF

Electronic Design Interchange Format. An industry-standard netlist format.

FPGA COMPILER

FPGA Compiler is the recommended Synopsys workstation tool for doing FPGA designs. Unlike Design Compiler which only maps to generic gates, FPGA Compiler will map an HDL design using CLB's and IOB's. The current version of FPGA Compiler is v1998.02

HDL

Hardware Description Language. A language which describes circuits in textual code. The two most widely accepted HDLs are VHDL and Verilog.

IEEE

(pronounced "I triple-E")

Institute of Electrical and Electronics Engineers.

OSC4

OSC4 is the name of the synthesis and simulation component that synthesizes and simulates the XC4000 oscillator. The OSC4 can only be simulated using A1.4 and later versions.

ROC

The ROC cell is a UNISIM simulation model for the A1.4 (and later) XSI VHDL flow. The ROC cell simulates the toggling of the GSR (Global Set/Reset) net in the XC4000 for both functional and timing simulation.

ROCBUF

The ROCBUF cell like the ROC cell simulates the toggling of the GSR net in both functional and timing simulation. Like ROC, ROCBUF is a UNISIM cell. The ROCBUF is used when the user wants to control via a testbench the toggling of the GSR, but does not want to use the GSR for the synthesized design. While the ROCBUF does add a port to the top-level entity, the Xilinx A1.4 (and later) implementation tools will not add this port to the implemented FPGA design. The ROCBUF is a simulation only cell. Use the -gp switch with NGD2VHDL to add this port to the backend simulation model.

SEDIF

SEDIF is the type of EDIF that Synopsys Design Compiler writes as an output. Note, that if a user is using an EDIF file from Design Compiler, the file extension of the EDIF file must be 'sedif'. Note the case. Ngdbuild is case-sensitive to file extensions. If the file extension case is wrong, ngdbuild may not translate the EDIF file from Synopsys correctly.

SIMPRIM

All devices supported in the M1 back-annotated simulation flow are simulated with a common simulation library, which is composed of components known as SIMPRIM's. Collectively, these common simulation library components are known as the SIMPRIM library. In A1.4 XSI, if you are using a version of VSS later than V3.4b, the A1.4 XSI SIMPRIM libraries must be recompiled for your newer version.

STARTBUF

The STARTBUF simulates the behavior of the STARTUP device in the XC4000 family. Instantiation of the STARTBUF is the new means of telling the M1 core tools that the user wants to manually control the GSR/GTS net via an external pin, or internal source. Use of the STARTBUF will let the user simulate the behavior of the STARTUP symbol in both functional and timing simulation.

SXNF

SXNF is the type of XNF that FPGA Compiler writes out. Note, that while the SXNF file type appears to resemble XNF very closely, it is not 100% XNF. If you want to use the XNF that FPGA Compiler writes out, the file extension 'sxnf' must be used. Note the case. Ngdbuild is case-senstive with respect to file extensions. If the wrong case and/or file extension is used, ngdbuild may not translate the SXNF file from FPGA Compiler correctly.

SYNLIBS

This program displays onscreen the target and link libraries for the specified part type and speed grade. You can append the output of the Synlibs command to the .synopsys_dc.setup file. Warning: You must list the libraries in your setup file in the order that they appear in the Synlibs output.

TOC

The TOC cell is a UNISIM simulation model for the A1.4 (and later) XSI VHDL flow. The TOC cell simulates the toggling of the GTS (Global Tri-state) net in the XC4000 for both functional and timing simulation.

TOCBUF

The TOCBUF cell like the TOC cell simulates the toggling of the GTS net in both functional and timing simulation. Like TOC, TOCBUF is a UNISIM cell. The TOCBUF is used when the user wants to control via a testbench the toggling of the GTS, but does not want to use the GTS for the synthesized design. While the TOCBUF does add a port to the top-level entity, the Xilinx A1.4 implementation tools will not add this port to the implemented FPGA design. The TOCBUF is a simulation only cell. To replace this port in the back-end simulation model, use the -tp switch when invoking NGD2VHDL.

UNGROUP

Ungroup is a Synopsys command used in the A1.4 XSI command. This command is typicially executed with the -all. The 'ungroup -all' command is executed after replace_fpga and before writing out the SXNF file from Synopsys. It is not necessary to run this command. If this command is executed, the 'write' command will create a single SXNF file. The 'ungroup -all -flatten' command does not change the synthesis results of the synthesized design.

UNISIM

The UNISIM libraries are new functional simulation libraries in the A1.4 XSI flow. The UNISIM libraries include the ROCBUF, STARTBUF, TOC, and TOCBUF. The UNISIM libraries allow an HDL user to perform functional and timing simulation of an HDL design, even if there are cells instantiated from the XSI A1.4 synthesis library. Additionally, the UNISIM libraries allow the user to perform functional simulation of the GSR net, GTS net, and STARTUP. If you are using a version of VSS later than v3.4b, the UNISIM libraries must be re-compiled for the newer version of VSS.

VERILOG

An industry-standard HDL developed by Cadence Design Systems. Recognizable as a file with a .v extension.

VHDL

VHSIC Hardware Description Language. An industry-standard (IEEE 1076.1) HDL. Recognizable as a file with a .vhd or .vhdl extension.

VHDLAN

The vhdlan program analyzes a VHDL (.vhd) source file for simulation.

VHDLDBX

The Vhdldbx program is the VHDL Debugger, a graphical interface to the VHDL simulator. Through its dialog box, you can issue simulator commands, view command output, and view source code.

VHDLSIM

Vhdlsim is the command-line version of the Synopsys VHDL simulator, VSS.

VHSIC

Very High Speed Integrated Circuit.

VITAL

VHDL Initiative Toward ASIC Libraries. A VHDL-library standard (IEEE 1076.4) that defines standard constructs for simulation modeling, accelerating and improving the performance of VHDL simulators. The A1.4 XSI SIMPRIM and UNISIM VHDL libraries and VITAL libraries.

X-BLOX

Blocks of Logic Optimized for Xilinx. A schematic-based synthesis tool where generic bus-width-independent symbols such as counters, adders, and data registers are used to implement architecture-optimized functions. XBLOX has been replaced in the M1 release with LogiBLOX.

XDW

XDW means two things. The A1.4 (and later) XSI DesignWare libraries are referred to as XDW libraries. Part of the UNISIM libraries includes a library known as XDW, which is used for post-synthesis pre-A1.4 simulation of a synthesized VHDL design from FPGA Compiler.

XNF

Xilinx Netlist Format.