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Synopsys FPGA/Design Compiler Interface - Top Solutions
Hot Solutions |
| Solution 7000 - A2.1i Synopsys Designware libraries compiled for 1998.02 and 1997.08 |
| Solution 6958 - Cannot find a valid implementation for module "xdw_comp_uns" (SYNH-14) |
| Solution 4811 - ERROR:basnu:93 logical block of type RAM16X1D is unexpanded (unexpanded primitives). |
| Solution 4809 - A1.5, Synopsys - New DesignWare libraries available on the FTP site to fix carry-in problem with add_sub component. |
| Solution 4671 - A1.5, XSI, Virtex - Error - Either a NOR, or an AND and an OR gate (two-input) is required for mapping. |
| Solution 2311 - Synopsys vhdlan - Common issues/solutions re-compiling the M1.3/M1.4 XSI simulation libraries |
| Solution 2245 - M1 (FPGA/Design Compiler) - Versions of Synopsys compatible with the Xilinx Alliance software |
Most Requested Solutions |
| Solution 1189 - Analyzing the Synopsys Designware and Simulation Libraries |
| Solution 1166 - M1.4, M1.3 & XSI 5.2.1 Libraries Analyzed for Synopsys 3.3b (XACT XSI only), 3.4a (XACT XSI only), 3.4b, 3.5a,1997.01, 1997.08, and 1998.02 |
| Solution 1458 - How to get a listing of all library cell names in a XSI Library |
| Solution 1459 - How to get the pin order of a XSI library cell |
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