- BEST
-
Behavior Extracting Synthesis Technology. Synplify employs BEST by
abstracting circuit behavior to a high level and maintaining it
throughout the entire synthesis process.
- DST
-
Direct Synthesis Technology. Synplify employs DST to map directly to
the architecture (LUTs, CLBs, etc.) of the device part, not to gates
(AND/OR).
- HDL Analyst
-
A graphical tool that automatically generates hierarchical RTL-level
and technology-primitive level (after Synplify maps to LUTs, CLBs, etc.)
schematics from the source HLD design to visualize the synthesis results.
- SCOPE
-
Synthesis Constraint OPtimization Environment. A multi-level graphical
constraints editor that provides fine-grain user control over the
synthesis results.
- Synplify
-
Synplicity's synthesis engine. Synplify takes Verilog and VHDL code
as input and outputs an optimized netlist in most popular FPGA vendor
formats.
- TCL
-
Tool Control Language. Industry standard scripting language for controlling
software applications. Synplicity has extended TCL with some synthesis
commands so that it can be used as a scripting language to run Synplify.
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