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Welcome to the 1.5/1.5i tutorials page. These tutorials work with A1.5/F1.5
and A1.5i/F1.5i. This page has been designed to
provide you with state of the art and easy-to-use tutorial modules.
The objective of the tutorial modules is to familiarize you with the
new and improved Xilinx design flows from design entry to verification
and debugging. A complete flow entails walking through:
- The EDA interface of choice module (Exemplar, Synopsys, Synplicity)
- Running the Implementation module (Place & Route)
- Running the H/W Debugger module
Foundation
The Watch Design Foundation Tutorial is a complete tutorial using the Foundation F1.5 tools. The tutorial includes three design entry formats (Schematic, VHDL and Verilog) and covers Design Entry, Synthesis, Implementation and Device Configuration.
Exemplar
The Watch Design Exemplar Tutorial is a flow based tutorial taking the
Verilog/VHDL Design files through Exemplar Leonardo Spectrum 1998.2 or
Exemplar Leonardo/Galileo Extreme 4.2.2 for
synthesis. The tutorial includes presysnthesis Functional Simulation,
and a post place and route (PAR) Timing Simulation, both using the
Model Technology ModelSim simulator.
Synopsys
These tutorials are for use on UNIX workstations.
They are designed to introduce the Alliance 1.5
XSI design flow. For synthesis, either FPGA Compiler I or
Alliance FPGA Express must be used. For simulation, either
VerilogXL or VSS must be used. These tutorials go through
the implementation flow via command-line. For more detailed
information on the implementation flow, refer to the
implementation tutorial. For more information on the
verification flow, refer to the verification tutorial.
Synplicity
The Watch Design Synplicity Tutorial is a flow based tutorial taking the
Verilog/VHDL Design files through Synplicity Synplify for
synthesis. The tutorial includes presysnthesis Functional Simulation,
and a post place and route (PAR) Timing Simulation, both using the
Model Technology ModelSim simulator.
Implementation
This document demonstrates the steps in the 1.5 Alliance Series design implementation (GUI) flow for the Watch design. Before beginning this tutorial, you should
have entered the Watch design into the design entry tool of your choice.
Hardware Debugger
This is the Hardware Debugger Tutorial for the
Watch Design.
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