| Welcome to the 3.1i tutorials page. This page has been designed to
provide you with state of the art and easy-to-use tutorial modules. The
objective of the tutorial modules is to familiarize you with the Xilinx
design flows from design entry to verification and debugging using the
Watch design targeting a Virtex device.
For Foundation ISE (Integrated Synthesis Environment) 3.1i users, a
complete design flow entails going through:
For Alliance 3.1i users, a complete design flow entails going through:
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Design Entry Module (Exemplar, Synopsys, Synplicity)
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Alliance Implementation module
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Simulation Module (Cadence, Modelsim, Synopsys)
The design files which are created in the Design Entry Modules can be used
to perform the tutorials in the Simulation Modules and Implementation Module.
Users who do not wish to go through the complete design flow may select
and complete only the modules in which they are interested by downloading
both the PDF Tutorial File and the Design File for each module.
For more advanced training beyond these self-paced tutorials, please
consider attending a training course or taking an E-learning module offered
through our Customer
Education Services.
Foundation ISE
The Foudation ISE 3.1i Watch Tutorial is a complete tutorial using the
Foundation ISE 3.1i tools. The tutorial includes three design entry formats
(Schematic, VHDL and Verilog) and covers Design Entry, Synthesis, Implementation
and Simulation.
Exemplar
The Exemplar Watch Tutorial is a flow based tutorial taking the Verilog/VHDL
Design files through Exemplar Leonardo Spectrum v2000.1a for synthesis.
Synopsys
These tutorials are designed to introduce the Alliance 3.1i XSI (Xilinx
Synopsys Interface) design flow on the Unix platform. The Synthesis
FPGA/Design Compiler Watch Tutorial takes the Verilog/VHDL design files
through FPGA/Design Compiler v1999.05 for synthesis. The VSS Simulation
Watch Tutorial takes the VHDL design files through Synopsys VSS for VHDL
Simulation. The VCS Simulation Watch Tutorial takes the Verilog design
files through Synopsys VCS for Verilog Simulation.
Synplicity
The Synplicity Watch Design Tutorial is a flow based tutorial taking the
Verilog/VHDL Design files through Synplicity Synplify 6.0.0 for synthesis.
Cadence
The Cadence Watch Tutorial takes the Verilog design files through Cadence
Verilog-XL 2.8 for simulation.
Modelsim
The Modelsim Watch Tutorials are flow based tutorials taking the Verilog/VHDL
design files through Modelsim EE/PE v5.3 for simulation.
Alliance Implementation
The Alliance 3.1i Watch Tutorial demonstrates the steps in the Alliance
Series design implementation flow for the Watch design. The tutorial
assumes you have completed one of the Design Entry
Watch Tutorials and will use the netlists created in those tutorials.
If you have not completed a Design Entry Watch Tutorial, you may use the
the netlists provided in the Alliance 3.1i Watch Design Files below.
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