What's New
Success Stories
|
|
The XC9500XL CPLD family is targeted for leading-edge systems that require rapid design development, longer system life, and robust field upgrade capability. This 3.3V in-system programmable family provides unparalleled performance and the highest programming reliability, with the lowest cost in the industry. The XC9500XL CPLDs also complement the higher density Xilinx FPGAs to provide a total logic solution, within a unified development environment. The XC9500XL family is fully WebPOWERED via its free WebFITTER and WebPACK ISE software.
Family Highlights |
- Lowest cost per macrocell
- State-of-the-art pin-locking architecture
- Highest programming reliability reduces system risk
- Complements Xilinx 3.3V FPGA families
|
Features
|
Benefits
|
- Highest performance 5ns/222Mhz
|
- Leading-edge computing application
|
- Most flexible pin-locking architecture
|
- Design iterations without board rework
|
- Highest device reliability
|
- Higher quality, reduced support cost
|
|
- Reduced board area, increased flexibility
|
- In-system programming via JTAG
|
- Compatible with industry-standard ISP
|
- Robust 5V, 3.3V, 2.5V interfacing
|
- Worry-free mixed voltage operation
|
|
- Easily accessible and free software tools saves development time and cost
|
Unprecedented Performance
- 5 ns pin-to-pin speed
- 222 MHz system frequency
Powerful Architecture
- Wide 54-input function blocks
- Up to 90 product-terms per macrocell
- Fast and routable FastCONNECT II switch matrix
- Three global clocks with local inversion
- Individual OE per output, with local inversion
|
Highest Reliability
- Endurance rating of 10,000 cycles
- Data retention rating of 20 years
- Immune from "ISP Lock-Out" failure mode
- Allows arbitrary mixed-power sequencing and waveforms
Advanced Technology
- 3rd generation, proven CPLD technology
- Mainstream, scalable, high-reliability processing
- Fast in-system programming and erase times
Outperforms All Other 3.3V CPLDs
- Extended data retention supports longer system operating life
- Virtually eliminates in-system programming failures
- Superior pin-locking for lower design risk
- Glitch-free I/O pins during power-up
- Full IEEE 1149.1 (JTAG) ISP and boundary-scan test
- Free WebPOWERED software
|
|
XC9536XL
|
XC9572XL
|
XC95144XL
|
XC95288XL
|
Macrocells |
36
|
72
|
144
|
288
|
Usable Gates |
800
|
1,600
|
3,200
|
6,400
|
Registers |
36
|
72
|
144
|
288
|
tPD (ns) |
5
|
5
|
5
|
6
|
fSYSTEM (MHz) |
222
|
222
|
222
|
208
|
User I/O Pins |
|
|
|
|
44-pin PLCC
|
34
|
34
|
|
|
44-pinVQFP
|
34
|
34
|
|
|
64-pin VQFP
|
36
|
52
|
|
|
100-pin TQFP
|
|
72
|
81
|
|
144-pin TQFP
|
|
|
117
|
117
|
208-pin PQFP
|
|
|
|
168
|
48-pin CSP
|
36
|
38
|
|
|
144-pin CSP
|
|
|
117
|
|
256-pin BGA
|
|
|
|
192
|
256-pin FBGA
|
|
|
|
192
|
280-pin CSP
|
|
|
|
192
|
|
|
|
|