|
The Spartan-II FPGA's provide an ideal solution for various aspects of clock management. Four digital Delay Locked Loops (DLLs) are available on each Spartan-II device which provide zero propagation delay and low-clock skew. The dedicated DLLs can be used to improve and simplify system level design making these ideal clock management solutions for:
Clock Generation
The Spartan-II DLLs can be configured to either double the clock or divide the source clock by 1.5, 2, 2.5, 3, 4, 5, 8, or 16. Additionally, each DLL provides for quadrature phases of the source clock. Furthermore, the DLLs can be cascaded to generate a wide range of frequency variations and multiple clocks from a single reference crystal or clock, providing advanced control of multiple clock domains.
Clock Buffering & Distribution
Each DLL can also operate as a clock mirror. By driving the DLL output off-chip and then back in again, the DLL can be used to de-skew a board level clock between multiple devices. The SelectI/O feature allows conversion of clocks from one voltage level to another.
EMI Reduction By Spread Spectrum Clocking
Spread spectrum clocking is a simple method to lower electromagnetic interference (EMI). A digital system can create a severe EMI spike at the clock frequency. Spread spectrum clocking speeds up and slow down the clock within a few percent of the target frequency, thus flattening out the EMI peak by spreading it across a range of frequencies. The Spartan-II DLL can tolerate a variance of 2.5% making this an ideal choice for use in spread spectrum clocking.
|
