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The Xilinx Foundation Series Integrated Synthesis Environment (ISE) is Xilinx's next generation design environment, optimized to deliver the benefits of an HDL methodology to programmable logic designers.
The Next Generation Programmable Logic Design Environment
Foundation ISE is packed with technologies that help you bring your product to market faster. Advantages include:
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Ultimate productivity engineered in an intuitive project navigation environment with complete source management and context sensitive design processing. |
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Maximum designer proficiency using a suite of advanced HDL development tools and core generation technology. |
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Enhanced system performance resulting from the application of state of the art HDL synthesis and optimization engines from SynopsysTM and Xilinx. |
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Accelerated design cycles with revolutionary new place and route technology included with the world class Xilinx implementation tools. |
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Flexible design flows based on the industry's most comprehensive suite of verification tools and interfaces. |
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Expert knowledge and guidance built into an Internet-enabled error navigation system. |
| Begin using your Foundation ISE today, and take advantage of Xilinx best in class programmable logic devices. Foundation ISE offers comprehensive support for: |
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The Virtex Series FPGAs offer the highest memory bandwidth, I/O performance, and logic density available in the industry. |
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The Spartan Series FPGAs are an ASIC and ASSP production replacement solution with all the density and system performance - at the cost of an ASIC. |
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The XC9500 Series CPLDs offer unparalleled performance and the highest programming reliability, with the lowest cost in the industry. |
| Xilinx EDA ALLSTAR program |
| Foundation ISE also includes a suite of tools contributed by our EDA partners. These value-added solutions are provided as part of the EDA ALLSTAR (Alliance Starter) program.
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| If your design needs exceed the capabilities of the ALLSTAR tools, upgrades are available for purchase directly from each of the partners. These upgrades utilize the same user interface of the ALLSTAR tool, while providing
increased performance and/or capacity.
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| Embedded CORE Generator Simplifying IP Integration |
| By allowing you to easily reuse Intellectual Property built elsewhere within your organization, or by a 3rd party provider, the Xilinx Core Generator allows you to focus your creative energies on designing the unique aspects
of your design, ensuring your products' success in the marketplace. The 3.1i release of the Core Generator delivers improvements in the graphical user interface, design flows, and a host of new cores. |
| See the IP Center http://www.xilinx.com/ipcenter/index.htm to learn about the Intellectual Property that is available for your use. |
| Advanced Synthesis Technology |
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The Integrated Synthesis Environment provides two synthesis engines: FPGA Express and Xilinx Synthesis Technology (XST). Each of these tools is seamlessly integrated into the context sensitive flows that Project Navigator manages,
making it simple to synthesize your HDL using two of the industry's best HDL synthesis engines.
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| Xilinx Foundation ISE automated design flows embed the FPGA Express (v3.4) synthesis engine from Synopsys, delivering unprecedented levels of design performance for VHDL, Verilog or mixed VHDL and Verilog designs.
The Express and Elite configurations of Foundation ISE also include the FPGA Express graphical constraints editor, Time Tracker and Vista GUIs.
XST can be used as an alternative to FPGA Express for HDL optimization. However, the benefits of XST do not stop there. Xilinx is using XST as a proving ground for many of the innovative optimization ideas that Xilinx engineers have
for improving HDL design flows for Xilinx devices. These improvements are then shared with Xilinx 3rd party synthesis partners to ensure that anyone targeting Xilinx FPGAs as their solution can benefit from the best optimization the
industry has to offer.
Block Level Incremental Synthesis (BLIS)
Xilinx 3.1i Foundation Series ISE products include a new Block Level Incremental Synthesis (BLIS) capability that enables you to rapidly converge on your design's timing requirements. Synopsys has built this capability exclusively
for Xilinx. BLIS is based on the concept of focussing the optimization of HDL on a module by module basis, localizing the changes within a module, and therefore improving the efficiency of guided design. BLIS is yet another design methodology
that Xilinx is delivering to help you complete your design more efficiently.
High-Level Floorplanning coupled with Incremental Synthesis accelerates your time to market by isolating the synthesis, optimization, placement and routing design task to only the area of your design that has changed. By preserving
the remainder of your design, we can increase your design efficiency AND PERHAPS EVEN MORE IMPORTANTLY - reduce the amount of logic that you need verify when you take your next design revision out to the lab! You see, our incremental
design flow preserves the timing of the unchanged portions of your design as well.
The Xilinx high-level floorplanner also helps improve the quality of results our synthesis partners obtain by enabling physical synthesis tools to establish more accurate and aggressive timing estimates for the interconnect delays
within each floorplanned hierarchical block.
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| The Industry's Most Advanced Implementation Tools
Foundation Series ISE also includes Xilinx' latest implementation tools, seamlessly integrated to help you create the most efficient and compact designs that operate at the highest possible speed. These features include
- Timing Driven Place and Route - Allows you to specify your timing requirements for critical paths. This feature often gives 30-40% performance improvements when speed is critical; you no longer need to manually fine-tune
your design.
- Static Timing Analysis - Shortens your design process by providing an evaluation of your timing at various points in the implementation process, allowing you to make changes immediately.
- Simulation - Provides design verification before and after implementation, thus reducing the number of design iterations required to meet design specifications.
- Incremental Design Capability - Reduces your overall design cycle by allowing you to re-use previous iterations of your design. This is very helpful for evaluating design alterations.
- Hierarchical Timing Analysis - The Interactive Timing Analyzer organizes and displays data that allows you to analyze the critical paths in your circuit, the cycle time of the circuit, the delay along any specified paths,
and the paths with the greatest delay. It also provides a quick analysis of the effect of different speed grades on the same design.
- Integrated Logic Analysis - Xilinx has created the industries best Integrated Logic Analysis tool in order to address the debug verification bottleneck. ChipScope ILA is a silicon based analysis solution that is included
as a core function within your design. ChipScope ILA enables the in-system analysis of any signal that is available within the FPGA, while operating within the target system.
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| Foundation Series ISE Product Configurations
The Foundation ISE EVAL supports a variety of devices and is the first to support ten million gate FPGA design flows.
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Foundation ISE Device Support Summary
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Family
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Density
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ISE-EVAL
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| Virtex |
XCV50 Only |
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| All devices up to XCV1000 |
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| Virtex-E |
XCV50E Only |
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| All devices up to XCV1000E |
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| All devices up to XCV3200E |
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| Virtex-EM |
XCV405EM and XCV812EM |
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| Spartan |
XCSxx (All Devices) |
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| SpartanXL |
XCSxxXL (All Devices) |
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| Spartan-II |
All Devices up to XCS200 |
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| XC9500 Series |
XC9500 XV/XL(All Devices) |
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| XC4000 Series |
XC4000E/L/EX (All Devices) |
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XC4000XL/XLA
(All devices up to XC4020) |
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| XC4000XL/XLA (All devices) |
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| XC4000XV (All devices) |
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| XC3000 Series |
XC3x00A/L (All Devices) |
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| XC5200 Series |
XC5200 (All Devices) |
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| *Note: CoolRunner Series is only available in WebFITTER and WebPACK at this time. |
| Platform and System Requirements |
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Platform Support
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IBM PC or Compatible
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- Windows NT 4.0 (English, Japanese)
- Windows 2000 (English)
- Windows 98 SE (English)
- Windows 98 (Chinese, Korean, Japanese)
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- IBM Compatible Pentium processor
- Hard disk, RAM, Virtual Memory (See Below)
- 1024 x 768 VGA Color Monitor (Minimum)
- ISO9660 compliant CD-ROM drive
- Parallel or USB Port for device programming
(not required; Cable not included)
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| The memory requirements for both RAM and hard disk space will vary depending on your target device family and size as well as the unique characteristics of your design. Spartan II and Virtex Series devices between
50 and 600 system gates typically require 128 - 256 MB of RAM and an additional 256 - 400 MB of Virtual Memory. For detailed listings of the memory requirements specific to your installation, please reference the Foundation ISE 3.1i
Release Notes and Installation Guide. |
| Feature Summary
Foundation Series ISE supports the full line of Xilinx FPGAs and CPLDs including our XC3000, XC4000E/X/XL/XV, XC5200, XC9500,Spartan/XL and Virtex families. Also included are synthesis tools for ABEL; interfaces to EDIF, VHDL, and
Verilog; and the most efficient HDL design tools in the industry. The table below lists the features of the Foundation ISE product family.
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Foundation ISE Feature Summary
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ISE-EVAL
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| Design Entry |
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| Schematic Entry |
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| HDL Language Assistant |
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| ABEL Entry |
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| Color Coded HDL Editor |
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| State Diagram Editor |
VSS*
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| Environment |
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| Operating System |
PC
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| Simulation |
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| Gate Level Timing Simulation |
not available**
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| HDL Simulation |
MTI*
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| HDL Test Bench Generator |
VSS*
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| Synthesis |
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| Xilinx Synthesis Technology (XST) |
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| FPGA Express |
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| Incremental Synthesis |
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| System Features |
ISE-ELI
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| Constraints Editor |
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| Floorplanner |
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| CPLD ChipViewer |
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| Pin Editor |
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| FPGA Editor |
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| Core Generator included |
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| Configuration by cable |
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| Error navigation to Xilinx Web |
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| Command line operation |
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| HTML timing reports |
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| Data Book I/O timing |
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| Project archiving |
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| System Interfaces |
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| EDIF in |
not available***
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| PROM file generation |
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| JTAG download software |
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| IBIS |
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| STAMP |
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| VHDL, Verilog |
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| HDL Simulation libraries |
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