FPGA Advantage from Mentor Graphics or Synplify Pro from Synplicity
Summary
After you have captured and processed your design using Simulink and the Xilinx System Generator, you will have a top level VHDL design and sub files in the form of additional VHDL files or EDIF files. You will use Synthesis software to
convert the top level ( and additional sub VHDL files) HDL behavioral or RTL design files to a gate level representation (EDIF) . There are currently two compatible synthesis tools for the System Generator design flow:
Key Features
- Synthesize your HDL to a design implemented with gates
- Decreases design time by eliminating the need to define every gate.
- Reduces the number of errors that can occur during a manual translation of a hardware description to a schematic design.
- Apply the automation techniques used by the synthesis tool (such as machine encoding styles or automatic I/O insertion) during the optimization of your design to the original HDL code, resulting in greater efficiency.
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Mentor Graphics Leonardo Spectrum (included in FPGA Advantage)
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Synplify Pro from Synplicity
Continue to Step 3 -- Simulation
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