Xtreme Performance

New DSP Solutions for the New Information Technology Era

The enhanced DSP capabilities of the Virtex-II feature set are driving performance to never before seen levels.

Xilinx creates the highest performing DSP platforms by exploiting the parallelism that is inherent in the DSP mathematical models. The vast logic resources in Xilinx Virtex-II devices—densities up to 10 million system gates and up to 3.5 million bits of block RAM—enable you to create fully parallel structures when you need the greatest possible computational power and bandwidth. You gain the performance advantage of an ASIC without the added expense of inflexibility, long lead-times, and hefty non-recurring engineering (NRE) costs.

The Virtex-II architecture provides the Xilinx exclusive Active Interconnect ™Technology, featuring actively driven segmented routing between each building block element on the FPGA. Combined with unique Xilinx Smart-IP™ Technology, this ensures that performance is consistent over the entire range of FPGA device sizes, independently of the surrounding user-logic and level of integration. Up to 192 18x18-bit high-performance combinatorial multipliers embedded in silicon support data rates up to 250 MHz and allow for fast and efficient implementations of adaptive filters, equalizers and FFTs used in applications such as xDSL and cable modems or Gigabit Ethernet.

Distributed DSP Resources

• Xilinx FPGA fabric is an array of lookup tables (LUTs), registers, memory, and multipliers
• Supports up to 10 million system gates which allow super high-performance DSP functions through tremendous parallel processing ability

Data Storage

• Up to 3.5 Mbit of True Dual-Port™ Block RAM allows for single-chip implementation of large FFTs, video line buffers, and other memory intensive DSP functions
• Up to 1.9 Mbit of distributed memory for storage of coefficients and data
• Can be configured as RAM/ROM/FIFO or shift registers

Arithmetic Functions

• Up to 192 18x18 embedded multipliers allow optimal implementation of high-speed non-pipelined DSP functions
• Distributed arithmetic multipliers constructed from lookup tables (LUT) for efficient pipelined data structures
• Fast carry chains for addition and subtraction carry look-ahead arithmetic pipelining—signals can be pipelined either through registers or memory

System Features

• Xilinx Platform FPGA provides complete system features such as microprocessors, high-speed I/Os and DDLs allow for complete system integration - including DSP, memory interfaces, and control logic
• Up to 420 MHz system clock rates
• 840 Mbps differential I/O performance
• 420 MHz - Clock synthesis / Phase manipulation