Simulation

ModelSim from Model Technology found within the Mentor Graphics FPGA advantage tool set

Summary Simulation of a HDL can occur during three times in the design flow:

1. Functional simulation. This is a behavioral simulation of the HDL to ensure that the results from System Generator for DSP are correct.
2. Post-Synthesis functional simulation. This is typically a sanity check to ensure that the resultant from synthesis is correct but is not commonly run.
3. Post-implementation back-annotated timing simulation. This is the final sanity check with timing reports after placing and routing the FPGA.

Key Features

• Fastest compilation and competitive simulation performance with Direct Compile architecture
• Seamless mixing of VHDL and Verilog with Single Kernel Simulation
• Simplified portability and library maintenance made possible with machine-and simulator-version independence

Continue to Step 4 -- Hardware Implementation