Answers Database

M1.4 Ngdanno - Annotated delays for DP RAM produce sim results inconsistent with TRCE.


Record #3315

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
M1.4 Ngdanno - Annotated delays for DP RAM produce sim results
inconsistent with TRCE.



Problem Description:
A DP RAM case has been seen where TRCE reports delay through the SPO
as 7ns, but the annotated simulation shows the delay as 13ns.

This issue has been fixed and a patch is available.


Solution 1:

This issue is fixed by the latest M1.4 Core Tools patch
which is available in the XILINX Download Area:

ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt14.zip



End of Record #3315