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Record #3813 Product Family: Software Product Line: FPGA Implementation Problem Title: A1.4/F1.4 - PAR duplicates flops to create an output to output route-thru. Problem Description: PAR will sometimes duplicate flops to drive seperate sections of a net. This is considered an output to output route-thru. This is a problem when the input net is asynchronous, there is a chance that the flops will be clocked while the input is changing and the two flops could end up in different states. An environment variable (CM_EXCLUDE_XQYQ) has been created that disables the use of CLB Flop outputs for output to output route-thrus. Solution 1: This new feature is available in the latest M1.4 Core Tools Update available on the Xilinx Download Area: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol14_m14.tar.Z ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun14_m14.tar.Z ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp14_m14.tar.Z ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt14.zip To set the variable: setenv CM_EXCLUDE_XQYQ (work stations) set CM_EXCLUDE_XQYQ = TRUE (PCs) End of Record #3813
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