![]() | |
![]() ![]() ![]() ![]() ![]() ![]() ![]() |
Record #4060 Product Family: Software Product Line: FPGA Implementation Problem Title: M1.4 Map - Map creates TIMEGRPs in PCF file that are incorrect. Problem Description: A design was created with two timegroups (PCI_CLK and DSP_CLK) each with aperiod timespec assigned to them. The resulting .pcf has several BELs have incorrectly been put into both timegroups. Solution 1: This problem has been corrected in the latest Core Tools Update: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol14_m14.tar.Z ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun14_m14.tar.Z ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp14_m14.tar.Z ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt14.zip End of Record #4060
For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals! |
© 1998 Xilinx, Inc. All rights reserved Trademarks and Patents |