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Xilinx Answer #7677 : XPLA Logistics: Technical help on CoolRunner products.
Xilinx Answer #7676 : XPLA Logistics: CoolRunner data sheet location.
Xilinx Answer #7675 : XPLA Logistics: CoolRunner web page location.
Xilinx Answer #7673 : XPLA Logistics: Future of the existing CoolRunner devices at Xilinx
Xilinx Answer #7672 : XPLA2: Available number of I/O pins per fast module?
Xilinx Answer #7671 : XPLA2: Timing delays associated with the XOR.
Xilinx Answer #7670 : XPLA2: Usefulness of the hardwired XOR.
Xilinx Answer #7669 : XPLA2: Number of product terms per macrocell.
Xilinx Answer #7668 : XPLA2: Number of macrocells in a logic block presence of PAL and PLA.
Xilinx Answer #7667 : XPLA2: Fan-in size from the local ZIA to each logic block.
Xilinx Answer #7666 : XPLA2: Fan-in and fan-out size of a fast module to the Global ZIA.
Xilinx Answer #7665 : XPLA2: Delay time through the Global ZIA.
Xilinx Answer #7664 : XPLA2: Fast modules.
Xilinx Answer #7663 : XPLA2: Daisy-chain for configuration.
Xilinx Answer #7662 : XPLA2: Length of time for configuration or download.
Xilinx Answer #7661 : XPLA2: Configuration PROMs supported.
Xilinx Answer #7660 : XPLA2: Reserving device configuration pins using the fitter.
Xilinx Answer #7659 : XPLA2: Supported by XPLA Professional.
Xilinx Answer #7658 : XPLA2: Available devices and packages.
Xilinx Answer #7657 : XPLA2: JTAG programming.
Xilinx Answer #7656 : XPLA2: How to use the global clocks, global reset, and global tri-states in the XPLA2?
Xilinx Answer #7655 : XPLA2: Grouping signals in a fast module.
Xilinx Answer #7654 : XPLA2: Utilizing the hardware XOR.
Xilinx Answer #7653 : XPLA2: Size of download file and amount of device memory space needed for configuration.
Xilinx Answer #7652 : XPLA2: Configuration modes of the XPLA2 devices.
Xilinx Answer #7651 : XPLA2: Are the XPLA2 devices SRAM-based or EEPROM-based?
Xilinx Answer #7649 : XPLA1: Which pins require termination on the Coolrunner devices?
Xilinx Answer #7648 : XPLA1: Characteristics of I/O's during power up/down.
Xilinx Answer #7647 : XPLA1: Initial state of registers upon power up.
Xilinx Answer #7646 : XPLA1: Availability of inverted outputs (Q!).
Xilinx Answer #7644 : XPLA1: Fitter error when exceeding maximum number of clocks.
Xilinx Answer #7642 : XPLA1: What is the active signal polarity for Reset / Preset / Output Enable / Global Tri-State?
Xilinx Answer #7641 : XPLA1: Internal pull ups or pull downs.
Xilinx Answer #7640 : XPLA1: The XPLA fitter does not allow a pins associated with an asynchronous clock to be used as a standard I/O.L
Xilinx Answer #7639 : XPLA1: Hysterisis on inputs or clock pins.
Xilinx Answer #7637 : XPLA1: CoolRunner startup current or high current demands.
Xilinx Answer #7633 : XPLA1: Clock resources available
Xilinx Answer #7632 : XPLA1: Number of product available per macrocell.
Xilinx Answer #7631 : XPLA1: Number of macrocells in a logic block and presence of a PAL and PLA.
Xilinx Answer #7622 : XPLA1: ZIA fan-ins to each logic block.
Xilinx Answer #7621 : XPLA1: Recommended decoupling.
Xilinx Answer #7620 : XPLA1: Transparent latch in macrocells.
Xilinx Answer #7619 : XPLA1: Slew rate control on the outputs.
Xilinx Answer #7604 : XPLA Architecture: CoolRunners and internal weak pull-up resistors.
Xilinx Answer #7603 : XPLA Architecture: Assembly locations of CoolRunner devices.
Xilinx Answer #7602 : XPLA Architecture: Fast Zero Power FZP parts drawing too much current.
Xilinx Answer #7600 : XPLA Architecture: CoolRunners with internal terminations on the I/O.
Xilinx Answer #7599 : XPLA Architecture: Differences between PALs and PLAs.
Xilinx Answer #7598 : XPLA Architecture: Differences between CPLDs and FPGAs.
Xilinx Answer #7597 : XPLA Architecture: Fast Zero Power or FZP.
Xilinx Answer #7596 : XPLA Architecture: Applying signals to the CoolRunner's I/Os before power is applied.
Xilinx Answer #7595 : XPLA Architecture: Currently offered CoolRunners