File Archive: app_3rdparty

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Contents of /pub/applications/3rdparty
 
Applications Relating to Third Party interfaces

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  Filename                Size             File Description
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m1_hdl_src.tar.Z        107 Kb  VHDL and Verilog Example files to accompany the
			        Xilinx Synthesis and Simulation Design Guide
			        (for M1). Source code-only.
				For All Platforms
				Uploaded: 01-20-98
m1_hdl_src.zip          126 Kb  VHDL and Verilog Example files to accompany the
			        Xilinx Synthesis and Simulation Design Guide
			        (for M1). Source code-only.
				For All Platforms
				Uploaded: 01-20-98
m1_verilog.src.zip       62 Kb  Verilog example files to accompany the Xilinx
			        Synthesis and Simulation Design Guide (for M1).
			        Source code-only.
				For All Platforms
				Uploaded: 01-20-98
m1_verilog_src.tar.Z     55 Kb  Verilog example files to accompany the Xilinx
			        Synthesis and Simulation Design Guide (for M1).
			        Source code-only.
				For All Platforms
				Uploaded: 01-20-98
m1_vhdl_src.tar.Z        58 Kb  VHDL example files to accompany the Xilinx
			        Synthesis and Simulation Design Guide (for M1).
			        Source code-only.
				For All Platforms
				Uploaded: 01-20-98
m1_vhdl_src.zip          66 Kb  VHDL example files to accompany the Xilinx
			        Synthesis and Simulation Design Guide (for M1).
			        Source code-only.
				For All Platforms
				Uploaded: 01-20-98
m1_xsi_hdl.tar.Z      11223 Kb  Verilog and VHDL example files to accompany the
			        Synopsys (XSI) Synthesis and Simulation Design
			        Guide (for M1). Source, script and all design
			        files.
				For All Platforms
				Uploaded: 01-20-98
m1_xsi_hdl.zip         7683 Kb  Verilog and VHDL example files to accompany the
			        Synopsys (XSI) Synthesis and Simulation Design
			        Guide (for M1). Source, script and all design
			        files.
				For All Platforms
				Uploaded: 01-20-98
m1_xsi_verilog.tar.Z   5128 Kb  Verilog example files to accompany the Synopsys
			        (XSI) Synthesis and Simulation Design Guide (for
			        M1). Source, script and all design files.
				For All Platforms
				Uploaded: 01-20-98
m1_xsi_verilog.zip     3545 Kb  Verilog example files to accompany the Synopsys
			        (XSI) Synthesis and Simulation Design Guide (for
			        M1). Source, script and all design files.
				For All Platforms
				Uploaded: 01-20-98
m1_xsi_vhdl.tar.Z      6181 Kb  VHDL example files to accompany the Synopsys
			        (XSI) Synthesis and Simulation Design Guide (for
			        M1). Source, script and all design files.
				For All Platforms
				Uploaded: 01-20-98
m1_xsi_vhdl.zip        4169 Kb  VHDL example files to accompany the Synopsys
			        (XSI) Synthesis and Simulation Design Guide (for
			        M1). Source, script and all design files.
				For All Platforms
				Uploaded: 01-20-98
vstbsim.zip             191 Kb  App note and sample design files describing
			        Board-level simulation with OrCAD VST v1.20
				For All Windows
				Uploaded: 12-04-97