File Archive: app_misc

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Contents of /pub/applications/misc
 
Miscellaneous Programmable Logic Applications

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  Filename                Size             File Description
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bcdcnt.zip                59KB  ViewLogic Schematics for "Ten Digit
                                Synchronous BCD Counter", targeted for 3142a
counter.pld                1KB  Counter file mentioned on p.1-4 of XEPLD
                                Design Guide, April 1994
hd16bit.zip               17KB  High-density 16-bit counter and accumulator
                                hard macros (8 CLBs each)
hd16bitb.zip     	   9KB  High speed 16-bit counter (9 CLBs)
latch_9k.zip            203 Kb  Uploaded: 08-31-1998
			        Contains three examples of implementing
			        efficient combinatorial feedback latches in the
			        9500/XL family for Foundation 1.5. The examples
			        show the implementation in ABEL (LD_ABL.ZIP),
			        VHDL (LD_VHD.ZIP), and in SCHEMATIC
			        (LD_SCH.ZIP).
				Solution #: 4174
				For Win 95, Win NT 4.0
				SW Release: F1.5
				Category: Utility, CPLD
pc_isa.zip               49 Kb  Design files to accompany "Configuring FPGAs
                                over a Processor Bus" application note
				Uploaded: 09-16-96
psmfiles.exe              44KB  Viewlogic schematic files for "Dynamic Micro-
                                controller in an XC4000 FPGA" App note.
pwm.zip                    8KB  Viewlogic design files for "Pulse Width
                                Modulation in Xilinx Programmable Logic"
                                application note
                                For All Platforms
                                Uploaded: 12-02-96
rs-232.zip              244 Kb  Design files to accompany the application note:
			        RS-232 Based Communications with Xilinx FPGAs.
			        Contains Viewlogic schematics in Pre-Unified
			        Libraries and post-script files.
				For All Platforms
				Uploaded: 02-19-98