VirtexTM Series

Application Notes Data Book

Product Pages

Application Notes

Title	Ver.	Size	Reference Design
XAPP267:Parity Generation and Validation in Virtex-II Devices	1.0	46K
XAPP262: Quad DataRate (QDR) SRAM Interface for Virtex-II Devices	1.0	79K	PC: VHDL UNIX: VHDL
XAPP261: Data-Width Conversion FIFOs Using the Virtex-II Block RAM Memory	1.0	80K	PC & UNIX: VHDL & Verilog
XAPP258: FIFOs Using Virtex-II Block RAM	1.0	79K	PC & UNIX: VHDL & Verilog
XAPP256: FIFOs Using Virtex-II Shift Registers	1.0	47K
XAPP254: The Virtex-II SiberBridge	1.0	120K	PC: Verilog
XAPP253: Synthesizable 266 MBits/s DDR SDRAM Controller	1.0	154K	PC: Verilog
XAPP246: PowerPC 60X Bus Interface to a Virtex-E Device	1.0	164K	Reference Design
XAPP243: Bus LVDS with Virtex-E Devices	1.0	274K
XAPP242: Interfacing to Lara Networks Search Engine using Virtex Devices	1.1	76K	PC: Verilog UNIX: Verilog
XAPP241: Virtex-EM FIR Filter for Video Applications	1.1	45K
XAPP240: High-Speed Buffered Crossbar Switch Design using Virtex-EM Devices	1.0	78K
XAPP238: LVDS System Data Framing	1.0	81K
XAPP237: Virtex-E LVPECL Receivers in Multi-Drop Applications	1.1	95K
XAPP235: Virtex-E Package Compatibility Guide	1.3	40K
XAPP234: Virtex SelectLink  Communications Channel	1.1	92K
XAPP233: Multi-channel 622 Mb/s LVDS Data Transfer with Virtex-E Devices	1.2	261K	Reference Design
XAPP232: Virtex-E LVDS Drivers and Receivers: Interface Guidelines	1.0	175K
XAPP231: Multi-Drop LVDS with Virtex-E FPGAs	1.0	83K
XAPP230: The LVDS I/O Standard	1.1	69K
XAPP225: Data to Clock Phase Alignment	1.0	48K	Reference Design
XAPP224: Data Recovery in Virtex and Virtex-II Devices	1.1	59K	Reference Design
XAPP223: 200MHz UART with Internal 16-Byte Buffer	1.0	151K	Reference Design
XAPP222: Designing Convolutional Interleavers with Virtex Devices	1.0	115K	Reference Design
XAPP220: Linear Feedback Shift Registers for Wireless Applications	1.1	135K	Reference Design
XAPP219: Transposed Form FIR Filters	1.1	148K	PC: VHDL UNIX: VHDL
XAPP217: Gold Code Generators in Virtex Devices	1.1	125K	PC: VHDL & Verilog UNIX: VHDL & Verilog
XAPP216: Correcting Single-Event Upsets Through Virtex Partial Reconfiguration	1.0	107K
XAPP215: Design Tips for HDL Implementation of Arithmetic Functions	1.0	117K	PC: VHDL & Verilog UNIX: VHDL & Verilog
XAPP214: Virtex Device Quad Data Rate (QDR) SRAM Interface	1.0	53K	PC: VHDL UNIX: VHDL
XAPP213: 8-Bit Microcontroller for Virtex Devices	1.1	506K	PC: VHDL
XAPP212: CDMA Matched Filters Implementation in Virtex Devices	1.1	172K	PC: VHDL UNIX: VHDL
XAPP211: PN Generators Using the Virtex SRL Macro	1.1	121K	PC: VHDL & Verilog UNIX: VHDL & Verilog
XAPP210: Linear Feedback Shift Registers in Virtex Devices	1.2	86K
XAPP208: IDCT implementation in Virtex Devices for MPEG applications	1.1	45K	PC: Verilog UNIX: Verilog
XAPP205: Data-Width Conversion FIFOs using Virtex Block SelectRAM Memory	1.3	47K	PC:Verilog
XAPP204: CAM in Block Select RAM	1.2	102K	PC: VHDL & Verilog UNIX: VHDL & Verilog
XAPP203: Designing Flexible, Fast CAMs with Virtex Slices	1.1	75K	PC: VHDL & Verilog UNIX: VHDL & Verilog
XAPP202: CAM in ATM applications	1.2	141K	PC:VHDL UNIX: VHDL
XAPP201: An Overview of Multiple CAM Designs in Virtex Devices	1.1	46K
XAPP200:  Double Data Rate SDRAM	2.3	103K	PC: 64-bit PC: 16-bit UNIX: 64-bit UNIX: 16-bit
XAPP196: Interfacing a Virtex-E Device to a Pentium Processor	1.0	71K	Reference Design
XAPP192: Interfacing a Virtex-E Device to a MIPS Processor	1.0	99K	Reference Design
XAPP158: Powering Virtex FPGAs	1.3	46K
XAPP157: Board Routability Guidelines with Xilinx Fine-Pitch BGA Packages	1.0	1806K
XAPP155: Virtex Analog to Digital Converter	1.1	48K
XAPP154: Virtex Synthesizable Delta-Sigma DAC	1.1	52K
XAPP153: Status and Control Semaphore Registers Using Partial Reconfiguration	1.0	181K	PC:Verilog
XAPP152:  Virtex Power Estimator User Guide	1.1	49K
XAPP151: Virtex Configuration Architecture Advanced User Guide	1.4	249K
XAPP139: Virtex Configuration and Readback through Boundary Scan	1.2	97K
XAPP138: Virtex Configuration and Readback	2.3	233K
XAPP137:  Configuring Virtex FPGAs from Parallel EPROMs with a CPLD	1.0	93K	PC:VHDL & Verilog
XAPP136:  Synthesizable 200 MHz ZBT(TM) SRAM Interface	2.0	44K	PC:VHDL PC:Verilog
XAPP135: Virtex I/V Curves for Various Output Options	1.0	26K
XAPP134:  Virtex Synthesizable High Performance SDRAM Controller	3.0	104K	PC:VHDL PC:Verilog UNIX:VHDL UNIX:Verilog
XAPP133:  Using the Virtex SelectI/O Resource	2.5	231K
XAPP132:  Using the Virtex Delay-Locked Loop	2.3	88K	PC:VHDL & Verilog
XAPP131:  170MHz Synchronous and Asynchronous FIFOs Using the Virtex Block SelectRAM+ Features	1.4	46K	PC & UNIX: VHDL & Verilog
XAPP130:  Using the Virtex Block SelectRAM+ Features	1.4	95K

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Data Book

Title	Size
Virtex 2.5V Field Programmable Gate Arrays Data Sheet	457K
Virtex-E 1.8V Field Programmable Gate Arrays Data Sheet	1461K
Virtex-E 1.8V Extended Memory Field Programmable Gate Arrays Data Sheet	1172K
Virtex-II 1.5V Field Programmable Gate Arrays Data Sheet Page
Virtex-II Platform FPGA Handbook and Data Sheet Page

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Product Pages

Virtex Series FPGAs Product Page
Virtex-II Platform FPGA Product Page