Xilinx Reuse Field Guides

---

Xilinx Design Reuse Field Guide

Xilinx, and Qualis Design Corporation have partnered to provide the industry's first Internet based reuse methodology field guide for both FPGA and ASIC design. The FPGA Reuse Field Guide contains leading design techniques for VHDL and Verilog based designs.

ASIC and FPGA methodologies are merging as the size and speed of FPGAs approaches that of mainstream ASICs. Having a common methodology allows for easy migration from one technology to another and maximizes the ability to migrate design between technologies. Through this migration, intellectual property (IP) technology can be used and reused among designers to shed critical time in the production cycle. This FPGA Reuse Methodology Field Guide is more than just a coding style guide. It provides an overview of the economic issues involved with design reuse, detailed information about project specifications, project management and organization, and project verification and qualification.

The Xilinx Reuse Field Guide is available for download from the Design Reuse Resource Lounge. To access this lounge you will need to register.

The Xilinx IP Internet Capture tool is available for download from the Design Reuse Resource Lounge. To access this lounge you will need to register.

• To Register Please Click Here and fill out the registration form
  

• If you have already registered, Click Here for the Xilinx FPGA Reuse Field Guide
  

FPGA Supplement to Reuse Methodology Manual

The Xilinx Design Reuse Methodology for ASIC and FPGA Designers manual is intended for designers who want a common strategy for reusing intellectual property, regardless of whether it was developed for ASICs or for FPGAs. The Xilinx supplement to the Synopsys and Mentor Graphics RMM manual provides an overview of FPGA system level features and contains general RTL synthesis coding guidelines that have the most impact on improving system performance. The guidelines and coding styles presented are built upon the discipline of good design. By coding with these guidelines an ASIC designer will find that they have improved their ASIC code as well as creating an FPGA friendly implementation.