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The single and 32 channel HDLC controller cores are optimized, low cost, ITU compliant solutions to accelerate
product time-to-market for data networking applications.
- Single and 32-Channel HDLC Cores for Virtex, Virtex-E and Spartan-II
- HDLC Solutions available now for prices
below ASSPs
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HDLC Lounges (Customers only)
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Overview
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Xilinx provides fixed netlist LogiCORE solutions for both the single channel and the 32-channel HDLC controller
cores for data networking applications. By using a Xilinx HDLC solution, users can significantly reduce implementation
cost and accelerate time-to-market compared to fixed function Application Specific Standard Product (ASSP) alternatives.
These cores are available immediately and support Xilinx Virtex, Virtex-E and Spartan-II FPGA families. These new
cores create an ideal solution for many data networking markets such as packet over SONET, cable modems, frame
relay switches and video conferencing over ISDN.
Click here for FAQ, data sheets, overview presentations, and other links. |
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The Basics of HDLC
HDLC, high-level data link control, is a popular ITU defined protocol used in data networking applications such
as cellular base station switch controllers, frame relay switches, high bandwidth WAN links, xDSL and modem error
correction. This protocol is responsible for transmitting data between network points. It organizes data into units,
following the bit oriented packet transmission mode, and sends it across a network to a destination that verifies
its successful arrival. The data stream and transmission rate is controlled from the network node (PCM highway
clock) with a back pressure mechanism. This eliminates additional synchronization and buffering of the data at
the network interface. Different variations of the protocol are used in different networks. For example, ISDN's
D-channel uses a slightly modified version of HDLC.
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Core Features
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- Fully compliant with ITU Q.921, X.25, ISO/IEC 3309 and ISDN Channels B and D
- 8 or 16-bit, selectable all frames and broadcast modes
- 16 and 32-bit CRC (FCS)
- Both cores suited for multiple HDLC scaling
- Full duplex operation, with 32 channel multiplex capability
- TI/E1 stream support using external mux/de-mux
- Generic 8-bit host interface for control and status registers
- Fully synchronized with bit-rate
- Optimized for Virtex, Virtex-E and Spartan-II architectures
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a Xilinx AllianceCORE partner
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Implementation Examples
| Target Device HDLC1 |
Virtex
XCV100-4
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Virtex-E
XCV100E-8
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Spartan-II
XC2S100-5
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| Size |
216 Slices
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216 Slices
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216 Slices
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| Speed |
61.5 MHz
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85.9 MHz
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64.1 MHz
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| Target Device HDLC32 |
Virtex
XCV100-6
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Virtex-E
XCV100E-6
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Spartan-II
XC2S100-6
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| Size |
513 Slices
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523 Slices
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523 Slices
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| Speed |
47.2 MHz
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49.5 MHz
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56.1 MHz
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Obtainable without stringent place and route constraints
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Ordering information
| Part number |
Product Description |
Supported Devices |
| DO-DI-HDLC1 |
Single-Channel HDLC Core |
Virtex, Virtex-E, Spartan-II |
| DO-DI-HDLC32 |
32-Channel HDLC Core |
Virtex, Virtex-E, Spartan-II |
Please contact your local Xilinx Sales Office
for pricing information or to place an order. Xilinx LogiCORE HDLC products
are provided as a single-use license under the  Xilinx
Core Project License Agreement.
Additional Information
 to view the PDF files on this page.
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