Subject: The Virtex^TM family and the Spartan^TM -II family contain a design process related marginality that may affect functionality of the distributed (LUT-based) SelectRAM when configured in a 32x1 mode. It is recommended that customers do not use these devices in this mode. 

Customer Update XCU2000-02 was published in September, 2000 detailing the design process marginality. This PCN provides detail on product traceability and availability for the fix of this design process marginality.

Products Affected: All Virtex production devices, all Spartan-II engineering (ES) devices, and some Spartan-II (XC2S150)  production devices (non-ES) are affected. This design marginality does not affect any Virtex-E production devices. This design marginality does not affect any designs configured in a 16x1 mode. 

Change Description: Xilinx has implemented a fix for this design process marginality. The fix widens the write strobe signal to accommodate a larger variation of memory cells.

Reason for Change: The design process marginality was identified in all Virtex and Spartan-II products. 

Product Traceability and Key Dates: For Virtex devices, customers requiring the 32x1 fix need to order product with SCD0693. This SCD shall be top marked with product available beginning May 2001. No action is required from customers not affected by this design marginality. 

For Spartan-II devices other than the XC2S150, all production devices have the fix implemented for this marginality. For the XC2S150 devices, all product shipped beginning with date code 0101 has the fix implemented. In summary, any product shipments from this date forward will have the fix implemented for this design marginality.

Response: No response to this notification is required. Requests for additional data or support should be made within 90 days of notification. Please address any questions you may have via email at pcn@xilinx.com, or directly by fax at 408 369-1718.