Q: What are the WebPOWERED applications?
A: WebPOWERED is a Xilinx concept aimed at empowering designers. The idea is to enable designers to create more complex PLD designs quicker and easier than in the past. The Web applications comprised of WebPACK ISE and WebFITTER are one aspect, while in-depth application notes and Web-based support round out the entire picture.

Q: What devices are supported in the WebPOWERED applications?
A: WebPACK ISE supports all Xilinx CPLD families (XC9500 and CoolRunner) as well as the Virtex V300E and entire line of Spartan II devices.  WebFITTER currently support all XC9500 and CoolRunner device families. In addition, WebFITTER also provides support for some of the more commonly used Simple PLDs such as 22V10, 20V8, 16R8, and many more.

Q: What software do I use to program Xilinx CPLDs?
A: The XC9500 JTAG Programmer module in WebPACK is used for programming XC9500 series devices. The XCR Programmer module in WebPACK is used for programming XPLA1 and XPLA3 series devices with limited support of the XPLA2 series. Both the XC9500 and XCR Programmer modules provide the following features: 

• Setup of JTAG chain 
• Port/cable setup 
• ATE vector generation 
• Safe programming modes 

Q: Is there support available for Web-based applications?
A: Web-based tools utilize Web-based support. Web-based support is provided by the same hotline experts that serve Xilinx Foundation and Alliance customers, but Web questions are assigned a lower priority than full paying software customers. All questions will be answered within 10 days. For faster service, direct support packages are available for Web tools and may be purchased by calling your local Xilinx representative. 

Q: Is XPLA Pro still available?
A: No. WebPACK ISE now contains support for the complete line of CoolRunner devices.

Q: What is WebPACK ISE, and how does it differ from WebPACK?
A: WebPACK is a collection of free, independent, downloadable software modules. WebPACK ISE is the next generation of WebPACK. Currently the following modules are available in WebPACK ISE: 

• Design Entry and Synthesis module for ABEL, VHDL, or Verilog designs 
• XC9500 Device Series Fitter module 
• Xilinx CoolRunner (XCR) Device Series Fitter module 
• Xilinx FPGA Device Series Fitter module
• JTAG Programmer module
• XCR Programmer module
• The backPACK modules consisting of
• MTI's ModelSim Xilinx Edition Starter simulation software
• StateCAD by Visual Software Solutions
• HDL Bencher by Visual Software Solutions
• XC9500 ChipViewer
• CPLD Schematic Libraries

Q: How is simulation supported? 
A: HDL simulation is supported by Model Technology Inc. simulation software which is fully integrated into WebPACK ISE. MTI's MXE Starter software is available as a backPACK module. Upgrades are available from either Xilinx or MTI and will work seamlessly in the WebPACK ISE environment. 

WebPACK ISE also supports a functional simulation for ABEL using BLIFSIM.  ABEL test vectors need to be created in conjunction with the design, and ABEL BLIF flow should be selected for the synthesis tool. For more information on this, please refer to the Test Vector and Simulation sections of WebPACK Help. 

Q: Is schematic entry supported? 
A: The Design Entry and Synthesis module contains a graphical HDL design entry tool. This may be used to create and connect HDL blocks together to form a top level schematic. WebPACK ISE's primary focus is HDL entry, design and synthesis.  Should a user desire to create a schematic design using logic primitives, CPLD logic libraries are available as a backPACK module. 

Third party schematic designs are supported using WebPACK's EDIF netlist entry.  Foundation designs (both schematic and mixed schematic/HDL) which target the 9500 library are supported. Foundation users targeting the XC9500 should complete the implementation in Foundation. Foundation users targeting the XCR series must create an EDIF netlist file in Foundation and import the EDIF net list file into WebPACK. 

Q: What features are available in WebPACK ISE?
A: WebPACK contains the following features: 

• Multiple design entry formats 
• Verilog, VHDL
• Third party EDIF netlist files
• ABEL
• Altera TDO files
• Produces VHDL and Verilog design timing models
• Fitters for the XC9500, CoolRunner (XCR), Virtex V300E and Spartan II devices 
• JTAG Programmer and XCR Programmer
• Graphical constraints entry and logic placement viewing for the XC9500 family utilizing ChipViewer and for the FPGA devices using FloorPlanner
• Third party tools such as MTI's ModelSim Xilinx Edition Starter software, VSS's StateCAD, and HDL Bencher software seamlessly integrated into the Project Navigator design environment
• Graphical HDL entry as well as schematic capture capability

Q: Can I download the modules in parallel, and is there any special order for installation?
A: Yes, the single file download installation option for multiple modules may be selected in parallel. The parallel operation will reduce the download speed proportionally. The advantage is that the selected modules may be saved to a convenient location in parallel for installation at another time. The disadvantage is that if your Internet connection gets interrupted, those affected modules will have to be downloaded again. 

No, there is no special order that the modules have to be installed in. The modules are designed to be independent with the exception of the CoolRunner Device Fitter module. This module needs the Design Entry and Synthesis module before it can be used. 

Q: Does WebPACK ISE work with third party synthesis tools?
A: Yes, the option is present to have the Xilinx environment variable set automatically when installing the 9500 series or XCR series family fitters, or you may add the following lines in your autoexec.bat file: 

set XILINX=C:\XILINX_CPLD (or directory location, if different) 
set PATH=%PATH%;%XILINX%\bin\nt;

Q: What operating system(s) does WebPACK ISE work on?
A: WebPACK ISE is primarily a PC-based tool. Support under Windows 98 and 2000 have been used in testing. Xilinx does not recommend installing under Windows 95 since no testing under this operating system was performed. Unix versions of the fitting tools are also available in 3.1WP1.0 and may be found on the download page under the Unix modules section.

Q: Can WebPACK ISE be installed on the same system as WebPACK? As Foundation ISE?
A: Yes. The unique bootloader used during the execution of WebPACK enables it to identify which software version was invoked. The only catch is that all versions of the software must be installed in different directory locations.

Q: Is XPLA Pro still available?
A: No. WebPACK ISE now contains support for the complete line of CoolRunner devices.

Q: What is a "backPACK," and do I really need it? 
A: The backPACK concept was created to group additional design tools that would be useful, but not necessary, in the process of completing a PLD design. The separation of the backPACK tools minimizes the Internet bandwidth required to complete a design.

Q: Are there limitations on the third party tools included with WebPACK, and if so, what are they?
A: These tools are starter versions offered by third party vendors such as Model Technology Inc. and Visual Software Solutions. The scaled down versions demonstrate the capabilities of their software and provide an indication of whether the full scale tool would be useful for the designer.

The limits for ModelSim Xilinx Starter Edition are 500 lines of debuggable code.  Beyond this limit, the processing begins to slow down, but does not stop. The usefulness of this software is going to depend on coding style and type of simulation (either functional or timing) that is desired.

Visual Software Solutions tools comprised of StateCAD and HDL Bencher follow the limits below:

Unregistered
------------------
StateCAD: 6 states, 16 transitions, 2 logic equations
Bencher: 12 signal assignments, 6 ports, max bus width (port) 8 bits

Registered
------------------
StateCAD: 10 states, 20 transitions, 8 logic equations
Bencher limit is 21 assignments (other limits dropped)

Both MTI and Visual Software Solutions offer registered users a discount on full software support purchases.

Q: Does WebPACK ISE work with third party synthesis tools?
A: Yes, the option is present to have the Xilinx environment variable set automatically when installing the 9500 series or XCR series family fitters, or you may add the following lines in your autoexec.bat file: 

set XILINX=C:\XILINX_CPLD (or directory location, if different) 
set PATH=%PATH%;%XILINX%\bin\nt;

Q: What third party programming support is available for the Xilinx CPLDs?
A: The following third party programmer vendors currently support both the CoolRunner (XCR) and XC9500 CPLD families: BP, Data I/O, Hi-Lo, Tribal, and Xilinx.  Additional  vendor support for Xilinx CPLD families varies depending on product line and family. For a detailed listing of device and package support, please visit our Third Party Programmer Support Web page.  Please note that this page will be updated frequently.
Note: The XPLA3 family is programmed using ISP through the JTAG port. Support by third party programmers is in development. 

Q: What is WebFITTER?
A: The WebFITTER is a free Web-based CPLD design fitting software tool.  WebFITTER allows logic designers to evaluate and design Xilinx CPLDs  using the latest version of Xilinx software. Fitting and device programming results can be obtained in minutes across the Web. WebFITTER also allows users to receive an immediate price quote for the device being targeted. You can register and use WebFITTER today. 

Q: What features are available in WebFITTER? 
A: See the following table:

Products Supported:	5V	XC9500, XCR22V10, and XPLA1(XCR5000)
	3.3V	XC9500XL, XCR22LV10, XPLA1(XCR3000A), XPLA2 (XCR3000-SRAM based),  XPLA3 (XCR3000XL)
	2.5V	XC9500XV
	---	Simple PLDs (22V10, 20V8, 16R8 etc.)
Accepted Design Entry Formats:	VHDL Verilog ABEL EDIF TDO TDF NCR XNF
Constraints File (Optional):	User specified constraints are accepted.
Device Selection Options:	By density, package, speed, voltage or auto select.
Output:	Timing report Fitter report Programming file (JEDEC) Timing simulation model  (VHDL, Verilog or EDIF)

---

General Questions

Q: Is XPLA Pro still available?
A: No. WebPACK ISE now contains support for the complete line of CoolRunner devices.

Q: How is simulation supported?
A: HDL simulation is supported by Model Technology Inc. simulation software which is fully integrated into WebPACK ISE. MTI's MXE Starter software is available as a backPACK module. Upgrades are available from either Xilinx or MTI and will work seamlessly in the WebPACK ISE environment. 

WebPACK ISE also supports a functional simulation for ABEL using BLIFSIM.  ABEL test vectors need to be created in conjunction with the design, and ABEL BLIF flow should be selected for the synthesis tool. For more information on this, please refer to the Test Vector and Simulation sections of WebPACK Help. 

Q: Is schematic entry supported?
A: The Design Entry and Synthesis module contains a graphical HDL design entry tool. This may be used to create and connect HDL blocks together to form a top level schematic. WebPACK ISE's primary focus is HDL entry, design and synthesis.  Should a user desire to create a schematic design using logic primitives, CPLD logic libraries are available as a backPACK module. 

Third party schematic designs are supported using WebPACK's EDIF netlist entry.  Foundation designs (both schematic and mixed schematic/HDL) which target the 9500 library are supported. Foundation users targeting the XC9500 should complete the implementation in Foundation. Foundation users targeting the XCR series must create an EDIF netlist file in Foundation and import the EDIF net list file into WebPACK. 

Q: What software do I use to program Xilinx CPLDs?
A: The XC9500 JTAG Programmer module in WebPACK is used for programming XC9500 series devices. The XCR Programmer module in WebPACK is used for programming XPLA1 and XPLA3 series devices with limited support of the XPLA2 series. Both the XC9500 and XCR Programmer modules provide the following features: 

• Setup of JTAG chain 
• Port/cable setup 
• ATE vector generation 
• Safe programming modes 

Q: What should I do if I forget my registration password?
A: Should you forget your password, a new, randomly generated password can be obtained through e-mail by following the links on the registration page or by clicking here.