 |
|
StateCAD/StateBench
- Purchase
Foundation ISE Base Express including StateCAD/StateBench Xilinx Edition
and HDL Bencher* for $695!
- Click here
for VSS product technical support and licensing.
Product Details
StateCAD Features at a Glance
|
|
StateCAD
automates state machine development in VHDL and Verilog. Using the
FSM wizard, complex, concurrent state machines are specified. Random
logic and Mealy/Moore outputs are added to complete the design.
|
|
|
To meet tough product requirements, StateCAD optimizes the code it generates for speed, area, loading and more.
Vendor specific code generation guarantees the design will function, with
your tools, as you expect. StateCAD had code generators for all top
name products from Synopsys, Viewlogic, Altera, Xilinx, Mentor and more! |
|
|
StateCAD
automatically analyzes your designs for over 200 logic and syntax
problems. Because errors are detected before code generation, they are eliminated before you get to simulation, reducing development
costs automatically! |
|
|
Once
a design is error free, StateCAD translates it to VHDL, Verilog, Abel,
Altera or C. StateCAD facilitates design migration.
Just choose the new optimizations, HDL, and generation preferences,
then StateCAD
will update the code! |
[Back to top]
State Machine Wizard
 |
Typical designs begin
with the State Machine Wizard, which helps you develop the initial
state machines. Next, use the Optimization Wizard to maximize performance
for the target device. Finally, you implement the details. Once the
design is completed, it is analyzed and translated to HDL, verified,
and a test bench is created.
[Back to top]
FSM Wizard
 |
The FSM wizard allows
you to quickly create arbitrary state machines in one easy step.
Manual drawing is eliminated. This wizard allows you to select
the layout and reset mode for the state machine. The wizard
then creates the state machine, places it into your drawing,
automatically assigns state names, and resets. |
[Back to top]
Customize FSMs
| After placing a
skeleton design into the diagram window, you modify state names,
update conditions, and assign outputs. A complete design consists
of many state machines and associated logic. Additional state
machines are added in the manner just described. |
|
|
[Back to top]
Logic Wizard
 |
The Logic
Wizard automatically creates data flow structures including
shifters, registers, latches, counters and muxes. Logic
can be added to states (Moore), transitions (Mealy), and
as random logic.
 |
|
| The Logic
Wizard automatically creates data flow structures including
shifters, registers, latches, counters and muxes. Logic can
be added to states (Moore), transitions (Mealy), and as random
logic. |
[Back to top]
Optimize Speed
& Area
 |
This
Wizard asks a number of questions to help achieve your performance
goals. |
[Back to top]
Generate HDL
 |
StateCAD automatically
translates state diagrams and data flow logic to synthesizable
VHDL, Verilog, Abel-HDL, Altera-HDL, and C. Signals are automatically
defined, ports are created, the correct libraries for the target
synthesis tool are specified and state assignment is resolved.
At any time in the design process you may switch HDLs, such
as when porting a design from an FPGA to an ASIC. |
[Back to top]
Compatibility
 |
| VHDL
and Verilog are supposed to be standard HDLs that yield uniform
results across tools. In reality this is not the case. Each
synthesis tool has style guidelines that must be rigidly followed
to yield efficient results. Also, the synthesis tools have unique
bugs, which are automatically worked around by StateCAD (and
StateBench) – so you don’t have to! |
[Back to top]
Eliminate Bugs
| After
optimization, the design is analyzed for problems. StateCAD
identifies over 200 problems including stuck at states, conflicting
conditions, and output driver conflicts. Because errors are
caught prior to HDL translation, your designs are much more
robust, and logically consistent. In fact, StateCAD will not
produce HDL until your design is syntactically flawless, semantically
valid, and logically correct! |
 |
 |
[Back to top]
Documentation
 |
Good documentation
greatly improves the exchange of ideas. To facilitate communication,
StateCAD (and StateBench) allows images to be exported to standard
documentation tools including Microsoft® Word and Wordperfect®.
StateCAD includes the high power documentation features you
expect from design tools including print preview, automatic
headers, page breaks, and clip board support (meta files and
bitmaps). |
[Back
to top]
Verify Behavior
 |
| StateCAD comes with
a built in simulator, StateBench, which automates behavioral
verification. Just click a sequence of states to validate a
path. In the example below, five mouse clicks causes the state
machine to be initialized and verified. In user assisted mode,
a sequence of small paths are defined and walked automatically,
making state machine verification a snap! |
[Back to top]
*HDL Bencher
v1.0 only. HDL Bencher v2.0 available only for purchase separately.
|
|
