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Can the Mode pins be driven High after Boundary Scan configuration?
What are the differences between Spartan-II engineering samples and the production product, regarding JTAG?
Can the Spartan-II devices be configured through the JTAG port?
How can the Spartan-II DLL be used to multiply the frequency of a clock signal by a factor of four?
What are the differences between the Spartan-II family and Spartan-XL family?
Are Spartan-II FPGAs pin-to-pin compatible to prior Spartan Series product offerings?
Is the new Spartan-II family footprint compatible with the Virtex family devices?
What are the differences between the Spartan-II family and the Virtex family since the two are based on the same architectures?
What are the architectural differences between the Spartan-II, Spartan-XL and Spartan families of FPGAs?
What routing advantages does the Virtex architecture provide for the Spartan-II family?
Are the Spartan-II devices bitstream compatible with the Virtex devices?
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