| FOR IMMEDIATE RELEASE
XILINX AND XENTEC ANNOUNCE UTOPIA LEVEL 3 INTERFACE CONTROLLER CORES Further utilization of communications market now possible through first FPGA-based UTOPIA Level 3 Master Cores SAN JOSE, Calif., June 5, 2000—Xilinx, Inc., (NASDAQ: XLNX) and Xentec, Inc. of Ontario, Canada, announced the immediate availability of four new AllianceCORETM products for use in Xilinx VirtexTM series FPGAs. The cores include UTOPIA Level 3 master (ATM-side) and slave (PHY-side) transmitter and receiver interface controllers. These cores target cell-based communications applications including Asynchronous Transfer Mode (ATM) systems. “Networking and communications companies continue to be a strong market for Xilinx programmable logic,” said Mark Bowlby, manager of the AllianceCORE program at Xilinx. “These new cores provide a programmable UTOPIA Level 3 solution for the rapidly expanding ATM market.” All of the Xentec UTOPIA cores are fully compatible with the ATM Forum's UTOPIA Level 3 specification. The cores are flexible and can be configured for 8-, 16- and 32-bit bus widths and cell formats from 52- to 56-octets. The ATM-side controller cores can support one PHY device in single-PHY (SPHY) mode or up to 32 PHY devices in multiple-PHY (MPHY) mode. While the Utopia Level 3 specification requires only 100 MHz performance, the ATM-side cores in Virtex series FPGAs achieve over 150 MHz operation. The PHY-side interfaces support FIFO buffer sizes from 2 to 64 cells. The FIFO buffers are constructed using Virtex on-chip Block SelectRAM. “The Virtex architecture made the implementation of these cores quite easy,” said Xerxes Wania, President and CEO of Xentec. “The completed designs exceed the clock rates required for specification compliance and the on-chip block RAM helps create a compact, single-chip solution.” The Virtex series improves upon the FPGA standard for system-level design with multiple I/O standards support, clock signal synchronization, and multiple-memory resources. By using the system integration features of Virtex devices, users should be able to reduce their overall design complexity, component count, and total system cost. Pricing and Availability All of these cores can be purchased directly from Xentec, Inc. The source code versions of the cores are completely configurable. Xilinx-optimized netlist versions are also available and Xentec can preconfigure them to customer specifications. The list prices for individual netlist cores start at $6000, with a price of $20,000 for the entire netlist set. Datasheets can be downloaded from the Xilinx IP Center, a comprehensive, searchable resource for system-level intellectual property and services. About Xentec Xentec, Inc. provides comprehensive FPGA and ASIC design services, integration expertise, and technology for the product development requirements of the world's leading electronics companies. Founded in 1995, Xentec's mission is to be the leading provider of analog/digital integrated circuit design services and Intellectual Property used in System-on-Chip (SoC) based integrated circuits for all facets of the electronics industry. The company is head quartered in Oakville, Ontario and is privately funded. More information about the company, its products, and services may be obtained from the World Wide Web at www.xentec-inc.com. For inquiries regarding Xentec cores and services please contact sales@xentec-inc.com About Xilinx Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com. —30— #0052
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