Q. What new applications will the Virtex-II family be able to address?
The Virtex-II family contains routing, memory, and logic constructs to support high performance applications in networking, wireless base-stations, mass storage, and video servers. For example, Virtex-II devices are being used to implement forward error-correction, network switch fabrics, echo cancellation, and video-on-demand servers.

Q. When will the family be sampling and in full production and what will the density range include?
The Virtex-II family includes members ranging in density from 40,000 up to 10 million system gates. The first members of the Virtex-II family, the XC2V40^TM, XC2V1000^TM, XCV3000E^TM and XC2V6000^TM devices are sampling now with the rest the family sampling by mid-2001. The entire Virtex-II family will be in full production by 3Q01. 

Q. What is the anticipated pricing for this family when it first samples?
Pricing for the XC2V40, XC2V1000, and XC2V6000 devices will be less than $10, less than $75, and $1200, respectively, in high volume for end of 2001.

Q. What types of packages will be available for the Virtex-II family?
The Virtex-II family is developed to support both standard wire-bond packages as well as leading-edge flip-chip packages with pin counts ranging from 144 to 1517 pins. The flip-chip package accommodates more I/O pins than the traditional wire-bond package by using internal chip area for package connections. Furthermore, the cavity-up nature of flip-chip packages allows superior thermal dissipation through the top of the package. Both the I/O pin-count and thermal advantages are important for complex designs to 10 million system gates and beyond.

Q. What software is available to support the Virtex-II family now?
Design software has been available since mid-2000 in the Xilinx Foundation Series^TM and Alliance Series^TM version 3.1i release, and as well as synthesis software from the leading EDA Alliance partners.

Q. What IP will be available for this family?
A wide selection of IP cores has been available for the Virtex-II family for more than six months. Focus areas for IP core availability include networking and digital signal processing fields, as embodied by SystemIO^TM and XtremeDSP^TM corporate initiatives. IP cores for RapidI/O, POS PHY Level 4, Flexbus 4, Lightning Data Transport (LDT) are planned for release during early 2001.

Q. Do you use copper in this technology?
Yes, the Virtex-II process uses copper for the top two metal layers.

 Q. Why don't you use all the levels of copper? Does this mean that those parts with all layer copper have better performance?
No, we have not seen significant gain in performance in using all layer copper. The new Active Interconnect^TM technology has significantly improved the overall performance. We have added two copper layers to minimize skew on the clock networks and to minimize I/R drops on long metal lines. Devices without a segmented routing architecture, i.e. long lines, may need copper on all layers.

Q. When is Xilinx expecting to ship the ten million gates parts?
With the shipment of the XC2V6000 device, Xilinx will have density leadership well into late 2001. We will deliver the 2V10000 device late in 2001 based on the needs of our customers.

Q. What is Xilinx solution for high-speed serial?
Xilinx has already licensed the pertinent technology from Conexant and we will deliver a 3.125 Gbps solution in 2001.

Q. Will this family have the embedded PowerPC from IBM? When will that be available? 
No, the current Virtex-II family does not have embedded processor. The Virtex-II family is the first Platform FPGA to incorporate the IP-Immersion^TM fabric that not only provide the ability to integrate a variety of soft IP, but also has the capability of embedding hard IP cores such as processors and Gigabit serial I/Os in future Virtex-II families schedule for late 2001. 

Q. How does this family represent a Platform FPGA?
The Platform FPGA is a solution that provides a single platform easily customizable to system connectivity, DSP and data processing applications. The new Virtex-II family incorporates enhanced routing and memory resources within the FPGA fabric to handle higher levels of data traffic and many innovative new system features (embedded multipliers, SystemIO, XCITE, and DCM) to realize the vision set forth by the Xilinx Platform FPGA initiative. 

Q. What are the key differences between Virtex-II and Virtex-E families?
The Virtex-II family extends the performance and density of the Virtex-E family, with significantly improvements to the FPGA switch fabric to handle the high level of logic integration and performance. In additions, Virtex-II FPGAs offer significant improvement in LVDS support to enable support for latest communication standards such as POS PHY Level 4, RapidI/O, LDT, and etc. The XCITE and DCM features are also first time innovations in Virtex series. 

Q. Is there a migration path to Virtex-II from its Xilinx predecessors?
In order to support the new system-level features in the Virtex-II family, there will be no package pin-out migration path from Virtex-E to Virtex-II designs. The Virtex-II packages are optimized for new I/O standards and capabilities such as the XCITE feature, and they are not compatible with previous Virtex pinouts. Virtex users will need to relay-out their boards to take advantage of the new features provided by the new Virtex-II solution. However, the users can re-target their Virtex-E designs to the new family in a straightforward manner. HDL source code may be recompiled using a new target device. Designs with IP cores may be updated by re-running the Coregen program. 

Q. What are the Xilinx IP-Immersion and Active Interconnect technologies and what are the benefits?
Xilinx Active Interconnect technology, built on the strength of the fourth generation segmented routing technology, provides full buffering at each routing interconnect point. This eliminates the variable routing delay effects of conventional interconnect architectures, where the total routing delay depends on the fan-out. With the conventional interconnect architecture, the routing delay of a particular node may be changed during design iteration, which makes complex designs like the ten million-system gates design impractical. In contrast, Active Interconnect technology allows precise delay calculations that are generally independent of signal fan-out. For complex IP-based designs, Active Interconnect technology allows predictable inter-IP routing delays to facilitate easy integration of multiple complex IP blocks.

Q. How does this family compare to competitors' offerings of similar densities?
The Virtex-II devices are built to support the unique challenges of logic efficient and routing for gate densities to ten million system gates. In particular, the Xilinx patented segmented architecture scales well to higher densities, which allows silicon efficient architectures to be defined to that level. To date, there are no other programmable logic offerings that can match the density.

Q. Are there plans for any new I/O standards to be supported?
The Xilinx plans for I/O support include physical layer support for the following popular high-bandwidth interconnect standards and applications: 

• Lightning Data TransportTM (LDT): A chip-to-chip interconnect that provides much greater bandwidth per I/O. It can achieve a bandwidth from 6.4 Gb/sec per eight wire link width, and can support up to 32 links. Applications include boards utilizing PCI and SIO, for example PC motherboards. 
• POS-PHY (PL4): A 13.3Gb/sec parallel link layer to physical layer interface for packet and cell transfer over SONET for OC-192c and 10 Gb/sec Ethernet applications. It is a 16-bit point-to-point interconnect with 832 Mb/sec per bit signaling utilizing double data rate clocking.
• InfiniBandTM: Promoted by an association comprising industry's leaders such as, Compaq, Dell, HP, IBM, Intel, Microsoft and Sun Microsystems, the focus is to develop a new common I/O specification to deliver a channel based, switched fabric technology. The newly designed interconnect utilizes a 2.5 Gb/sec wire speed connection with one, four or twelve wire link widths. Applications include remote storage devices and servers. 
• XAUI: A quad transceiver utilizing 3.125 Gb/sec serial links to create a 10-gigabit attachment unit interface (XAUI). Multiple XAUI interfaces can be implemented to allow a single chip to interface to both 10-Gigabit Ethernet and OC-192c. 
• Fibre Channel: A high-bandwidth serial standard offering 1.06 Gb/sec baud rates scalable to 2.12 or 4.24 Gb/sec. Capable of carrying multiple existing interface command sets, including Internet Protocol (IP), SCSI, IPI, HIPPI-FP, and audio/video. 
• Gigabit Ethernet + 10 Gbit Ethernet: This includes devices compliant with the IEEE 802.3 alliance. Applications include LANs and access and aggregation equipment in the Internet edge space. 
• ATM (OC-12, OC-48, OC-192): This includes support for OC-12 (622 Mbps), OC-48 (2.4 Gb/sec) and OC-192 (10Gb/sec). Applications include WANs, MANs, and access and aggregation equipment in the Internet edge space. 
• RapidIOTM: A next-generation switched-fabric interconnect architecture for embedded systems that is optimized for both high bandwidth and low latency. Initial implementations are expected to exceed 1.0 Gb/sec throughput based on clock rates from 250 MHz and higher. Applications will include embedded systems in the networking, multimedia, storage and signal-processing sectors. 

Q. Does this new family continue the memory-to-logic ratio established with the Virtex-E and EM families?
In today's high-bandwidth applications, system designers are in constant need of more memory for data buffering to maintain highest throughput in their system. Virtex-II family continues the memory-to-logic ratio established in the Virtex series with double the amount of the block RAM size and more distributed RAM resources for tomorrow's data intensive Internet applications. This unprecedented memory-to-logic ratio is unattainable by any programmable product available in the market today.

Q. Why does Xilinx find merit in this ratio?
The Virtex-II family is targeted for efficient sub-system integration, where overall system bandwidth is directly improved by providing additional buffering on-chip. For telecom, wireless, networking, mass storage, and high-end video and image processing applications, the additional memory is an important part of the high-bandwidth solution to achieve the maximum throughput in the system.

Q. Are other suppliers able to simply add more block memory to match this trend?
The Virtex-II family is engineered to meet the need for an abundance of block memories for sub-system function support in network switches, high-end video filtering, and mass storage applications. These applications require both density and performance in order to efficiently use the block memory for overall system performance increases. To date, no other FPGA architectures can provide the level of density nor performance and memory resource, and would have to go through a total redesign in order to achieve the optimal memory-to-logic ratio available with the Virtex-II family.

Q. How does Xilinx measure density?
Xilinx measures density in terms of system gates, using the same basic measurement established with the Virtex family. It is a combination of logic, memory, and custom circuit resources that would be utilized in a typical design. The system gate estimate is found in typical designs using a portion of the resources available on the device. This does not count a sum total of all the logic, memory, and custom circuit resources available on each device. Of course, each design uses a different amount of logic and memory, so the density measurement will vary. If a design uses only logic portion of the resources on the devices, the achieved density will be far less than if the design were to use both the logic and a good portion of the memory.