What is the Virtex-E family?   
The Virtex-E family is a family of enhanced, next-generation Xilinx FPGAs based on the industry-leading Virtex architecture. It provides enhanced performance and features while maintaining design and footprint compatibility with Virtex. A family of eleven separate devices, it is the industry’s first 0.18 µm 1.8V FPGA family, and the first to achieve a system-gate density of over 3 million gates. 

What applications require multiple 10 Gbit/sec performance mentioned in the press release?   
Next generation telecom systems based on OC-192 (SONET standard) as well as many proprietary backplane applications.   

What are the differences between the Virtex family and the Virtex-E family?  
The Virtex-E family is: 

• Built on baseline features and functionality of Virtex
• Based on the 0.18 µm, 6LM process vs. a 0.25 µm 5LM process for Virtex
• Over 3x density increase (from 1 million to 3.2 million system gates)
• 1.3x speed grade performance
• Over 1.5x number of user I/Os (from 512 to 804)
• Over 1.5x I/O performance (from 200 MHz to over 311 MHz)
• 6.5x the internal block memory (from 128 Kbits to 832 Kbits)
• 2x the number of DLLs (from 4DLLs to 8 DLLs)
• Available with more advanced fine pitch packaging (FG860, FG900, and FG1156) support bringing the max I/O count up to 804
• Support three differential I/O standards: LVDS, Bus LVDS, and LVPECL (from supporting 17 I/O standards to 20 I/O standards)
• Capable of delivering 622 Megabits per second (Mbps) differential I/O performance

Who are the decision-makers for designing in a Virtex-E device? Are these different people than other FPGA decision-makers?  
The Virtex-E family continues to redefine what is possible for an FPGA, just as Virtex series did a year ago at its introduction. Current FPGA designers will like the increased density, increased I/O and memory performance, as well as the enhanced system integration feature set of Virtex-E devices. In addition, Virtex family has the attention of the reluctant ASIC user who previously did not have the option to consider FPGAs due to its performance. With the significant improvements in both I/O and memory bandwidth performance and the flexibility of the Virtex-E solution, system architects can now consider Virtex-E family as a viable alternative to the ASIC while enjoying the time to market and flexibility advantages of FPGAs for all components in a system. 

What are some of the new markets and applications that Virtex-E family will enable for Xilinx?  
Virtex-E devices will find homes in the traditional strong markets for FPGAs: networking, telecommunication, high-end computing, industrial and wireless markets. These are key markets for Virtex-E devices since the time to market and flexibility advantages of FPGAs have always been valued. Within these strong markets, Virtex-E devices offer new high performance/bandwidth application possibilities for FPGAs based on its enhanced I/O and memory performance. The Virtex-E family is already being considered for applications that previously required ASICs. Some examples are SONET data stream processing for OC-3, OC-12, OC-48, and OC-192 standards, main processing engine for massively parallel compute network, variety of protocol controllers and switch matrix for next generation network equipment, and backplane controllers for ultra high speed board to board communication. 

Is Xilinx the only semiconductor supplier shipping the 0.18 µm process?  
Xilinx is the first programmable logic vendor to deliver devices employing the 0.18 µm process technology.   

Which features are unique to the Virtex-E devices?  
Building on the success of the Virtex system integration feature set, the Virtex-E devices offer significant enhancement in the system integration feature set. The enhancements include high performance memory hierarchy, multiple digital delay locked loops (DLL) and multi-standard I/O. Each feature by itself, is unique to the industry in the specific implementation. All these features are dramatic improvements that greatly enhance FPGA performance and system level integration. 

• Virtex devices are the first to provide high performance, working clock management circuitry with their DLL technology. With the Virtex-E devices, the DLLs are now capable of performance over 311 MHz. Other PLD vendors have introduced devices with phase locked loops (PLL) that have questionable success or have only worked at lower frequencies.
• Virtex-E devices are the first products to support direct interface to multiple differential signal standards including LVPECL, LVDS and Bus LVDS (BLVDS) via its SelectI/O+Ô technology. The Virtex-E device offers a hierarchy of differential solution, including up to 36 differential pairs for LVDS and LVPECL operating at 622 Mbps per pair, and up to 344 differential pairs capable of over 311 Mbps per pair (providing a total aggregate bandwidth of over 100 Gbits/sec with high noise immunity).
• Virtex-E devices are the first products to provide simultaneous support for four different voltage standards including 1.8, 2.5, 3.3, and 5.0 volts (with external resistor).
• The Virtex-E family is the first FPGA family to interface to high performance memories (like 266 MHz DDRä SRAM and 200 MHz ZBTâ SRAM)
• The Virtex-E FPGA family is the first to support multiple 10 Gbps ports in a single device

Is Virtex-E bitstream compatible with the Virtex device? 
No, a Virtex-E device is not bitstream compatible with a Virtex device.   

What is meant by design compatible with the Virtex device?  
All Virtex-E base elements are the same as those of the Virtex family. The Virtex-E family has more elements that are capable of higher performance. Any design in Virtex can be easily reused in Virtex-E devices with recompilation. 

Is there a price premium for Virtex-E over Virtex?  
Initially there will be a slight price premium over the Virtex family. However, price projections show the Virtex-E family at lower price per logic cell by mid 2000. Xilinx expects the Virtex-E family to be the main design vehicle of choice starting in 2000. 

What are the primary application areas for the DLL?  
Clock synchronization is critical in high performance applications. The Virtex-E digital delay locked loops (DLLs) provide a mechanism to remove all clock skew in a system as well as minimize clock to output delays. In ultra high performance applications, clock skew and clock to output delays can easily be more than 50 percent of the critical path. With Virtex-E DLLs these values can be reduced to nearly zero effectively doubling possible system frequency. Furthermore, the ability to generate a precise 50/50 duty cycle is especially essential for applications requiring high performance clocking scheme (e.g. Double Data RateÔ applications). 

What are the advantages of the DLL over the traditional PLL?  
Compared to a phase locked loop (PLL), a DLL has a number of advantages. The Virtex-E DLL is a complete digital implementation that simplifies the processing and the future scalability of the DLL. The Virtex-E DLL does not accumulate jitter because each clock edge in essence restarts the circuitry. Further, the Virtex-E DLL has been proven to operate at frequencies over 311 MHz while competing PLL solutions in programmable logic devices either had questionable success or are limited to frequencies below 100 MHz. Unlike the PLL solution, the Virtex-E DLL also does not require external inductors, capacitors, or separate ground and power plane when implemented in a system design. 

Why did Xilinx double the number of DLLs?  
For complete internal and external clock deskew, two DLLs are required. By doubling the number of DLLs (from four to eight), Virtex-E allows four system clocks to be managed by a single device.   

What is LVDS used for? LVPECL? Bus LVDS?  
LVPECL, BLVDS, and LVDS offer high noise immunity to data transfer. Backplane and data communication applications greatly benefit from this noise immunity. In addition, LVPECL is the standard for distributing clocks above 100 MHz and interfacing to high performance optical transceiver, networking and mixed-signal devices. 

Does the Virtex-E family support applications for reconfigurable computing? Is it partially reconfigurable?  
Virtex-E devices do support reconfigurable computing. Each device can be reconfigured to provide different functions at different times. A specific high-speed configuration port allows bitstreams to be downloaded into Virtex-E devices at a rate up to 400 Mbit/second, which allows even the largest device to be completely reconfigured in milliseconds. Virtex-E devices will also provide for partial reconfiguration, meaning a portion of the device can be changed while the rest of the device continues to operate.   

Do Virtex-E devices have the capability to support Internet Reconfigurable Logic (IRL)?  
The Virtex-E devices, with their capability of supporting partial reconfiguration, are used as the hardware vehicle for implementing Xilinx Online applications. 

Does the gate-counting method for Virtex-E differ from the method used to calculate the original Virtex series?  
The gate counting used on Virtex-E devices is consistent with the system gate counting used for the original Virtex devices. The basics of the system gate count equation are each logic cell used as logic provides 12 system gates; each logic cell used as distributed memory provides 64 system gates (16 bits x 4 gates/bit). Since larger devices typically require more memory the percentage of logic cells used as distributed memory ranges from 5—30 percent across the family. With Virtex devices additional capabilities add to the system gate count. Each DLL used provides 7000 system gates and each logic cell used as a programmable delay element provides 112 system gates. Finally, block memory adds to the gate capacity of Virtex device and each bit of block RAM memory provides four system gates. Up to 40 percent of block memory usage is factored into the system gate count.   

When will software support be available for the Virtex-E family?   
Virtex-E software support is available today. Xilinx and other EDA vendors, including Exemplar, Synopsys and Synplicity, offer technology in performance via VHDL and Verilog synthesis. The latest software releases, the version 2.1i of Xilinx Alliance Series and Foundation Series software, offer full support for the Virtex-E family. Timing driven compile time benchmarks have been set with these tools by offering typical rates of 400,000 gates/hour for timing driven place and route.   

What feature in Xilinx software version 2.1i can be used to support customers designing with the Virtex-E million+ gate devices?  
To coordinate multiple design modules in remote locations for million-plus gate density designs, Xilinx offers Internet Team Design (ITD) tools in its latest release of version 2.1i software. The ITD tool can be used to coordinate many design source files and expertly integrate design flows over the Internet to improve communication and reduce the design cycle.   

Are there any new cores available for Virtex-E FPGA?  
The CORE Generator 2.1i tools support the Virtex-E devices at silicon availability. Popular high bandwidth cores including the Real-PCI 64/66 solution and the 32/33 Xilinx LogiCORE PCI solution, support Virtex-E devices today. With the capabilities of the Virtex-E architecture coupled with Xilinx LogiCORE, AllianceCORE and XPERTs programs, many high bandwidth cores are in development. For up to date information on the latest cores, contact Xilinx IP Center. 

What has been the demand for the newer packages? CSP and the FG?   
While not eclipsing mainstream Xilinx BGA package offerings, demand for high-density packaging is growing at a faster rate. The combination of board efficiency with high reliability has increased Xilinx leadership in packaging technology.   

What are the available package and the other members of the family?  
The Virtex E family supports all the package technologies offered by the original Virtex series. In addition, Virtex-E family also offers three more advanced fine pitch packages (FG860, FG900, and FG1156), bringing the max I/O count to 804.