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Analyze
- The first step in the FPGA Express synthesis flow.
In this stage, the HDL code is checked for syntax errors.
Behavioral simulation
- Also known as functional simulation. This type of
simulation takes place during the pre-synthesis stage of HDL design.
The purpose of this simulation is to check that the HDL code
describes the desired design behavior.
Bottom-up design
- HDL methodology where already defined HDL blocks
are merged into one overall desired design behavior.
Carry-logic
- An architecture feature of the Xilinx XC4000 and
XC5200 families. Carry-logic was designed to speed-up and reduce
the area of counters, adders, incrementers, descrementers, comparators,
and subtractors. FPGA Express can synthesize carry-logic directly.
EDIF
- Electronic Design Interchange Format. An EDA industry
netlist format.
FROM:TO timespecs
- Timespec style used in M1 and XACT. This timespec
style allows point-to-point, group-to-group, one-to-many, and
many-to-one path types to be specified.
HDL
- Hardware Description Language. A language which
describes circuits in textual code. The two most widely accepted
HDL's are Verilog and VHDL.
IEEE(pronounced "I-triple-E")
- Institute of Electrical and Electronic Engineers
Implement
- The second step in the FPGA Express synthesis flow.
In this stage, the analyzed HDL is expanded into gates. This step is also refered to as elaboration.
LogiBLOX
- M1 tool used to generate blocks of RAM or ROM. These
blocks of RAM or ROM can be instantiated for use in FPGA Express.
MEMGEN
- XACT 5.2.x/6.0.x tool used to generate blocks of
RAM or ROM. These blocks of RAM or ROM can be instantiated for
use in FPGA Express.
Optimize
- The third step in the FPGA Express synthesis flow.
In this stage, the implemented design is re-synthesized with
constraints the user specifies. This is the final step before
writing out the XNF file from FPGA Express.
OVI
- Open Verilog International. A non-profit organization which
maintains the Verilog HDL standard.
Post-synthesis simulation
- This type of simulation is usually done after the
HDL code has been expanded into gates. Post-synthesis simulation
is similar to behavioral simulation since design behavior is being
checked. The difference is that in post-synthesis simulation
the synthesis tool's results are being checked. If post-synthesis
and behavioral simulation match, then the HDL synthesis tool has
interpreted the HDL code correctly.
Timespecs
- XACT and M1 commands, which can be specified in a
HDL flow or in an external file, which specify the timing requirements
of a design to the place and route software.
TIMING SIMULATION
- Also known as backannotated timing simulatioin.
This type of simulation takes place after the HDL design has been
synthesized and placed & routed. The purpose of this simulation
is check that the dynamic timing behavior of the HDL design in
the target technology.
Top-down design
- HDL methodology where overall design behavior is
defined first, and then HDL blocks.
Verilog
- An industry standard HDL(IEEE Std 1364) originally
developed by Cadence Design Systems, now maintained by OVI. Originally,
this HDL was designed as a simulation language. Design files
of the Verilog type are recognized by .v extension.
VHDL
- VHSIC Hardware Description Language. An industry
standard HDL(IEEE Std 1076.1). Originally, this HDL was designed
as a documentation language. Design files of the VHDL type are
recognized by the .vhd or .vhdl extension.
VHSIC
Very High Speed Integrated Circuit
VITAL
- VHDL Initiative Toward ASIC Libraries. A VHDL simulation
library standard(IEEE Std 1076.4) that defines standard constructs
for simulation modeling which can be used with any VITAL compliant
simulator.
XNF
- Xilinx Netlist Format
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