Boundary Scan/JTAG: Getting Started
 Overview
Boundary Scan in Xilinx Devices
Software Support
Boundary Scan Links
Boundary Scan Product Suppliers
 to view the  PDF files below.
Overview
Boundary Scan/JTAG, formally known as IEEE/ANSI standard 1149.1_1190 is a set of design rules, which when applied at the chip level help reduce the cost of designing and producing ICs. The standard came about as a result of the efforts of a Joint Test Action Group (JTAG) formed by several North American and European elctronics engineering companies. The JTAG proposed a basic test architecture to be incorporated at the IC level alongwith a set of basic instructions and protocols for manipulating the same.
The standard requires four (optionally 5) dedicated boundary scan pins, viz: Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK), Test Mode Select (TMS) and optional Test Reset (TRST - active low). These pins for the Test Access Port (TAP). The TCK, TMS and TRST pins must float high if left unconnected.
A sixteen state FSM called the TAP Controller is also required. The FSM is controlled by TCK and changes states as per TMS (and optionally, TRST). The TAP controller understands the basic Boundary Scan instructions and generates internal control signals used by the test circuitry.
A Boundary Scan Instruction Register and decode logic in addition to two mandatory Boundary Scan Data Registers, viz: the Bypass Register and the Boundary Register must be present on the IC. The Instruction Register is controlled by the TAP and can act as a serial shift register between TDI and TDO. It selects the appropriate Data Register to be used, as per the current instruction. The Instruction Register must be at least two bits wide.
Lastly, the standard states that the following three instructions, BYPASS, SAMPLE/PRELOAD and EXTEST must be supported. The BYPASS instruction puts the one-bit Bypass Register between TDI and TDO. A bit pattern of all 1's in the Instruction Register must translate to the BYPASS instruction. The SAMPLE/PRELOAD instruction connects the boundary register between the TDI and TDO pins without disconnecting the system logic from the IC's pins. The EXTEST instruction connects the Boundary Register between the TDI and TDO pins, but disconnects the system logic from the IC's pins. A bit pattern of all 0's must translate to EXTEST.
Texas Instruments provides a Boundary Scan educational tool called the Scan Educator on their web site. It is a DOS based shareware program. Click here to download the Scan Educator software from the Texas Instrument website
The standard also mandates a description syntax for the IEEE 1149.1 IC's and is known as the Boundary Scan Description Language (BSDL). It is a subset of VHDL. For more description on the BSDL format, read Texas Instrument's BSDL page. Hewlett-Packard provides a BSDL/IEEE 1149.1 Verification Servicewhere a BSDL file can be tested for conformance with the standard. Xilinx provides BSDL files for its devices on the FTP site. Other vendors such as Intel and Motorola provide BSDL files for their devices on their respective Web Sites.
Boundary Scan in Xilinx Devices
Xilinx offers Boundary Scan/JTAG support in its XC4000, XC5200, Spartan and XC9500 family devices. For more details please refer to  Boundary Scan in XC4000 and XC5200 devices and Using XC9500 Boundary Scan Interface and Using ISP in Boundary Scan systems.
Software Support
Xilinx offers software access to the Boundary Scan interface of the XC9500 devices through the M1.x JTAG Programmer software or the XACT 6.x EZTAG software. You can download EZTAG software from the Xilinx FTP site.
Boundary Scan Links
Boundary Scan Product Suppliers
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