Synopsys FPGA/Design Compiler Interface - Tips and Techniques

	Solution 7418 - A2.1i: Virtex-E synthesis libraries for 1999.05
	Solution 6654 - NGDBUILD ERROR:basnu:93 -logical block "<blockname>" of type "f402" is unexpanded
	Solution 4686 - How to use the VHDL ROC (Reset On Configuration) Component
	Solution 4595 - Synopsys Design Compiler - How to specify the INIT attribute on instantiated ROM/RAM primitives
	Solution 2865 - FPGA/Design Compiler - How to instantiate LogiBLOX in the Synopsys VHDL or Verilog Flow
	Solution 4345 - FPGA Compiler, Verilog - Example of how to infer "set" flip-flop when GSR is asserted
	Solution 2500 - SYNOPSYS FPGA/Design Compiler - How to constrain I/O pins in Synopsys designs (I/O pin locking)


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