Synplicity Interface - Documentation

to view the PDF files below.

Design Flow

• Synplify User Manual
  The complete details on the usage and options of Synplify 5.3.x
• Synplify/Modelsim Tutorial Guide for Alliance 2.1i, 7/99 (197 KB)
  The Watch Design Synplicity Tutorial is a flow based tutorial taking the Verilog/VHDL Design files through Synplicity Synplify 5.1.x for synthesis. The tutorial includes pre-synthesis Functional Simulation, and a post place and route (PAR) Timing Simulation, both using the Model Technology ModelSim 5.2x simulator.

  Design files

  • Synplify/Modelsim Design Files, tar.Z format, 07/99 (186 KB)
  • Synplify/Modelsim Design Files, ZIP format, 07/99 (103 KB)
• ModelSim and Synplicity Synthesis
  A general overview of using a post-synthesis/pre-Alliance simulation netlist with ModelSim

• Synthesis and Simulation Design Guide, 4/98 (1.3 MB)
  Manual providing a general overview for designing into FPGAs using VHDL and Verilog including Verilog simulation techniques.

Design Techniques

• Synplicity-Xilinx High Density Methodology
  An app noted intended to assist designers who are using Synplify and Xilinx to design high density FPGAs (500K -1 million system gates).
• Using Xilinx and Synplify for Incremental Designing (ECO)
  Guided place and route (PAR) can help you reduce runtimes when incremental changes are made to a design, such as for an Engineering Change Order (ECO). By making only small changes to a design along with optimizing only the changed block(s), you allow guided PAR to perform at its best, preserving timing and reducing PAR runtimes. To localize the design changes without affecting the remainder of your design, either a top-down preserving hierarchy or a bottom-up methodology must be used.
  • TCL scripts, tar.Z format, 08/99 (69 KB)
  • TCL scripts, ZIP format, 08/99 (46 KB)
• Hierarchy Management in Synplify
• Inferring RAM in Synplify
• Synplify Extends Timing Constraint Control for Mixed Entry
• Synplify - Achieving Optimal Results
• Alternatives to VHDL Configurations in Synplify
• Designing Safe Verilog State Machines with Synplify
• Designing Safe VHDL State Machines with Synplify
• Tips For Achieving Best Results With Synplify
• Synplicity Support for Xilinx Virtex Series  

PCI

• Design Flow & M1 Implementation for LogiCORE PCI32
  An overview for LogiCORE PCI32 Interface through Synplify and Xilinx M1.5.
• Synplify Flow for Xilinx Virtex Real PCI 64/66 Core

Tools

• HDL Analyst - A Unique Tool for Visualizing Synthesis Results
• Certify: RTL Multichip Partitioning and Synthesis for ASIC Prototype Using FPGAs
• Amplify with Xilinx Datasheet