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3.1i Constraints

5/30/00


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Table of Contents

3.1i Constraints

M1 Design Flow

What Needs Constraining?

Types of constraints supported

Where do Constraints go?

Brief Review of Constraint Flow

Timing Constraints (I)

Period Constraints

The Period Constraint

Period Path Tracing

Period and Two-Phase Clocks

Period and RAM

Period Examples

I/O Timing: Offset

PPT Slide

The OFFSET IN - ‘BEFORE’ constraint

The OFFSET IN - ‘AFTER’ constraint

The OFFSET OUT - ‘AFTER’ constraint

The OFFSET OUT - ‘BEFORE’ constraint

OFFSET Constraints in 3.1i

Clock Register Groups in OFFSET

Data Path Groups in OFFSET

OFFSET Examples (1)

OFFSET Examples (2)

Synopsys Support for PERIOD and OFFSET

Timing Constraints (II)

Timing Path Keywords

Basic Global Timing Constraints ( using the FROM-TO Syntax)

Basic Global Timing Constraints ( using the FROM-TO Syntax)

Using TNM to create Groups

Using TNM to create Groups.

Using TNM_NET to create Groups

Grouping of Block RAM Ports

Multi-Cycle Delays Grouping by net name

Multi-Cycle Delays Grouping by instance name

Slow Exceptions

Slow Exceptions: Multi-Cycle Delays with Clock Enables

Specific Delays from one group to another

Specific Delays going through specific logic (TPTHRU)

Specific Delays Excluding Logic

Constraining Between Rising & Falling Clock Edges

Constraining Between Multiple Clock Domains

Creating new synchronous points (TPSYNC)

Ignoring Paths (TIG)

Controlling False Paths (TPTHRU)

Timing Constraint Priority (1)

Timing Constraint Priority (2)

Timing Constraint Priority (3)

SKEW

SKEW (II)

MAXSKEW: Limiting SKEW

USELOWSKEWLINES

Reporting SKEW in TRACE

Prorating Constraints

Placement & Other Constraints

Pin Location Constraints

Other Location Constraints

AREA_GROUP Constraint

Range and Compression

AREA_GROUP Example

Prohibit Location Constraints

Mapping Constraints

Implementation Constraints

Conclusion

Basic constraints file

More specific constraints file

More specific constraints file (cont.)

ISSUES to be aware of

ISSUES to be aware of (II)

ISSUES to be aware of (III)

Summary

Documentation

Email: chris.zeh@xilinx.com

Home Page: http://support.xilinx.com/support/techsup/journals/timing/index.htm

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