CompGE Summary: The CompGE function performs a numerical comparison of two inputs, X and Y, to form the 2-bit output, Z. If Z[0] is set, the two inputs are equal. If Z[1] is set, X is greater than Y. Note: It is possible for two signals to have the same bit pattern but not be equal. For example, wire signed [7:0] X = -1; wire [7:0] Y = 255; These two inputs have the same bit pattern, but they are not equal. The Equal bit of the output, Z[0], is 0. The width of the X input signals is controlled by Xwidth. The width of the Y input signals is controlled by Ywidth. When Xsigned is set, X input is a two's complement number. When Ysigned is set, Y input is a two's complement number. The CompGE is always optimized for minimum possible delay. Function: Z[1]=(X>Y) Z[0]=(X==Y) Signals: X: Xwidth wide input (signed if Xsigned is selected) Y: Ywidth wide input (signed if Ysigned is selected) Z: 2-bit output (Z[1] is true if X>Y, Z[0] is true if X==Y) Parameters: Name: actual module name Xwidth: width of the X signal (1-256) Ywidth: width of the Y signal (1-256) Xsigned: format of X (signed when selected, unsigned otherwise) Ysigned: format of Y (signed when selected, unsigned otherwise) Verilog Usage: Name(X,Y,Z); Version: $Id: CompGE.help,v 1.1 1996/11/15 01:56:47 aaron Exp $