Counter, CountUpDown Summary: These functions are synchronous up and up/down counters, respectively. Both are positive edge triggered. The width of the counter is controlled by Width. The type of the adder used in the incrementor is controlled by AdderType. The adder is always optimized for minimum possible delay. Counter is an up-only counter, with a 1-bit X input (count up 0 or 1). CountUpDown has a two-bit signed X input to allow counting by -2, -1, 0, 1 Both counters can be held by setting the X input to zero and can be loaded to the value on the START bus by holding RESET LOW while CLK goes HIGH. Function: Z(n)= RESET(n-1) ? Z(n-1)+X(n-1) : START(n-1) Signals: Z: Width wide output X: 1-bit unsigned input (Counter), 2-bit signed input (CountUpDown) RESET: 1-bit synchronous reset input, active LOW START: Width wide input, initial counter value CLK: positive edge triggered clock Parameters: Name: actual module name Width: width of the START and Z signals AdderType: type of the adder to build Verilog Usage: Name (RESET,START,X,Z,CLK); Version: $Id: CountUpDown.help,v 1.1 1997/06/26 20:16:34 peterr Exp $