FPF2I, FPI2F Summary: These functions convert between signed integer formats and floating point formats. IEEE standard floating point is implemented. However, you have the option to create new floating point formats and to select rounding and status options that go beyond the standard. Certain IEEE specified exceptions are not handled in hardware and are left to software exception handlers. The particular floating point format of all three signals is programmable via MantWidth and ExpWidth. MantWidth sets the width of the mantissa or fractional part of the floating point value. ExpWidth sets the width of the exponent part of the value. The floating point value has a total width of ExpWidth+MantWidth+1 bits because there is also a sign bit. The width of integer values is controlled via IntWidth. Integers are always signed. Rounding options may be set dynamically by selecting DynamicRounding. Otherwise a fixed rounding scheme is used. If OutputStatus is selected, then status flags are available to indicate special conditions which occured in the computations. If DynamicRounding and OutputStatus are not selected, will result in some area and delay savings. Some implementation architecture variations can be controlled via the Arch parameter. See the Floating Point Library User Guide for more details on floating point representation, rounding options, status bits and architecture options. Function: Z=int(A) (FPI2F) Z=float(A) (FPF2I) Signals: Z: MantWidth+ExpWidth+1 bit wide floating point output (FPI2F) IntWidth bit wide integer output (FPF2I) A: MantWidth+ExpWidth+1 bit wide floating point input (FPF2I) IntWidth bit wide integer input (FPI2F) RND: 3-bit wide rounding control input (DynmaicRounding selected) STATUS: 8-bit status output (OutputStatus selected) Parameters: Name: actual module name MantWidth: matissa (fraction) width of floating point signals. Range: 2 to 256 ExpWidth: exponent width of floating point signals. Range: 3 to 31 IntWidth: integer width. Range: 3 to 512 DynamicRounding: Flag to control rounding options. Select to control at run-time. OutputStatus: Flag to control the output of status bits. Select to output. Arch: Architecture control. Verilog Usage: Name(Z,A); (DynmaicRounding=0, OutputStatus=0) Name(Z,A,RND); (DynmaicRounding=1, OutputStatus=0) Name(Z,A,STATUS); (DynmaicRounding=0, OutputStatus=1) Name(Z,A,RND,STATUS); (DynmaicRounding=1, OutputStatus=1) Version: $Id: FPI2F.help,v 1.1 1998/10/02 22:53:43 mcsrc Exp $