Divide

Summary:
The Divide function divides dividend X by divisor Y, to get quotient Q and 
remainder R.  All of X, Y, Q, and R are unsigned inputs/outputs.  The width 
of the X and Y inputs can be controlled independently with the Xwidth and 
Ywidth parameters, respectively.  Consequently, the width of Q and R are 
Xwidth and Ywidth, respectively.

Note that Q and R are not defined when divisor, Y, is 0.  The equation, 
X = Q*Y+R, is true only when Arch=1, Round not selected, and Y != 0.
There are two architectures in Divide function, controlled by "Arch".

If Arch=1, a shift-subtract divider is produced, which is generally smaller
than Arch=2.  The remainder (R=X%Y) is only meaningful at Arch=1 and Round 
not selected.

If Arch=2, X is multipled by 1/Y. A ROM generates 1/Y; therefore, this 
architecture is good for small Ywidth and is generally faster than Arch=1.  
The type of the multiplier (Booth or non-Booth) is controlled by "Booth".
There is no remainder, R, for both rounding modes in this architecture.

For both architectures, there are two rounding modes for the quotient Q, 
controlled by "Round".  When Round is selected, Q is the nearest integer 
of quotient X/Y.  When Round is not selected, the quotient, X/Y, is truncated 
to form Q.

The Divide desired delay is controlled via the Delay parameter. When Delay is 
greater than zero, a pipelined Divider is constructed, else an unpipelined 
Divider is constructed.


Function: 
    Q = nint(X/Y)  (if Round is selected)
      : nint(x) which converts a float x into the nearest integer. The halfway 
        cases are rounded up.

    Q = floor(X/Y) (if Round  is not selected)
      : floor(x) returns the greatest integral value less than or equal to x.  
        This corresponds to IEEE rounding toward negative infinity.

    R = X%Y        (Exist only at Arch=1 and Round not selected)

Signals:
    X: Xwidth wide input  (unsigned only)
    Y: Ywidth wide input  (unsigned only)
    Q: Xwidth wide output (unsigned only)
    R: Ywidth wide output (unsigned only)
    CLK: positive edge triggered clock (if pipelined)

Parameters:
    Name: actual module name
    Xwidth: width of input X
    Ywidth: width of input Y
    Delay: select the cycle time in ps (pipelined), or 0 for the fastest 
           unpipelined design.
    Arch:  1 for architecture with smaller size, 2 for faster speed
    Round: select for biased rounding, no rounding otherwise
    Booth: select for a Booth multiplier, non-Booth otherwise (only for Arch=2)
    AdderType: specify adder type (ripple, csa, fastcla, cla, clsa)

Verilog Usage:
  Arch=1 and Round not selected:  
    Name(X,Y,Q,R); (not pipelined)
    Name(X,Y,Q,R,CLK); (pipelined)
  Otherwise:
    Name(X,Y,Q); (not pipelined)
    Name(X,Y,Q,CLK); (pipelined)

Version: $Id: Divide.help,v 1.3 1996/11/21 23:05:46 aaron Exp $