Inner

Summary:
The Inner function computes the inner product of the two input vectors, X and Y. The 
dimension of vectors (and the number of multipliers) is specified with the Taps parameter.
The inner product result is provided at Z.  The width of the X and Y inp
uts can be controlled independently with the Xwidth and Ywidth parameters, respectively.
The formats (signed or unsigned) of X and Y are also controlled independently with 
Xsigned and Ysigned, respectively.  The inner product desired delay is controlled 
via the Delay parameter.  When Delay is greater than zero, a pipelined inner
product is constructed, else an unpipelined inner product is constructed.

The output, Z, is always a full precision value, with width equal to Zwidth.  When
rounding is selected (Round>0), only the bits of Z with indices from Round to Zwidth-1 
are valid.

The type of the  multipliers used (Booth or non-Booth) is controlled by Booth.  Booth 
multipliers are most efficient when X and Y are large (greater than 8 bits) and
when X and Y have an even number of bits and are signed. Non-Booth multipliers are
most efficient when X and Y are unsigned and/or the widths are small.

The type of the final adder type is controlled by "AdderType".

Function: 
    Z(n)=Y0*X0+Y1*X1+ ... YTaps-1*XTaps-1 + 1<<(Round-1)

Signals:
    Xi: Xwidth wide inputs (Xsigned sets format, 0<=i<Taps)
    Yi: Ywidth wide inputs (Ysigned sets format, 0<=i<Taps)
    Z: Zwidth wide output
    CLK: positive edge triggered clock (if pipelined)

Parameters:
    Name: actual module name
    Taps: number of taps
    XWidth: width of input X
    Xwidth: width of input Y
    Width: width of the output
    Xsigned: format of all Xi inputs (signed when selected, unsigned otherwise)
    Ysigned: format of all Yi inputs (signed when selected, unsigned otherwise)
    Delay: select the pipelined cycle time in ps, or 0 for unpipelined
    Round: select the rounding position (0 for no rounding)
    Booth: select for Booth multipliers, non-Booth otherwise
    AdderType: type of the adder to build (cla, fastcla, clsa, csa, ripple)

Verilog Usage: 
    Name(X0, ... XTaps-1,Y0, ... YTaps-1,Z,CLK); (if pipelined)
    Name(X0, ... XTaps-1,Y0, ... YTaps-1,Z); (not pipelined)


Version: $Id: Inner.help,v 1.5 1998/08/22 00:28:42 peter Exp $