Square Summary: The Square function squares the input, X, to form the product Z. The width of the X input can be controlled with the Xwidth parameter. The format (signed or unsigned) of X is controlled with Xsigned. The desired delay is controlled via the Delay parameter. When Delay is greater than zero, a pipelined squaring circuit is constructed, else it is unpipelined. The output, Z, is always a full precision value, with width equal to 2*Xwidth. When rounding is selected (Round>0), only the bits of Z with indices from Round to 2*Xwidth-1 are valid. The type of the final adder is controlled by "AdderType". Function: Z=X*X Signals: X: Xwidth wide input (Xsigned sets format) Z: 2*Xwidth wide output CLK: positive edge triggered clock (if pipelined) Parameters: Name: actual module name Xwidth: width of input X Xsigned: format of X (signed when selected, unsigned otherwise) Delay: select the cycle time in ps (pipelined), or 0 for unpipelined Round: select the rounding position (0 for no rounding) AdderType: type of the adder to build (cla, fastcla, clsa, csa, ripple) Verilog Usage: Name(X,Z); (not pipelined) Name(X,Z,CLK); (pipelined) Version: $Id: Square.help,v 1.4 1997/06/26 20:16:34 peterr Exp $