nR1W_Latch Summary: These functions provide netlist based low-power asynchronous memories (RAMs) with 2 to 8 ports. All RAMs have only one write port and have a behavior very similar to the nR1W_RAM functions (the exception being that CSN does not directly affect the output). The write port is always controlled by the highest numbered address (or A for 1-port). The nR1W_Latch function should be used to construct RAMs with a large number of words and bits. Note: the delay reported by DPA will be the longest path through the register file. In general, this is a write through delay. For more meaningful delay information, see the estimated timing parameters in in the "User Critical Path" section of the Report file. Function: Low Power Asynchronous RAM (see Memory Architect User Manual for details) Signals: DOi: Bits wide data outputs for port i DIi: Bits wide data input for port i Ai: Address input for port i WEN: 1-bit Write Enable (LOW to write) CSN: 1-bit Chip Select (LOW to enable, HIGH to disable) Parameters: Name: actual module name Ports: the number of total ports (2-8) Words: the number of words (2-128) Bits: the number of bits (1-128) Verilog Usage: Name(DIn,A1,..,An,WEN,CSN,DO1,..,DOn-1); Version: $Id: nR1W_Latch.help,v 1.1 1995/06/13 00:37:44 peter Exp $