Aaяр0P pА0Pр0Р@ °`ђ`°0 PP@Ђ` Ђ@ Ѓ@РђЂЂЂ‰Ђ·ГВddКшКшКшяЂяяяЂяяяЂяяБђяяц КшяяяяяяяяЂ™ snpsBook]6\э]]]] ]]]]]]]]]] ]$ ]% ]) ]* ].]2]3]4]5FBABHGECI: Section: FPGA Compiler II Altera Edition Express Online Help†ЯFPGA Express Online HelpCHDEJAIG: Section: Audience†ЯAudience'i100000: Section: Launching the Program†Яpage 22'BABGGCIG: Section: Related Publications†ЯRelated PublicationsCi100000: Section: Launching FPGA Compiler II Altera Edition Express†ЯLaunching the Program1BGBGHGBH: Title(ChapterTitle): 2 Basic Operations†Я2, ТBasic Operations'BABBCACD: Section: SOLV-IT! Online Help†ЯSOLV-IT! Online Help#BABCBHAB: Section: Customer Support†ЯCustomer Support 7BABCDBAI: Section: Analyzing and Debugging Source Files†Я(ТDebugging the Source FilesУ on page 37BABGFIGA: Section: Conventions†ЯConventionsBGBHDHBE: Section: Features†Я!Features QBABCHIFD: Figure: Figure 34 The Project Window After Adding Design Source Files†Я Figure 31 /BABIDCEJ: Figure: Figure 35 HDL Editor Window†Я Figure 32 >BABFCACJ: Figure: Figure 36 Identifying the Top-Level Design†Я Figure 33 >BABGFDIA: Figure: Figure 37 Create Implementation Dialog Box†Я Figure 34 @BABHIBHB: Figure: Figure 38 Creating the Design Implementation†Я Figure 35 IBABICCFF: Figure: Figure 39 Ports Constraint Table and Other Table Tabs†Я Figure 36 RBABJFHID: Figure: Figure 310 Optimization Results in the Clocks Constraint Table†Я Figure 37 QBABFCCID: Figure: Figure 311 Optimization Results in the Paths Constraint Table†Я Figure 38 QBABGCBEJ: Figure: Figure 312 Optimization Results in the Ports Constraint Table†Я Figure 39 [BABCBABA: Figure: Figure 313 Viewing Optimization Results in the Modules Constraint Table†ЯFigure 310 8BABEDBHI: Figure: Figure 314 Schematic ViewerСRTL View†ЯFigure 311 ?BABBBHFE: Figure: Figure 315 Schematic ViewerСGate-Level View†ЯFigure 312 0BABEABIB: Figure: Figure 316 Export Dialog Box†ЯFigure 313?BGBGHHEI: Figure: Figure 13 FPGA Express Design Flow Overview†Я Figure 11 ABABEJJCA: Figure: Figure 319 Generate Project Report Dialog Box†ЯFigure 3149CHDJEIFB: Section: Using FPGA Express in Your Design Flow†Я4ТUsing FPGA Express in Your Design FlowУ on page 17,BGBEGAFB: Section: Vendor-Provided Documents†Я$Altera-Provided DocumentsBGBFDHDE: Section: Benefits†ЯBenefits'i100000: Section: What Is FPGA Express?†ЯWhat Is FPGA Express?9CHDJEIFB: Section: Using FPGA Express in Your Design Flow†Я&Using FPGA Express in Your Design Flow 8CJADCACH: Figure: Figure 315 Export Netlist Dialog Box†Я Figure 01>BGBGHGFC: Section: Using the Quick Tour Video and the Tutorial†Я+Using the Quick Tour Video and the Tutorial CIHIAHBB: Section: Learning More†Я Learning More#CIHGCGHF: Section: Using the Toobar†ЯUsing the Tool Bar"CIHDHEHC: Section: Additional Tips†ЯAdditional Tips /CIHBHCED: Section: Creating Design Source Files†ЯCreating Design Source Files )CIHGAGIG: Section: Setting Up the Project†ЯSetting Up the Project )CIHGJCBF: Section: Elaborating the Design†ЯElaborating the Design ;CIHIAHDB: Section: Entering Design Constraints and Controls†Я(Entering Design Constraints and Controls 7CIHFHEEJ: Section: Optimizing the Design Implementation†Я$Optimizing the Design Implementation #CIHBFEBJ: Section: Analyzing Timing†ЯAnalyzing Timing %CIHGHHFG: Section: Viewing Schematics†ЯViewing SchematicsBGBJDJHI: Section: Tip Bar†Я$Tip Bar 2CIHHBEIH: Section: Running the FPGA Scripting Tool†ЯRunning the FPGA Scripting ToolDBABHCGFH: Section: FPGA Compiler II Altera Edition Express Man Pages†ЯFPGA Express Man Pages $CIHHJHIC: Section: Launching Quartus†ЯLaunching Quartus 9CJAJGABI: Figure: Figure 316 Place and Route Dialog Box†ЯFigure 315 BGBGFEFG: Section: Output Window†Я$ Output Window UCIHJCJHE: Section: Generating Netlists and Reports, Reports, and the Project Database†ЯGenerating Netlists and Reports*BGBCDIAE: Section: Topic-Based Help System†Я$Topic-Based Help System0BGBJDBHH: Section: Context-Sensitive Help System†Я$Context-Sensitive Help System.BGBFGFDF: Section: FPGA Express FPGA Man Pages†Я$FPGA Express Man Pages-BGBJCDEJ: Section: Compiler Reference Manuals†Я$Compiler Reference ManualsEBGEIDHFJ: Figure: Figure 18 FPGA Express in Your Design Environment†Я Figure 12Figure <$elemparanumonly>Figure <$elemparanumonly>?Т<$elemtext>У on page <$elemparanumonly[Number]><$elempagenum>?Т<$elemtext>У on page <$elemparanumonly[Number]><$elempagenum><$elemtext><$elemtext>.page <$elemparanumonly[Number]><$elempagenum>.page <$elemparanumonly[Number]><$elempagenum> <$elemparanumonly>, Т<$elemtext> <$elemparanumonly>, Т<$elemtext><$elemtextonly><$elemtextonly> cover.fm toc.fm lof.fm lot.fmabout.fm fpxgs_1.fm fpxgs_2.fmgetstart_intro.fm fpxgs_3.fmindex.fm\ъВdГ\ш\щc+ЂDPPcover.fmPPPtoc.fm+PPlof.fm+PP lot.fm+P PPabout.fmP Pfpxgs_1.fmPPfpxgs_2.fmPPfpxgs_3.fmPPPindex.fm+PPPCВdГ\ыВdГlВdГlЂАЃ@Ђ@ЂЂЂ™ AboutTitle. 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