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Y39368: FigureTitle: Figure 12 Using FPGA Express / FPGA Compiler II in Different DesignO'adesign flow:HDL-based;design methodology( (see design flow)<$nopage>`/ simulationa0 simulationD simulation -945266Nplace and route#Sback-annotation8 +7119679 -711967: =711967; +398306< -398306= =398306> +917503? -917503@ =917503A +348884B -348884C =348884D +879938 -879938H =879938I +363249. -363249K =363249L +756347M -756347N =756347O +396596P+FPGA Compiler II Altera Edition, definitionQ =396596R +632679S -632679T =632679U +843824m [37208: FigureTitle: Figure 11 How FPGA Compiler II / FPGA Express Fits In The Design FlowW =843824X +944778Y -944778Z =944778[ +905351\ -905351] =905351^ +284131_ -284131` =284131a +214597b -214597c =214597d +247518e -247518f =247518g +774955h -774955i =774955j +796355km FPGA vendorsl =796355m +662149n -662149o =662149p +267170q -267170r =267170s +933702t -933702u =933702v +178478w -178478x =178478y +882108z -882108{ =882108| +894803} -894803~ =894803 +455658 -455658 =455658 +148923=#dc_shell scripting;scripts:dc_shell =148923 +756796 -756796 =756796 +895166f -895166 =895166 +526913 -526913 =526913 +136423 -136423 =136423 +696303 -696303 =696303 +190675 -190675 =190675 +342848 -342848 =342848 +791124 -791124 =791124 +477615 -477615 =477615 +608392! -608392" =608392# +658793$ -658793% =658793& +468961' -468961( =468961) +939173* -939173+ =939173, +710316- -710316. =710316/ +2157090 -2157091 =2157092 +8554763 -8554764 =8554765 +3860266 -3860267 =3860268 +1638929 -163892: =163892; +837924< -837924= =837924> +945600? -945600@ =945600A +960660B -960660C =960660D +283766E -283766F =283766G +847686H -847686I =847686J +860758K -860758L =860758M +278082N -278082O =278082P +175144 8ASIC-compatible design flow; design flow:ASIC-compatibleR =175144S +848689 K54314: FigureTitle: Figure 14 FPGA Compiler II in Your Design EnvironmentU =848689V +176294W -176294X =176294Y +366969Z -366969[ =366969\ +182326] -182326^ =182326_ +194619` -194619a =194619b +386925c -386925d =386925e +301145f -301145g =301145h +713724i -713724j =713724k +945266Jplace and routem =945266n +907965o -907965p =907965q +433735r -433735s =433735t +211530u -211530v =211530   : ;<87 'i100000: Section: What Is FPGA Express?BGBCEGIH: Section: FeaturesBGBJAFEE: Section: Features87* "BGBHDHBE: Section: Features871#%BGBFDHDE: Section: Benefits87:&(9CHDJEIFB: Section: Using FPGA Express in Your Design Flow-CBGBIDJJG: Figure: Figure 11 FPGA Compiler II Design Flow Overview11RBGBGADCI: Figure: Figure 12 FPGA Compiler II Altera Edition Design Flow Overview56?BGBGHHEI: Figure: Figure 13 FPGA Express Design Flow Overview87CE9;?BGBGHHEI: Figure: Figure 13 FPGA Express Design Flow OverviewwIBGBEHHCI: Figure: Figure 14 FPGA Compiler II in Your Design Environment{cBGBBADJC: Title(): Figure 15 FPGA Compiler II Altera Edition in Your Design EnvironmentEBGEFDDHB: Figure: Figure 17 FPGA Express in Your Design Environment87LEBGEIDHFJ: Figure: Figure 18 FPGA Express in Your Design Environment* <$curpagenum> <$filename>"<$tblsheetnum> of <$tblsheetcount><$lastpagenum> (continued) 0<$paratext[ChapTitle,AppTitle,Title,AboutTitle]> <$paratext[Heading]> <$marker2> 5<$paranumonly[ChapNumber,AppLetter,Title,AboutTitle]> PRODUCT NAME FPGA Compiler II Number & Text <$elemparanumonly>, <$elemtext>Section <$elemtext>NumOnly<$paranumonly>Heading & Page?<$elemtext> on page <$elemparanumonly[Number]><$elempagenum>Page.page <$elemparanumonly[Number]><$elempagenum>See Heading & PageDSee <$elemtext> on page <$elemparanumonly[Number]><$elempagenum>. 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Hcn=J=J  GG  hMpNpOpPWhat Is FPGArC pQEExpresspR?pS  UT(tpTFPGArpW: ExprespXs pY is a complete< PLD r logic-synthesis, optimization, and 0G8iQanalysis tool< specifically for Altera devices . With it, you can create Coptimized netlists from VHDL code, Verilog HDL code, and existing, H%unoptimized EDIF netlists.pZp[  (rrJpypzFigure 11p{ summarizes the way that FPGA p|KExpressJp} fits in your design JwH flow.p~ !Lt h@pppFPGA Express Design Flow Overviewppp " dchpppIn this pflow, you use FPGAr;  p:Express p to perform the following steps:pp #(Gs(LppUse your favorite text editor to enter VHDL or Verilog HDL source P9DHcode for your design. p HcnH;" HcnH ld;` Hcn%P&! Hcn%P&%P&$ UTUT)YpFPGArp: Express p accepts any combination of VHDL, Verilog HDL, 0RAand EDIF netlist files as sources for a design. For example, you :can use functions or subdesigns created through schematic I>capture and Verilog within a VHDL top-level design.pp %[n)NppCreate your project folder, add the source files to it, and analyze 0l?the HDL (VHDL and Verilog HDL) design source files for correct Isyntax. p &t)^pBegin by creating an FPGArp: Express p project a working directory qI!folder to hold your files. p 'Ձ)NpWhen you add the design source files to the project, FPGArp: :Ү BExpress p automatically analyzes them, using the Synopsys "  Aindustry-standard HDL language supportr. If the source files =contain errors, the Output window helps you find and correct ?problems. You can use the integrated text editor on the design I5source files to facilitate easy debugging.pp (>*)NpppElaborate logic from VHDL, Verilog HDL,and EDIF netlist source O("ILfiles, targeting a specific< Altera  architecture and device. p )j)VpFPGArp: Express p elaborates the logic of your design, using 0{H Rarchitecture-specific algorithms to targetr< Altera devices . In this ?part of the design flow, the program elaborates each subdesign contain performance requirements and optimization options for I2architecture-specific optimization engines. p -[n)]pAfter optimization, FPGArp: Express p generates a netlist ready for l Hplace and route byr< MAX+plus II and Quartus. Note that Quartus < Lcan be launched from within the GUI of FPGA rJ Express. The " =program can also generate reports and an optimized schematic Iof your design. pp .)VppAnalyze ptiming. Extract and display accurate post-synthesis pdelay I5information for timing analysis and debugging. p /)ZpFPGArp: Express p displays timing information beside your design 0Bconstraints and highlights timing violations. This information is IIlinked directly to the schematic for easy debugging.pppp O H>i'sCqSqTqUFeaturesqV P;UTg)cqWqXqYThe FPGA qZ:Express;q[ core technology was developed specifically for 0ywCqbqcIndustry-leading quality of results (QOR)qdqe T iUs;qjqkEasy-to-use design flows and graphical user interfacesqlqm CU;iGqnqoIntegrated static timing analysis with TimeTrackerqpqq HcnH;˕"HcnH ld;˻ Hcn!HcnV;UTUT)RqrqsVista (visual tools for analysis) including qtschematic viewing with RI%tight links to TimeTrackerquqv WziDqwqxTcl-based language for qyscriptingqzq{q|q} X p$iq~qqBenefitsq Y UTL)\qFPGAs q: Express q adds control to the design process and helps you 0ɈBmigrate to an HDL design methodology while using common, familiar Isystems.q Zi4qqAdding Control to the Design Processq [ UT)_qUsing FPGAsq: Express q, you can produce the results you want without 0 VImultiple design iterations. You eliminate most or all iterations because Ayou enter the target performance and select speed or area as the Eprimary design goal before you synthesize. Other constraints you can Bspecify include system clock speed, path delays, port delays, and Chierarchical requirements. These additional constraints are passed I(to the place-and-route tool. qq \Fi8qqqMigrating to HDL Design Methodologyq ] UT")HqIf you are migrating from a schematic-based to an HDL-based design 0A Pmethodology, FPGAsq: Express q adds HDL logic synthesis and Loptimization to your current< PLD s design environment. You can Bcompletely define a design with HDL source code, or use a mixture Mof schematics and HDL source code to enter a design into FPGAsq: B:IExpress q.q HcnH;˾"HcnH  ld; Hcnʤ!Hcnʤʤ^ UTUT)BqUsing an HDL-based design methodology increases productivity 0 Pbecause HDL source code is s<device- independent, retargetable, and Greusable. The built-in optimization algorithms, which are specifically Vtuned fors< Altera devices , provide the smallest, fastest designs in the Ishortest time. qq _i.qqUsing Common, Familiar Systemsq ` UTv)SqThe FPGAs q: Express q Windows-compliant GUI uses standard 0 q: Express q allows you to divide a design between HDL and 0RBschematic input in any proportion and create virtually any design =hierarchy. You can also use functional blocks made from both 7schematics and HDL to reuse modules from common design I1libraries or design sources.qqqq o6)i3qqChoosing Your Synthesis Design Flowq p UT)nqqqFPGAsAq: Express q supports a variety of design flows.q Choose the flow I2that meets your designs requirements. qq qsi!qqqPush-Button q r=)GqIn only two steps you can go from an HDL description or schematic 0:Enetlist to an optimized netlist ready for place and route. The steps Mare simple: First, add your designs source files to the FPGAsDq: : JExpress q project. Then select the target device (vendor, family,  I&package, and speed grade). qq sHi'qqqConstraint-Driven q td_)XqWith FPGAsGq: Express q you can specify design requirements and 0u]%Cconstraints details in the TimeTracker static timing analysis tool I0to tailor the results to your needs. qq ui$qrrMultiple-Devicer v)\rThe FPGAsJr: Express r project manager allows you to design several p҅ Bdevices in the same project. You can add the source files for all Fthe chips on a board. After you identify the top-level design file of Beach chip, the program automatically links the rest of the design I(files in the chip hierarchy. rr HcnH;̕"HcnH  ld;̙  Hcn\~!Hcn\~\~ w UTUTi"rr r Script-Based r  zM)^r You can access all of the functionality of FPGAsMr : Express r via the pz>FPGA Scripting Tool (FST), a Tcl-based command-line language. ?You can use FST to synthesize many chips, either in batch mode IDor interactively, from the shell command line. rrsPr HcnH;̜"HcnH#  ld;̿## Hcn/ !!Hcn/ / ]]]#  UTUT-qsSJr7r8Figure 12r9 shows the flow of FPGA r:KExpressJr; with other tools in these 2JFdesign environments. The steps in this procedure are similar for each >environment; only the method of entering the design into FPGA I=Express differs. Note that simulation is optional.Lr< SL]b iFr=r>r?FPGA Express in Your Design Environmentr@rArB HcnH;"!HcnH &"" ld;&& HcnBk!$HcnBkBk&  UTUTmXrCrDTo use FPGAsVrE: Express rF in your design environment,rG 8dm'rHrIrJCreate the design:rK E]-OrLrMrNFor an rOHDL-based design methodology, write the HDL source UMcode for the design.rPrQ qɃ-ArRrSFor a schematic-based methodology, capture the design 0ư:schematics and export the design in VHDL, Verilog or EDIF Mformat.rTrU -ErVrWFor a mixed (HDL and schematic) design methodology, write 0>the HDL source code for the parts of the design you decide to http://www.synopsys.com/products/fpga/fpga_comp11.html8rr8r  e ?m,p.p/p0p1Featuresp2p3p4 8m1p5p6p7Featuresp8p9r8r A ̒Ym+r Compiler IIB Altera Editionr 7UTNm?pU Compiler?pV7 II8 Altera rEditionr = 1#mr FPGAr  e ?-Pp\p]p^Figure 11p_ summarizes the way that FPGA Compiler II fits in ]sMyour design flow.p` F}V mEpapbpcFPGA Compiler II Design Flow Overview pdpepf 8š-JpgphFigure 12pi summarizes the way that FPGA Compiler II Altera šM'Edition fits in your design flow.pj G mSpkplpmFPGA Compiler II Altera Edition Design Flow Overviewpnpopp #H-MpqprFigure 14ps summarizes the way that FPGA Express fits in your Mdesign flow.pt I m@pupvFPGA Express Design Flow Overviewpwpxrr 7m+r Compiler II8 Altera Editionr m+r Compiler II8 Altera Editionr m+r Compiler II8 Altera Editionr  m+r Compiler II8 Altera Editionr !!-<r, which includes the ability to recognize instantiated M&DesignWare Foundation componentsr "m+r Compiler II8 Altera Editionr #=m<p devices from the leading rFPGA manufacturersr $7m+r Compiler II8 Altera Editionr %=mr FPGA vendor toolsr &7m+r Compiler II8 Altera Editionr 'm+r Compiler II8 Altera Editionr (=mr FPGA vendor tools.r )8m'r Compiler II Altera Edition.r *7m+s Compiler II8 Altera Editions  e 0M UTm"ppppFeaturesp 1?UTš-OppppFPGA Compiler II is a superset of the next-generation FPGA 0š PpNExpress?p synthesis technology. It also includes enhancements >and features that especially benefit high-density FPGA design Mflows:pp !2-AppArchitecture-specific mapping and optimization for all M-leading programmable logic vendorspp 3m>ppIndustry-leading quality of results (QOR)pp 4m?ppComplete programmable logic vendor supportpp 5mKppEasy-to-use design flows and graphical user interfacespp 6mGppIntegrated static timing analysis with TimeTrackerpp !7-MppVista (visual tools for analysis) including pschematic viewing M*with tight links to TimeTrackerpp 8m:ppTcl-based language for pscriptingpp !9-GppSupport for incremental synthesis to enable faster synthesis 9and place-and-route recompilation time and better timing M1preservation for unmodified subdesignspp !:-GpppSupport for register retiming and pipelining to balance Compiler II reads in and writes out dc_shell scripts to allow M4designers migrate between ASICs and FPGAspp !<-9qqSupport for instantiated DesignWare Foundation Mcomponents in HDLqq !=-IqqAbility to export .db database files, so that projects created mPqq Platform-independent licensing for UNIX and Windows NTq q q  !?-Eq Users of the original FPGA Compiler software should install the :new FPGA Compiler II to take advantage of the latest FPGA 7technology. All in-maintenance FPGA Compiler customers M@have been automatically upgraded to FPGA Compiler II.qq @B UTmqqqFeaturesq A8UTš-QqqqqFPGA Compiler II Altera Edition contains all of the powerful 0šqqIndustry-leading quality of results (QOR)q q! DmKq"q#Easy-to-use design flows and graphical user interfacesq$q% EmGq&q'Integrated static timing analysis with TimeTrackerq(q) !F-Mq*q+Vista (Visual tools for analysis) including q,schematic viewing M*with tight links to TimeTrackerq-q. Gm?q/q0Tcl-based language for q1scriptingq2q3q4 !H-Oq5q6q7q8FPGA Compiler II Altera Edition also includes enhancements =and features that especially benefit high-density PLD design Mflows:q9q: !I-Gq;q<q=Support for register retiming and pipelining to balance q? !J-=q@qAdc_shell scripting support for ASIC migrationFPGA m&s< FPGA place and route toolss= ?7m+s? Compiler II8 Altera Editions@ @m+sB Compiler II8 Altera EditionsC Am+sE Compiler II8 Altera EditionsF Bm+sH Compiler II8 Altera EditionsI Cm+sK Compiler II8 Altera EditionsL Dm+sN Compiler II8 Altera EditionsO - e x7m*rrrrASIC-Compatible r !y-LrWith FPGA Compiler II8 Altera Edition7, you can easily migrate ?between ASIC and? FPGA8 PLD7 design flows. You can ;generate dc_shell scripts for any design and can translate MIthem to? fc2_shell8 fc2_altera_shell7 format.rsQsR E e #{?-SrrrFigure 15r shows the flow of FPGA Compiler II with other tools >in these design environments. The steps in this procedure are >similar for each environment; only the method of entering the >design into FPGA Compiler II differs. Note that simulation is Moptional.r |F mJrrr FPGA Compiler II in Your Design Environmentr!r"r# #}8-Lr$r%Figure 16r& shows the flow of FPGA Compiler II Altera Edition Awith other tools in these design environments. The steps in this ?procedure are similar for each environment; only the method of Bentering the design into FPGA Compiler II Altera Edition differs. M'Note that simulation is optional.r' #~G-9r(r)FPGA Compiler II Altera Edition in Your Design MEnvironmentr*r+r, #H-ar-r.Figure 17r/ shows the flow of FPGA r0TExpressHr1 with other tools in ;these design environments. The steps in this procedure are >similar for each environment; only the method of entering the :design into FPGA Express differs. Note that simulation is Moptional.r2 I mPr3r4FPGA Express in Your Design Environmentr5r6HsTHsU G7m+sW Compiler II8 Altera EditionsX Hm+sZ Compiler II8 Altera Editions[ Im+s] Compiler II8 Altera Editions^ Jm+s` Compiler II8 Altera Editionsa K=msc or XNFsd L7m+sf Compiler II8 Altera Editionsg Mm+si Compiler II8 Altera Editionsj F e #7-Rrrrrr(Optional) Export DB database for integration with other M)Synopsys tools.rrsl7sm O=m1so the FPGA vendors development system.sp P8m'sr Compiler II Altera Edition.ss Q=msuFPGA sv CN mp HHˆ;t!HHHˆII ldLeftdRightdcFirstdk Referenced{LinesdFirstd d d d d d d d d !d $d ' dHHIDDEN̎ff\\@P  AboutHead1 Single LineBody. ̎ff\\@P AboutHead1TopOfPage Single LineBody. ffff33\\@P  AboutHead2Indented Single LineBody. ffff33\\@P  AboutHead3Body. ffffG\\@P  AboutHead4Body. ]̅\\@AQ]  AboutTableTitleA:Table < >< >< >< >Body. /\\@O33 ř AboutTitleSpacer Single Line invisibleFIX ME!. ]̇335\\@FQ]  AppEquationTitleF:Equation < >< >< >Figure. ]̅5\\@FQ]  AppExampleTitleF:Example < >< >< >Example. ]̇335\\@FQ]  AppFigureTitleF:Figure < >< >< >Figure. \\@FQH AppLetterSpacerF:< =0>< =0>< =0>< =0>AppTitle. ]̅\\@FQ]  AppTableTitleF:Table < >< >< >Body. /\\@NAO33 ř AppTitle Single Line invisibleN:Body. ffff \\@d   BNF. G/\\@MAVO33 ř ChapTitle Single Line invisibleM:Body. ffff33ff|\\@  Body. ̎ff\\@P XHead1 Single LineBody. ffff33ff|\\@  Body. @{  BookTitleSpacerHalf Single Line. Hff̂/\\@H Bullet\t. VffĤ/\\@Vff Bullet2-\t. ق\\@  F qff Caption. Hff33ff|\\@AH l  ff CautionEmphasisCaution!Body. \\@AQH ChapNumberSpacerA:< =0>< =0>< =0>< =0> ChapTitle. /\\@MAO33 ř ChapTitle Single Line invisibleM:Body. ffff|\\@P   DisplayHeadBody. ]̇335\\@AQ]  EquationTitleA:Equation < >< >< >Figure. ]̇335\\@AQ]  EquationTitleNoChapA:Equation < >< >< >< >Figure. ffffQp|\\@d  R s33   ff  33 5 V vff  33 Example. VffVffQp|\\@d  s33   ff  33 5 V vff  33 Example2Indent. HHQp|\\@d  s33   ff  33 5 V vff  33 ExampleIndent. ]̅5\\@AQ]  ExampleTitleA:Example < >< >< >Example. ]̅5\\@AQ]  ExampleTitleNoChapA:Example < >< >< >< >Example. \\@d  ff R s33   ff  33 5 V vff  33 ExampleWide. ffff1@@ FigureBody. ]̇335\\@AQ]  FigureTitleA:Figure < >< >< >Figure. ]̇335\\@AQ]  FigureTitleNoChapA:Figure < >< >< >< >Figure. 1@@  FigureWideBody. قف\\@  Footnote. ffff33p@ GlossaryBody. ffff33@  GlossaryTerm. Hff33|\\@R HangIndent. VffH33|\\@Vff D HangIndent2. HH33|\\@l  D HangIndentPara. ffff33|\\@R HangIndentTerm. ̎ff\\@P Head1 Single LineBody. ffff33\\@P Head2Indented Single LineBody. ffff33\\@P Head3Body. ffffG\\@P Head4Body. @  LegalBody. Hff33|\\@QR LimitStart Limitation:Body. HH33|\\@QR LimitStart2 Limitation:Body. HHff/\\@l  D ListPara. VffVff33|\\@ff .ff ff ListPara2. Hff33ff|\\@AR NoteNote:Body. Hff33|\\@QR NoteStartNote:Body. HH33|\\@QR NoteStart2Note:Body. Hff̂/\\@GAH Number G:.\tNumber. VffH33\\@HAVff Z. ff. Number2 H:.\tNumber2. VffF\33\\@HAVff. Z. ff. Number2First H:.\tNumber2. Hff̂/\\@GAH. NumberFirst G:.\tNumber. ll33ff|\\@@. . PartBodyPartBody. l\\@PAdl. ř. PartTitleSpacer Double LineP:Part PartBody. Hff33|\\@QR. ShortcutStart Shortcut:Body. HH33|\\@QR. ShortcutStart2 Shortcut:Body. Hff̂/\\@GAH. Step G:.\tStep. HĤ/\\@l. . D. StepBody. Hff̂/\\@GAH. StepFirst G:.\tStep. ffffff|\\@P. . StepHead StepFirst. Hff̂/\\@H. StepOnly\t. ffff\\@  R. s33. . . ff. . 33. 5. V. vff. . 33. Syntax. Hff33|\\@R. SynTerm. ff5\\@ ff. . 33. H. TableBulleted\t. 5\\@ . 33. H. TableCell. قف\\@ . TableFootnote. 5\\@  Q. c. TableHead. ff5\\@ ff. . 33. H. TableNumbered.\t. ff5\\@ ff. . 33. H. TableNumberedFirst.\t. ]̅\\@AQ]. . TableTitleA:Table -< >< >< >Body. ]̅\\@AQ]. . TableTitleNoChapA:Table < >< >< >< >Body. \\@. 33. H. TabularListBody. /\\@O33. ř. TitleSpacer Single Line. \\@ TitleBody. Hff33|\\@QR. WarnStartCaution!Body. HH33|\\@QR. WarnStart2Caution!Body. A@@  ' $. H. l. . . . . . D. h. . TableCellHead. 5\\@ . 33. H. TableCell. ffff33ff|\\@   Body. 5\\@  Q. c. TableHead. ]̅\\@AQ]. . TableTitleA:Table -< >< >< >Body. @@ &Body. \\@ . 33. H. TabularListBody. ق\\@ . F. qff. FooterTitleLeft. ffff33ff|\\@ . . Body. ق\\@ . F. qff. FooterTitle. \\@AQH ChapNumberSpacerA:< =0>< =0>< =0>< =0> ChapTitle. /\\@MA6O33 ř ChapTitle Single Line invisibleM:Body. ffff33ff|\\@   Body. Hff̂/\\@1 H Bullet\t. Hff̂/\\@ H Bullet\t. ̎ff\\@P Head1 Single LineBody. ]̇335\\@Aa]  FigureTitleA:Figure < >< >< >Figure. ]̇335\\@AA]  FigureTitleA:Figure < >< >< >Figure. Hff̂/\\@GA H. NumberFirst G:.\tNumber. HHff/\\@ l  D ListPara. Hff̂/\\@GA H Number G:.\tNumber. ̎ff\\@P Head1 Single LineBody. Hff̂/\\@ H Bullet\t. ffff33\\@P Head2Indented Single LineBody. ffffff|\\@P . . StepHead StepFirst. Hff̂/\\@GA H. StepFirst G:.\tStep. VffĤ/\\@ Vff Bullet2-\t. Hff̂/\\@GA H. Step G:.\tStep. ffff33ff|\\@  Body. ffff33ff|\\@  Body. ffff33ff|\\@W  Body. ffff33ff|\\@  Body. HHff/\\@l  D ListPara. HHff/\\@l  D ListPara. HHff/\\@l  D ListPara. HHff/\\@l  D ListPara. HHff/\\@l  D ListPara. HHff/\\@l  D ListPara. HHff/\\@l  D ListPara. HHff/\\@l  D ListPara. ffff33ff|\\@  Body. ffff33ff|\\@  Body. ffff33ff|\\@  Body. ffff33ff|\\@  Body. ffff33ff|\\@  Body. ffff33ff|\\@  Body. ffff33ff|\\@  Body. ̎ff\\@P XHead1 Single LineBody. ffff33ff|\\@  Body. ffff33\\@P YHead2Indented Single LineBody. ffff33ff|\\@  Body. HHff/\\@l  D ListPara. ffff33ff|\\@  Body. HHff/\\@l  D ListPara. HHff/\\@l  D ListPara. HHff/\\@l  D ListPara. HHff/\\@l  D ListPara. ffff33ff|\\@  Body. ffffff|\\@P. . StepHead StepFirst. Hff̂/\\@GAH. Step G:.\tStep. Hff̂/\\@GAH. Step G:.\tStep. Hff̂/\\@GAH. Step G:.\tStep. Hff̂/\\@GAH. Step G:.\tStep. HHff/\\@l  D ListPara. Hff̂/\\@GAH. Step G:.\tStep. #ffff33ff|\\@  Body. ffff33ff|\\@  Body.  bnfmodifier   bnfreserved[ [ yc>yc>Hyc>yc> yc> yc> [ doctitle  emphbold emphitalicfilenamehotlink# invisible  kbdinput QUERY subscript superscriptsyntaxtechtermuserdef VarText wordasword ڝ [  [  yc> [  [  [  j[  [  [ Hyc>yc>yc>yc> emphitalicyc> invisibleyc>yc> yc> emphitalicyc>yc>yc>yc>hotlinkyc>yc> emphitalic[ [ [  [  emphitalicyc>yc>yc>yc>yc>yc> emphitalicyc>[ yc> emphitalic[ [ [  emphitalicyc> emphitalicyc> invisibleyc>[ [ (ddZdddZdZddZddddd ddddddddZdZdddZdddddd@dddzdZdZdZd Weight Four DoubleWeight Three DoubleWeight Two DoubleWeight One Double Weight Four Weight Three Weight Two Weight OneThickThinDoubleff33ffMMZ33XYXXYX OptionTable3333 \[Y[[Y[[Y[Wide33 ][Y[[Y[[Y[ WideNoTitle33ffff Z^^^^^^ TabularList33ff33 \3#[Y[3#[Y[3#[Y[ TextColumn33ff ]3#[Y[3#[Y[3#[Y[TextColumnNoTitlefae fc2 fcX fefe_A OutQueryT.N^Z;uV , =>;qtG.0Z;z v ;s]^;uY A@0./AZ;u_ .A0;z D@ DZ;z xD8 V9Z;|/ 9 b;U_  W c;Ue  1 W;  emphitalic )Z;ZH-  . XYZ;Un  XY;  emphitalic`nT;t .nZ;t.Z;t.MMZ;t # &Z;U$ )Z;Wp Zdd.d;Wsddd" Z;Wy .f;W| ;W ;"Z;t .f;t ;t <"NZ;u .f;u  ;u  ="#!!Z;A8 . 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U.egf;$V.efk;0W"^eikZ;> X.hjf;AY.hikk;QZ.hjk;V [k ;\ emphitalicV[nZ;gj ]Kmoo;X^#mnpZ;XG _)otqqZ;X `Zdd.p "d;X adddq ! ;b emphitalicq!";X(Index"opyuwZ;X c.twv#f;X du#;X)Index.tu$%k;X ew$% ;f emphitalic"ot~z|Z;X g.y|{&f;X hz&;X*Index.yz'(k;X i|'(;j emphitalic"oyZ;X k.~)f;Y l);Y+Index.~*+k;Y m*+;n emphitalic"o~Z;Y o.,f;Y p,;Y,Index.-.k;Y q-.;r emphitalic"R Z;z s. /f;z t /;zNIndex. k;zu i;zy  ;{.1Z;{a z1;{d E@Z;{j |Ei;{m}E ;{q\.3Z;{ ~2;{ F23X;{ emphitalic@SFZ;{ Fi;{ ;{.mo5Z;s 4;s G45;s emphitalic@mGZ;s GHi;sH-mTZ;ۚ !67Ip;c7  I67;c:  emphitalic+,""Z;u  &!#$Z;x  ."$q;1  #"#%*Z;ܩ"$(&&Z;ܬ .%89r;ܯ &89;ܱ 0Index"$%*))Z;ܻ .(r;ܾ"$(++Z; .*r;+!1--Z; &,..Z; .-:<s; .:;;1Index.;<;2Index+,522Z; &133Z; .2=>s;) 3=>; emphitalic+1966Z;? &577Z;? .6?@s;? 7?@;? emphitalic+5=::Z;?  &9;;Z;? !.:ABs;? ";AB;?# emphitalic+9A>>Z;? $&=??Z;? %.>CDs;? &?CD;?' emphitalic+=KBBZ; (&ACEZ; ).BEEFs; *CEF;3Index.BCGHk; +EGH;9, emphitalic+STHHZ;| -&GIIZ;| ..HJIs;| /II;|iIndex+APLLZ; 0&KMMZ; 1.LNOs; 2MJ;5IndexMJ;tt3 emphitalic+KTQQZ;G 4&PRRZ;K 5.QKLs;V 6RKL;X6Index+PUUZ;k 7&TVVZ;o 8.Us;x9 c;t1Z;tZ;t*+g;u*+g;u,-Z;uB,-Z;uC;vU01;vV56;vW:;<Z :<Z ABd;vcddABd;vdddEFk;vuEFk;vvIJk;vIJk;vKLk;vKLk;vNOlPQk;vOP;vhIndex;}>STk;vSTk;vWXk;w WXk;w YZk;wDYZk;wE]^k;wW]^k;wXcde;xce;xqr;xqr;xtu;xtu;xyz;x ;x;x;x;x;x;x;x,-d/dd,-d0dd9:f19:f2<=f3<=f4@AZ;x@AZ;xDEZ;yDEZ;yGHo9IJZ;yAIJKZ;yBIKZ;yCOPZ;y}OPZ;y~TUZ;yTUZ;yWXm;yWXm;yYZZ;yYZZ;y\]o;y`ad;zdd`ad;zddklk;zJklk;zKqrd;z_ddqrsd;z`ddqsd;zadduvfMwxk;zuwxk;zvz{fP|}k;z|}k;zfSk;zk;zfVk;zk;z ;z;|<;|=;|>;|?Z^Z_ p;|N p;|O&'rb &'rc ./sd./0se.0sf34s;|d34s;|e78s;|z78s;|{;<s;|;<s;|?@s;|?@s;|CDsoCDspEFk;|EFk;|IJ;|MNOs;}#RSsuRSsvv;t=hotlink;}?7m;}@m_;}A2;}B2;}CG;}DG;}E`: ( Title&*2 .<=*-M#>?@,A! .Intro9K .<=*-M#>?@,A!  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List-introt CCBDDefinition-listP & ' (&.Step..Note()*+(   + Procedure/0: ( Body %&'+238:;<=>= Printedin-.= Ordernumber =Titleversionref012/ 0 1/Bookinfo= Booktitle BookTitleAB ( Footnote TableFootnote= (4  Cell-itemI= (4  Cell-bodyEF6 5 5 6 Cell-list     ChapterB 7 (4  Entry= Versiondate>?@3 : 23Cover (  Example-lineExampleXY[< Example-block EEquation  <= Example  Figure\ ] ^ _TableD $Definition-itemBDefinition-group: ( Term  Equation-art=Toc=Lof=Lot=LoeF G H IFront: ( HeadHead1ijklHypertext-markerp [ Y* [ Syntax-spec'; J   8 8   %  Manual#$%&' (  Menu-itemwx X U Option-item P Option-body ( Option-label1 TableHead ( Option-label2 TableHead  R SR SOption-column-labels4 ( Option-description TableCell TT Option-headV QV Q Option-group4 (  Option-name TableCell WWV Option-list 9Row ( SyntaxSyntax : ( Ttitle TableTitle56 ZThead ZTbody ZTfootNoName=;J;M;Q;^ ;a ;e 0 H K Q UM [^a;t;t !;t"G;t#Lz$'}%&(-),*+;W/4;t03;t12;t5J;u69;u78;u :? ;>!<=;A=@E#AD$BC;FK&GJ'HI;NG)OS*QR+T[,WY-]`;uU^_;uXaf;u^bd.;uagj0;uhi;ukp2;uln3;uqt5;vrs ;vuV7;v vw8;vy~:+z{ ;qX|}<2=8>;F?C @F AI BM CTDWE\F_ GfHiInJqKwL{!.M"$N%)P&'Q*-S+,T/;U02V36W45X7:Y89Z*.;xD+-;xG/3;xO02;xR5P;x[6:;x^79;xa;?;xi<>;xl@C;xtAB ;xwDG!;x}EF";xHK#;xIJ$;xLO%;xMN&;xQR';xS}(TV)W|*X]+Y\,Z[-^a._`/!be0'cd1*g 2;xhi3;xjm49kl5<nq6Bop7Erv8Ksu9Nw{;Vxz<Y~.>c?f@lAo BuCx D} EFGIJKL$MN!O P"#Q%-R&(S),T*+U//V04W23X59Y78Z:a[;?\=>]@`^AF_BE`CDaGMbHJcKLd NTeOQfRSgU_h!VXi$YZj*[^k/\]l2b.m;cdn>eoCflpFgkqIhirLmutUnpuXqtw_rsxcv~yiwyzlz}|s{|}v~}   Q;z ;z ;z;z ;z#;z! ;z$';{`%& ;{c(,;{i)*;{l-2;{./ ;{01;{3T;{45;{7<89;s:;=B>@C- DGEF H\!I["JK#LZ$#MQ%&NP&)RU(1ST)4VY*:WX+=]d,F^c-I_b.Lel1Wfk2Zgj3]hi4`mt5hns6kor7npq8qu|9yv{:|wz;xy<}=~>?@AB C E FlG;|H;|I;|KLMO &P!%Q"$R',T(+U)*V12;r34;u56 ;yEFM;tdBlackT!WhiteddARedddGreendd BluedCyandMagentad Yellowd Blue GreenCrayon Blue GreencPANTONE Yellow 012 CVCPANTONE CoatedPANTONE Yellow 012 CVCZPPANTONE Purple CVCPANTONE CoatedPANTONE Purple CVCd'PANTONE Process Cyan CVPYt TRUMATCH 1-aTRUMATCH 4-Color Selector TRUMATCH 1-aYt TOYO 0001pc*TOYO COLOR FINDER TOYO 0001pc*dE BittersweetCrayon Bittersweet^dPANTONE Green CVC&c TOYO 0007pc*cPANTONE Rubine Red CVCPANTONE CoatedPANTONE Rubine Red CVC9dRED^d&GREENddColor 8dC7@PPindigoFGpuce[[È<= Red_QueryccMaroon FOCOLTONEFCS 2249SalmonMUNSELL High Chroma ColorsMunsell 2.5R 6:14V|xOrangePANTONE ProSimPANTONE Orange 021 CVPdd2Color 920Id#>% DefinitionI Sequence-type<$ UnorderedO2OrderedWType<:GenericTCommand3:Optionv1Argument4SwitchKeywordE-Variable? Attribute73Style,1Italict!Bold4Align"-Left Center Rightc4Justify(Char)Charoff7(Valign6Top%MiddleQ,Bottom6)Width EWide!+Not-wide% Target-Margin@Inline>7 Productname;+ Manualtype Version Date9 Docnumber-<Infoy Limitationj$ShortcutC0Warning8Value *Country the U.S.A. Kind2]Tutorial-exercise ChapterTitle0] AppendixTitle}Yi999999[i100000:CBGBCEGIHgpBGBJAFEEXBGBHDHBEOUBGBFDHDE;jCHDJEIFBQBGBIDJJG0kBGBGADCIDfBGBGHHEINBGBEHHCIgBGBBADJC&UBGEFDDHBARBGEIDHFJi[CHDFGFBF?jBGBCGBIBEPartBodyBodyBulletListParaBullet2 ListPara2BulletListPara NumberFirst NumberFirstNumberListPara Number2First Number2FirstNumber2 ListPara2 NumberFirst NumberFirstNumberListPara GlossaryBodyHangIndentParaStepOnly StepFirstStepOnly StepFirstStepListParaListParaDD GlossaryBodyListParaBody ListPara2ListPara @ TableCell TableNumberedFirstTableNumberedFirst TableNumbered TableBulleted> ExampleWideExample2Indent ExampleIndent ExampleIndentExample@ GL invisibleHead2Head3Head4AboutHead1TopOfPageAboutHead1TopOfPage AboutHead1 AboutHead2 AboutHead3 AboutHead4D DisplayHead NoteStart2ShortcutStart2 LimitStart2 WarnStart2 NoteStart ShortcutStart LimitStart WarnStart ChapNumber AppLetterArgument Description LegalBody LegalBody@ CC< GlossaryTermHangIndentTerm PartTitle ChapTitle FigureTitle EquationTitle ExampleTitleStepHeadAppTitleAppFigureTitleAppEquationTitleAppExampleTitleStepHead AboutTitleFigureTitleNoChapEquationTitleNoChapExampleTitleNoChapStepHead LegalBodyAboutTableTitle AppTableTitle TitleBody  .C.D.EHKEFGHIJKLM.NTZNOSOPQRTUYUVWXZ[_[\]^.`a.bbckcdgjdefghi.llmn.op.qrs.t.uv.wx3{3|665   *< <!!"#<$$%&((*%-%.K=>?@ABKCDEFGHKIKJLLNP)ROVOWXZ,f,glghijklmnop stWvRxSz0}0~///'  D'(.4()*+,-./0123456789:<1@1A1B\E\FHJ:N:O:PR, bnfmodifier  bnfreserved66% & ! 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