############################################################################### ############################################################################### # # # FILE NAME: dc_err # # ABSTRACT: Keep track of all error messages in executable. # # COPYRIGHT (C) 1995, SYNOPSYS INC., ALL RIGHTS RESERVED. # ############################################################################### ############################################################################### W ATTR-1 Attribute '%s' has not been defined for %ss W ATTR-2 Attribute '%s' is not user-defined for %ss; can't %s it W ATTR-3 Attribute '%s' does not exist on %s '%s' W ATTR-4 Value '%s' is not valid for '%s' on %ss W ATTR-5 Value '%s' for '%s' is not in range (%s) W ATTR-6 Value '%s' for '%s' is not valid. Specify one of:\n\t%s E BS-1 Every block in a design built for scheduling must be\n\ \ttriggered by a clock%s E BS-2 Blocks with an asynchronous reset are not supported\n\ \tin designs being built for scheduling%s E BS-3 Blocks with three state devices are not supported\n\ \tin designs being built for scheduling%s E CDNO-1 Design '%s' has no schematic. E CDNO-2 Can't find the sheet template symbol for schematic '%s'. W CDNO-3 Unnamed off-sheet connector encountered--pinInstance command not written. W CDNO-4 Unnamed port encountered--pinInstance command not written. W CDNO-5 Unnamed cell encountered--instance command not written. W CDNO-6 Duplicate cell name '%s' renamed to '%s'. E CHR-001 Cannot specify '-no_timing' unless '-constraints' or '-connections'\n\ \tis also specified. E CHR-002 Characterize failed. E CHR-003 Cannot characterize leaf cell '%s'. W CHR-004 There are multiple clocks in the fanin of pin '%s'\n\ \ton cell '%s'. Ignoring clock '%s'. E CLUS-2 Cell %s could not be assigned to a cluster. I CLUS-3 Loading route layer data from technology library: %s. W CLUS-4 Could not generate 'preferred' region for new cell %s in cluster %s. E CMD-001 Cannot specify '%s' with '%s'. E CMD-002 Value for '%s' cannot be negative E CMD-003 Cannot specify %s without %s. E CMD-004 Must specify one of these options: %s. E CMD-005 unknown command '%s' E CMD-006 ambiguous command '%s' matched %d commands:\n\t(%s) E CMD-007 Required argument '%s' was not found E CMD-008 value not specified for option '%s' E CMD-009 value '%s' for option '%s' not of type '%s' E CMD-010 unknown option '%s' E CMD-011 ambiguous option '%s' E CMD-012 extra positional option '%s' E CMD-013 %s\n\tUse error_info for more info. E CMD-014 Invalid %s value '%s' in list. E CMD-015 could not open %s file \"%s\" E CMD-016 could not close %s file \"%s\" W CMD-017 duplicate option '%s' ignored. W CMD-018 duplicate option '%s' overrides previous value. E CMD-019 value '%s' for option '%s' not in range (%s). E CMD-020 unknown OR extra positional option '%s' W CMD-021 invoked %s outside of a loop W CMD-022 Can't create alias named '%s' - %s%s. E CMD-023 Alias loop: %s E CMD-024 Can't %s %s: %s E CMD-025 No manual entry for '%s' E CMD-026 %s required for the '%s' argument. E CMD-027 couldn't change working directory to '%s' E CMD-028 couldn't get working directory name W CMD-029 no aliases matched '%s' W CMD-030 File '%s' was not found in search path. W CMD-031 value '%s' for option '%s' is not valid. Specify one of:\n\t%s W CMD-032 command '%s' requires some options. E CMD-033 cannot source the current log file. E CMD-035 Value for %s cannot be larger than the %s value. E CMD-036 Value for list '%s' must have %s elements. E CMD-037 value '%s' for option '%s' is invalid: must be %s. I CMD-038 The '%s' option for %s is unsupported.%s I CMD-039 The '%s' variable is unsupported.%s I CMD-040 No %s matched '%s'. I CMD-041 Defining new variable '%s'. E CMD-050 Unknown procedure '%s'. E CMD-051 Procedure '%s' cannot be modified. E CMD-052 Unknown command group '%s' W CMD-053 The body of procedure '%s' is protected E CMD-060 Syntax error in argument definition %d for proc '%s'. E CMD-061 Need at least 2 fields in argument definition %d for proc '%s'. E CMD-062 Unknown %s '%s' in argument definition %d (%s) for proc '%s'. E CMD-063 Illegal name '%s' for Boolean argument definition %d for\n\ \t proc '%s': must begin with '-'. W CMD-064 Value help ignored for Boolean option %s\n\ \tin argument definition %d for proc '%s'. E CMD-065 Can't specify both 'optional' and 'required' in argument\n\tdefinition %d (%s) for procedure '%s' E CMD-066 Must specify a value for attribute 'values' when using '%s'\noption type as in option %d (%s) for procedure '%s' E CMD-067 Invalid attribute specification for attribute '%s'\n\t(%s)\n\tin option %d (%s) for procedure '%s' E CMD-068 Could not find procedure '%s'. Arguments can't be parsed. E CMD-069 Could not set '%s(%s)' while parsing arguments in '%s'. E CMD-070 parse_proc_arguments can only be called from within a procedure E CNTXT-001 Cannot characterize context in min and max mode. I CNTXT-002 Characterizing the context for cell '%s' I CNTXT-003 Deleting the context for cell '%s' E CNTXT-004 This command applies to hierarchical cells only\n\ \t Cell '%s' is a leaf cell. E CONV-1 Undefined variable on or near line %d at or near '%s'. E CONV-2 Undefined operator on or near line %d at or near '%s'. E CONV-3 Incorrect number of operands on or near line %d at or near '%s'. E CONV-4 Invalid operand type on or near line %d at or near '%s'. E CONV-5 Evaluation error on or near line %d at or near '%s'. E CONV-6 Internal error. E CONV-7 Evaluation error on or near line %d at or near '%s'. E CONV-8 Error on or near line %d at or near '%s'\n\ %s E CONV-9 Operator used in bad context on or near line %d at or near '%s'. E CONV-10 Defining new variable '%s'. E DB-1 File is not a DB file. W DB-3 Can't locate file '%s'. E DB-4 Open gen_state (0x%x) -- %s object '%s' (0x%x)\n\ attach '%s' id = %d E DBCK-1 Line is not connected to anything - Sheet: %s. E DBCK-2 Endpoint of a line touches a line of another net - Sheet: %s. E DBCK-3 Schematic has coexistent lines of different nets - Sheet: %s. I DBCK-4 Input cell/pin (%s) is not driven, assumed to be shorted to logic 0. E DBR-001 Cannot read file '%s'. I DBR-002 Errors reading file '%s'. W DBR-003 Design '%s' (file '%s')\n\ \tis already registered. Remove the design before rereading. W DBR-004 Library '%s' (file '%s')\n\ \tis already registered. I DBR-005 Errors reading design '%s'; the linker will not resolve references to it. E DBR-006 Unknown pin '%s' makes instance '%s' of '%s'\n\ \tin design '%s' inconsistent with previous instances. W DBR-007 Found unsupported LSI reference '%s' to '%s' in design '%s'.\n\ \tThe linker will not be able to resolve this reference. E DBR-008 Cannot remove library '%s'. The following cells of the\n\ library are referenced:\n\ \t%s W DBR-009 Found name-based LSI reference '%s' to '%s' in design '%s'.\n\ \tThe linker might not be able to resolve this reference. E DBR-010 Cannot access temp directory '%s'%s. E DBR-011 Problem in read_%s: %s. E DBR-012 Cannot read design db files. A db file must be a library. E DBR-013 read_min_max_lib can only merge libraries. E DBR-014 multiple libraries in a single DB not supported. W DBR-015 ignoring degenerated cell '%s' from library '%s'. E DBR-016 cannot find port '%s' for cell '%s' in all libraries. E DBR-017 cannot find %s '%s' in all libraries. E DBR-018 %s value '%g' of operating condition '%s' is different from the nominal %s value '%g'. E DBR-019 cannot find operating condition '%s' in library '%s'. I DBR-020 Renamed scalar net '%s' to '%s' in design '%s'. W DBR-021 Library file '%s'\n\ \tis already registered. E DBR-022 Template %s is not the same in min and max libraries. E DBR-023 Duplicate reference port '%s/%s' in module %s\n\ \tending at line %d in %s E DBR-030 Invalid global reference '%s' - \n\ \t%s\n\ \tin module ending at line %d in %s E DBRBO-1 Attribute '%s' does not have valid values. E DBSEC-1 Can't read %s; it contains protected data generated by %s. E DBSGE-1 Symbol library '%s' has symbols with off-grid pins. Check to make sure that the variable 'grid_pins : true' is defined in the symbol library source file (.slib file) and recreate the symbol library with a v2.2b or later version of dc_shell or design analyzer. E DBSGE-2 Sheet size for the schematic of the design '%s' is \ too large for SGE. Regenerate the schematic with a smaller sheet size. W DBSGE-3 Unable to place a part of net '%s' from sheet '%s'. E DBSGE-4 Error in saving the schematic for design '%s'. W DBSGE-5 The name for off-sheet connector '%s' could not be \ placed on sheet '%s'. I DBSGE-6 Transferring symbol '%s'. E DBSGE-7 The width of the pin '%s' in design '%s' is too large. There will be an error in the configuration declaration part of the VHDL generated from this SGE symbol. W DBSGE-8 File '%s' already exists. Did not overwrite it. W DBSGE-9 No symbol found for library cell '%s'. W DBSGE-10 The name for net '%s' could not be placed on \ sheet '%s'. W DBSGE-11 The name for port '%s' could not be placed on \ sheet '%s'. W DBSGE-12 Overwrote existing file '%s'. E DBSGE-13 Transfer the schematic again using the -ripper option. E DBSGE-14 Schematic for '%s' is an older version. Regenerate\nthe schematic and run db2sge on the newer version of the schematic. W DBSGE-15 Could not create symbol for '%s'. E DBSGE-16 Symbol library '%s' does not have a route grid \ specified. E DBSGE-17 Symbol libraries '%s' and '%s' have different \ route grids. E DBSGE-18 Route grid of schematic of '%s' differs from that of \ other schematics in '%s'. W DBSGE-19 Design '%s' could not be found in the given \ database file. E DBSGE-20 No designs specified whose schematics can be \ transferred. E DBSGE-21 Error in opening file '%s' for writing. E DBSGE-22 Port '%s' is connected to more than one net or bus. I DBSGE-23 Transferring schematic for the design "%s". E DBSGE-24 Could not create directory '%s'. E DBSGE-25 Cannot read the file '%s'. E DBSGE-26 There is no schematic for the design '%s'. Please \ generate the schematic for this design and run db2sge again. E DBSGE-27 Schematic for '%s' is not generated with the -sge \ option. Regenerate the schematic and run db2sge on the newer version of the \ schematic. E DBSGE-28 A compound name in the design '%s' is too long. \ Regenerating the schematic for this design without busses and then running \ db2sge may work. E DBSGE-29 There is no symbol for the design '%s'. Please generate\ the schematic for this design and run db2sge again. E DBSGE-30 You cannot use the bustaps option to transfer this \ schematic to SGE. E DBSGE-31 '%s' is not a symbol library file. E DBSGE-32 '%s' is not a technology library file. E DBSGE-33 Error in translation. Did not save symbol for '%s'. E DBSGE-34 Error in translation. Did not save schematic for the design '%s'. E DBSGE-35 Error in saving the symbol '%s'. E DBSGE-36 Schematic for '%s' is generated with the -sge option. Regenerate the schematic without this option. W DBSGE-37 Library '%s' was created with an older version of Synopsys software. You may potentially get VHDL-illegal names from this. E DBSGE-38 Cannot find the library '%s' in the specified search path. E DBSGE-40 %s. E DBSGE-41 There are ports on the design whose direction is not defined. Hence type information cannot be transferred to SGE. E DBSGE-42 Some ports on the design have bad types. Hence type information cannot be transferred to SGE. W DBVH-1 Time units are not specified in the '%s' library. E DBVH-2 The '%s' library contains no valid library cells. W DBVH-3 The '%s' pin on the '%s' cell has duplicate timing constraints.\n\ \tOnly one of them is used. W DBVH-4 The '%s' pin on the '%s' cell has duplicate timing arcs.\n\ \tOnly one of the timing arc is used. W DBVH-5 The '%s' pin has an invalid timing type related to '%s'.\n\ \tThe invalid timing arc is ignored. E DBVH-6 The '%s' pin is unused in the '%s' sequential cell. E DBVH-7 Missing timing arc between '%s' and '%s' pins in the '%s' cell. W DBVH-8 The '%s' pin on the '%s' cell has no 'function' attribute. W DBVH-9 The '%s' pin on the '%s' cell has an unknown direction.\n\ \tThe direction defaults to inout. W DBVH-10 The '%s' function on the '%s' pin in the '%s' cell is not recognized. W DBVH-11 The '%s' pin has an unsupported constraint related to '%s'.\n\ \tThe invalid timing arc is ignored. W DBVH-12 The '%s' cell has constraints with both rise and fall edges. E DBVH-13 Could not open '%s' file for writing. W DBVH-14 The '%s' pin in the '%s' cell is related to more than one output. W DBVH-15 The '%s' cell contains circular timing arcs. The '%s' pin\n\ \tis in one of the cycles. W DBVH-16 The '%s' pin in the '%s' cell is related to an output and\n\ \tthe '%s' input pin. W DBVH-17 The '%s' cell has two opposite output pins, '%s' and '%s',\n\ \twith the same '%s' value. The '%s' pin should not be related\n\ \tto the opposite '%s' output. E DBVH-18 The '%s' pin is missing. E DBVH-19 The '%s' cell has more than %d pins. W DBVH-20 The '%s' pin is unused in the '%s' cell. W DBVH-21 The '%s' time is a nonpositive setup or hold constraint. E DBVH-22 The '%s' cell is overwriting the '%s' cell in the '%s' library. W DBVH-23 The minimum period attribute is allowed only on clock pins. \n\ \tThe '%s' port has a minimum period constraint and is not a clock.\n\ \tThe constraint is ignored. W DBVH-24 The driver_type attribute on the '%s' pin is ignored. E DBVH-25 Cannot read the '%s' file. W DBVH-26 Unknown '%s' architecture in vhdllib_architecture.\n\ \tThe unknown architecture is ignored. E DBVH-27 The '%s' cell component is not in vhdlmacro library. W DBVH-28 The 'U%d' component instance has open pins. E DBVH-29 Cell cannot have both force_00 and force_11.\n\ \tTry another force combination. W DBVH-30 Missing timing arc between '%s' and '%s' pins in the '%s' cell.\n\ \tA timing arc is estimated. W DBVH-31 A pull-up or pull-down on the '%s' input pin is not visible\n\ \toutside the cell. Make the pin an inout pin. W DBVH-32 '%s' to '%s' %s input delay ranges %0.3f to %0.3f.\n\ \tThe maximum input delay %0.3f is chosen. W DBVH-33 Could not lump all the timing related to the '%s' pin. W DBVH-34 Timing arcs related to the '%s' pin have inconsistent timing\n\ \tsense. The pin is chosen to be active %s in the recovery checker. W DBVH-35 The '%s' pin is related to an output and only some\n\ \tasynchronous inputs. All asynchronous inputs are ignored. W DBVH-36 The '%s' pin is a clock, and bundled clocks are not supported. E DBVH-37 Unknown logic system '%s' in vhdllib_logic_system.\n\ \tUse the logic system 'IEEE-1164'. Aborting the execution. E DBVH-38 The '%s' pin on the '%s' cell has a timing arc whose\n\ \trelated_pin '%s' is not functionally related. E DBVH-39 The '%s' pin on the '%s' cell has duplicate delay paths\n\ \tfrom the '%s' related pin. E DBVH-40 The '%s' pin on the '%s' cell has 5 or more parameters\n\ \tin the 'three_state' function. E DBVH-41 The '%s' function on the '%s' sequential cell has\n\ \tmore than 5 parameters. E DBVH-42 The functionally unrelated output timing arc is defined in the\n \ \t'%s' pin group with the '%s' related pin on the '%s' cell. E DBVH-43 An obsolete 'state' group is found in the '%s' sequential cell.\n\ \tUse the 'ff' group or 'latch' group instead. E DBVH-44 The '%s' master-slave cell is currently not supported. E DBVH-45 Neither the 'next_state' nor 'data_in' function is\n\ \tdefined in the '%s' cell. E DBVH-46 Neither the 'clocked_on' nor 'enable' function is\n\ \tdefined in the '%s' cell. W DBVH-47 The '%s' input pin active edge is unknown in\n\ \tthe '%s' sequential cell. W DBVH-48 Unknown pulse handling algorithm '%s' in the\n\ \tvhdllib_pulse_handle. Use the default value "use_vhdllib_glitch_handle". W DBVH-49 Unable to properly associate timing with the '%s' function.\n\ \tAll related timing arcs defined in the '%s' output pin group of the '%s' cell are ignored. W DBVH-50 The 'clear_preset_var1'/'clear_preset_var2' value is incompatible\n\ \twith the asynchronous timing arcs in the '%s' output pin group of the '%s' cell.\n\ \tOne or more asynchronous timing arcs are ignored. E DBVH-51 The '%s' output pin on the '%s' sequential cell with an\n\ \toutput timing arc has 5 or more asynchronous timing arcs.\n\ \tCurrently, this is not supported. E DBVH-52 Incomplete functional and/or timing information is\n\ \tspecified for the '%s' cell. The cell is a black box. W DBVH-53 The '%s' pin on the '%s' cell has duplicate '%s' timing arcs\n\ \tfrom the same related_pin. Only one of them is used. W DBVH-55 The inertial algorithm is chosen as the pulse handling algorithm for FTGS models. E DBVH-57 The '%s' cell component is not in the testsimmacro library. E DBVH-58 Unable to find a nonscan equivalent cell in the current library. W DBVH-59 A minimum pulse-width constraint on '%s' is only allowed on\n\ \tclock and asynchronous clear/preset pins. The constraint is ignored. W DBVH-60 Using the nonscan equivalent cell, the fault simulation structural\n\ \t model will model the nonscan behavior only. E DBVH-61 MVL7 is not an acceptable logic system in the VITAL\n\ \tarchitecture, so VITAL architecture is not generated. W DBVH-62 The '%s' output pin has an output-related timing arc from\n\ \t the '%s' output. All timing arcs of the '%s' pin are ignored. W DBVH-63 The '%s' output pin has undefined value if both clear and\n\ \t preset are active. Force the output value to X. E DBVH-64 Cannot write the library to the '%s' file. E DBVH-65 Design compiler does not recognize the cell's function. E DBVH-66 The vhdllib_logic_system is set to the obsolete 'MVL7' logic system.\n\ \tUse the 'IEEE-1164' logic system. Quitting execution. W DBVH-67 The internal timing arc between the '%s' and '%s' pins is ignored. E DBVH-68 The '%s' output pin has more than 16 pins in the function. E DBVH-69 The state table function fails to transform into an FTGS netlist. E DBVH-70 Test cell related pin '%s' has unknown unateness. E DBVH-71 Cannot handle multiple clocks in a single state. E DBVH-72 Error in the library db file. E DBVH-73 Cannot derive the output state when clear and preset are\n\ \tboth active. W DBVH-74 The cell is in the state table format. Only FTGS and VITAL\n\ \tmodels might be generated. W DBVH-75 The timing check between the '%s' and '%s' pins is ignored. I DBVH-76 A black box TESTSIM model is created for the '%s' cell. I DBVH-77 Black box TESTSIM models are created for all cells that failed. E DBVH-78 A different bus/bundle size is found between\n\ \tbus/bundle ports '%s' and '%s'. E DBVH-79 A RAM cell with more than %d write ports is unsupported. E DBVH-80 The '%s' RAM is edge-triggered and level sensitive.\n\ \tTestSim does not support it. E DBVH-81 Cannot find the '%s' cell in the\t\ \ttestsimmacro.db TestSim library. E DBVH-82 The '%s' RAM contains complex sequential devices in the wrapper network. E DBVH-83 Testsim does not support bundles. The '%s' RAM contains bundle ports. E DBVH-84 An undriven '%s' net is found in the '%s' cell. RAM modeling failed. E DBVH-85 A no fanout '%s' net is found in the '%s' cell. The RAM modeling failed. E DBVH-86 An unconnected '%s' port is found in the '%s' cell.\n\ \tThe RAM modeling failed. I DBVH-87 The worst-case timing arc is used for non-unate inputs. W DBVH-88 The FTBM architecture is obsolete with 1997.01 release.\n\ \tThe architecture is ignored. W DBVH-89 Pin name '%s' on cell '%s' contains underscore characters.\n\ \tThe generated VITAL model will not be VITAL-compliant. E DBVH-90 DCM delay model is used in library '%s'. W DCM-100 Unable to load DCM library for '%s'. \n\ Using the default delay model as specified in the .db library. E DCM-101 Errors found during rule_init() - library '%s' will be unloaded. W DCM-102 No DCM model for cell '%s' of library '%s'. E DCM-103 Unable to load DCM EXPOSE function '%s' from the DCM library. This\n\ \tlibrary cannot be used by this program without the specified EXPOSE function. E DCM-104 The following feature of the DCL language is not (yet) \n\ \tsupported by this program: %s. E DCM-105 Error while processing DCL external function '%s' - passed pin '%s' is\n\ \tnot part of the current timing arc. W DCM-106 The DCL-PI function '%s' returned a nonzero error code %d while\n\ \tprocessing the timing segment '%s'. W DCM-107 Unsupported test type or edge propagation pair '%s' specified for\n\ \tthe arc '%s'. This arc will be ignored. W DCM-108 Internal timing pin '%s' of cell '%s' in library '%s' is\n\ \tnot defined in the corresponding .db library. Any timing arcs connecting to or from\n\ \tthis pin will be ignored. W DCM-109 %s '%s' is invalid. The valid values are '%s' and '%s' W DCM-110 DPCM expose dpcmAddWireLoadModel not supported in DPCL library. Therefore DB/custom wireload models are not supported. W DCM-111 The design %s read in has wireload %s, which is not present in \ the current DPCM. Changing to default DPCM wireload %s. W DCM-112 The design %s read in has a DCPM wireload %s. Deleting the dpcm wireload. F DCSH-1 %s is not enabled. F DCSH-3 System \".synopsys\" not found. Software improperly installed. F DCSH-7 Error in .synopsys file. Cannot continue. F DCSH-9 %s: could not connect to parent '%s'. F DCSH-10 At least one of the following must be enabled : %s. E DCSH-11 Can't read Tcl file %s in your working directory because\n\ \tyou read the default format in home init. W DDB-1 Cell %s not added to design %s because a cell with that name already exists. W DDB-2 Net %s not added to design %s because a net with that name already exists. W DDB-3 Consistency problem: port %s is not owned by any design or reference. W DDB-4 Consistency problem: a pin is not owned by any cell. W DDB-5 Consistency problem: cell %s is not owned by any design. W DDB-7 Consistency problem: net %s is not owned by any design. W DDB-8 Consistency problem: a pin was found without a corresponding port. W DDB-9 Consistency problem: cell %s was found without a corresponding reference. W DDB-10 Consistency problem detected in design %s\n%s W DDB-11 Internal error\n%s W DDB-12 Removed duplicate cell '%s'. W DDB-13 The name of net '%s' in design '%s' can't be changed \n\ \tto the name of both ports '%s' and '%s' to which it's connected. W DDB-14 The net '%s' in design '%s' is connected to both \n\ \tports '%s' and '%s'. E DDB-21 Conflict between logic 0 and 1. Can't %s. E DDB-22 Can't set equal ports opposite in design '%s': '%s' '%s'. E DDB-23 Can't set opposite ports equal in design '%s': '%s' '%s'. W DDB-24 Overwriting design file '%s/%s'. E DDB-27 '%s' value must be positive. E DDB-28 '%s' cannot be set on %s pin '%s'. E DDB-29 '%s' cannot be set on %s port '%s'. E DDB-30 Can't specify output port '%s' as a path startpoint. E DDB-31 Can't specify input port '%s' as a path endpoint. E DDB-32 Can't specify hierarchical cell '%s' as a path '%s'. E DDB-33 Pin '%s' does not have a library hold time. E DDB-34 %s '%s' is in design '%s', but %s '%s' is in design '%s'. E DDB-35 '%s' does not exist in library '%s'. E DDB-38 Can't open security file '%s' for protected library '%s'. E DDB-39 Bad security key in file '%s' for library '%s'. E DDB-40 Can't read protected library '%s'. E DDB-41 Incomplete library protection attributes. W DDB-43 Could not create attribute '%s' for %s objects. E DDB-44 Can't read unprotected library '%s'. E DDB-45 A design with name '%s' already exists in the same\n\ \tdesign file as design '%s'. E DDB-46 A reference with name '%s' already exists in design '%s'. E DDB-47 A cell with name '%s' already exists in design '%s'. W DDB-48 Creating port '%s' on design '%s' with direction unknown. W DDB-51 In the value of %s, \n\ \tthe characters separating the \"%%s\" and \"%%d\" are the same as \n\ \tthose separating each \"%%d\" (may be ambiguous). E DDB-52 The value of %s \n\ \tmust include one \"%%s\" and two \"%%d\". E DDB-53 The value of %s \n\ \tmust include one \"%%s\" and one \"%%d\". E DDB-54 The value of %s \n\ \tmust include only one \"%%s\" and only two \"%%d\". E DDB-55 The value of %s \n\ \tmust include only one \"%%s\" and only one \"%%d\". E DDB-56 In the value of %s, \n\ \tthere are no characters separating %s. E DDB-57 In the value of %s, \n\ \tthe %s of the characters separating \n\ \t%s must not be%s a digit. W DDB-58 In the value of %s, \n\ \tthere are no characters separating the \"%%s\" and \"%%d\" (may \n\ \tbe ambiguous). E DDB-60 Could not find library pin for pin '%s'. W DDB-66 Removing group '%s'. W DDB-67 Removing %s from group '%s'. W DDB-68 Removing external delay related to clock %s. E DDB-70 None of the selected cells were grouped. E DDB-71 Design '%s' requires one of the following licenses: '%s'. I DDB-72 Added key list '%s' to design '%s'. W DDB-73 License '%s' contains the illegal character '%c'.\n\tIt was ignored. W DDB-74 Design '%s' inherited license information from design '%s'. W DDB-75 Design '%s' is being converted to a limited design. E DDB-76 Cannot load design '%s'. E DDB-77 License '%s' is a Synopsys internal key and should\n\ \tnot have a seed associated with it. E DDB-78 No seed provided for the third-party license '%s'. E DDB-79 The license '%s' has an invalid seed associated with it. E DDB-80 The seed '%s' specified for license '%s' is\n\tnot a valid 32-bit integer. W DDB-81 Unable to find specified driving_cell for port '%s'. E DDB-84 Only ports of the same direction can be grouped. E DDB-85 Objects must be either all ports or all nets. E DDB-86 Bus name '%s' conflicts with existing names. E DDB-87 All objects must be from the same design. E DDB-88 At least one of the port objects specified is already a member of a bus. E DDB-89 Type name '%s' conflicts with existing type. E DDB-90 specified range is different from number of objects to be bussed. E DDB-91 only designs or references can have busses created in them. E DDB-92 Cannot load design '%s' for an HDL embedded command. W DDB-95 Unable to find net instance '%s' in design '%s'. W DDB-100 Unable to find minimum version of library cell '%s/%s' in library '%s'. W DDB-101 Unable to find minimum version of library pin '%s/%s' in library '%s'. W DDB-102 Conflicting timing arc descriptions between maximum library '%s' and minimum library '%s' to pin '%s/%s'. W DDB-103 Pin %s of lib cell %s exists in maximum library %s but not in minimum library %s. Assuming min delay for pin to be same as max delay. W DDB-105 Design '%s' requires one of the following licenses: '%s'. \n\tWaiting for license to become available, press -C to terminate. E DDP-1 Bad status %x from '%s' E DDP-2 Can't open map file '%s' W DDP-3 Duplicated symbol '%s' specified E DDP-4 The map file '%s' is corrupted at line '%s' W DDP-5 No symbol to be created E DDP-6 Unable to Write library '%s' E DDP-7 Can't open file '%s' I DDP-8 Scan symbol '%s' E DDP-9 Can't open symbol '%s' under component '%s' for symbol '%s' E DDP-10 Unable to scan symbol '%s' W DDP-11 Find netcon '%s' different from '%s' E DDP-12 More than one bus end on ripper '%s' E DDP-13 Can't find bus end for ripper '%s' W DDP-14 Different user units exist in the symbols E DDP-15 Error in writing symbol '%s' W DDP-16 '%s' does not exist for %s E DDP-17 Unable to traverse design '%s' E DDP-18 Unable to translate symbol '%s' E DDP-19 Error in adding instance symbols for design '%s' E DDP-20 Error in translating schematic of '%s' E DDP-21 Can't load design '%s' E DDP-22 Unrecognized unit '%s' I DDP-23 Create schematic of '%s' W DDP-24 Sheet '%s' of design '%s' does not pass check W DDP-25 Close sheet '%s' of design '%s' failed E DDP-26 Can't open '%s' of schematic '%s' under component '%s' E DDP-27 Can't instantiate symbol '%s' of component '%s' E DDP-28 Can't find symbol '%s' E DDP-29 Global net '%s' is not recognized I DDP-30 Symbol '%s' of type '%s' is ignored I DDP-31 Create symbol of '%s' E DDP-32 Can't create symbol '%s' under component '%s' E DDP-33 Ripper symbol '%s' does not have a 'bundle' pin E DDP-34 Can't find pin name W DDP-35 Symbol'%s' does not pass check W DDP-36 Close symbol of '%s' failed W DDP-37 Can't find instance '%s' W DDP-38 Can't find pin '%s' of instance '%s' W DDP-39 Can't find symbol for library cell '%s' W DDP-40 Symbol library '%s' has symbols with off-grid pins. Recreate \nlibrary with a v2.2b or later version of dc_shell or design analyzer. E DDP-41 %s have different route grids W DDP-42 Designs without schematics: %s\n\t%s E DDP-43 Can't read the file '%s' E DDP-44 '%s' is not a %s library file E DDP-45 Error in translating symbols from library '%s' W DDP-46 Can't add property '%s' E DDP-47 Can't find design '%s' in file '%s' E DDP-48 Can't find symbol for instance '%s' of design '%s' I DDP-49 The content of the additional sheet '%s' in design '%s' is removed E DDX-1 In design '%s', connection to %s is too wide. E DDX-2 In design '%s', connection to %s is too narrow. W DDX-3 In design '%s', port '%s' is not an array.\n\t"multiple_port" attribute ignored. E DEFIN-1 Failed to read file '%s'. W DEFIN-2 Ignore '%s' at line %d. W DEFIN-3 Extract the pin location from this section, assuming pin name is matching netlist port name. W DEFIN-4 Probably the DIEAREA statement has unexpected syntax. W DEFIN-5 Probably inside the COMPONENTS section, the plus statement is incorrect. E DEFIN-6 Failed to read file '%s' because of missing PINS section. E DEFIN-7 Require to read pdb which contains macro class definition to tell which components are PAD, so the program can take that as port location. W DEFIN-8 Can not find macro type for this component '%s'. E DEFIN-9 Only support 5.1 version. Ignore the Site statement at line %d. E DEFIN-10 The program requires reading pdb. W DEFIN-11 Pin '%s' does not have location. W DEFIN-12 Only extract the first rectangle as boundary at line '%d'. W DEFIN-13 Only support regions in GROUPS at line '%d'. W DEFIN-14 Only support regular expressions '*','%','-' in GROUPS E DEFIN-15 This layer %s is not defined in the library. The PDEF\ file will be incorrect. W DEFIN-16 Detect %s near toke '%s' at line %d.\ Continue to parse until the next correct rule can be applied. W DEFIN-17 Probably the UNITS statement has incorrect syntax. W DEFIN-18 Probably the ROW statement has incorrect syntax. W DEFIN-19 Probably inside the SPECIALNETS section, the plus statement is incorrect. W DEFIN-20 Probably the special wiring continue point has incorrect syntax. W DEFIN-21 Probably the special wiring section has incorrect syntax. W DEFIN-22 Probably the new special wiring statment has incorrect syntax. W DEFIN-23 Probably the regular wiring section has incorrect syntax. W DEFIN-24 Probably the new regular wiring statment has incorrect syntax. W DEFIN-25 Probably inside the PINS section, the plus statement is incorrect. W DEFIN-26 Probably inside the REGIONS section, the plus statement is incorrect. W DEFIN-27 Probably inside the GROUPS section, the plus statement is incorrect. E DEL-001 You cannot mix an LCD operating conditon with a \ non LCD operating condition. E DEL-002 You cannot specify a single LCD operating conditon. W DEL-003 Library '%s' has time unit of %gns\nbut the main library unit is %gns W DEL-004 Library '%s' has capacitive_load unit of %gpF\nbut the main library unit is %gpF E DES-001 Current design is not defined. E DES-002 Cannot find %s '%s' in design '%s' E DES-003 '%s' cannot be set on %s port '%s'. E DES-004 Cannot find design '%s'. E DES-005 Cannot set current instance to leaf cell '%s'. E DES-006 Cannot find pin '%s' on cell '%s'. W DES-007 '%s' is not a valid object type. E DES-008 Cannot find %s '%s' in library '%s'. E DES-009 Cannot find pin '%s' on library cell '%s'. E DES-010 Cannot find %s '%s'. E DES-011 Cell '%s' is not hierarchical. E DES-012 Cannot use '%s' command on %s '%s'. E DES-013 Current design is not in min-max mode. E DES-014 Object '%s' is not in the current design. E DES-015 Cannot use '%s' command on %s '%s'\n\ \tbecause it is a limited design. E DES-016 Cannot use '%s' command on %s '%s'\n\ \tbecause it contains instances of limited designs%s. I DES-017 Could not auto-link design '%s'. E DES-018 There is already an operating condition named '%s' in library '%s'. W DES-019 library '%s' has been generated with an old version\n\ \tof the Library Compiler. It needs to be rebuilt to support case\n\ \tanalysis on sequential cells. W DES-020 No operating condition is specified, assuming a voltage value of %s volts for RC delay calculation. W DES-021 These environment variables need to be set for accurate RC delay\n calculation:\n\ Variable name Default\n\ -------------------------------------------\n\ rc_slew_lower_threshold_pct_rise 20\n\ rc_slew_lower_threshold_pct_fall 20\n\ rc_slew_upper_threshold_pct_rise 80\n\ rc_slew_upper_threshold_pct_fall 80\n\ rc_input_threshold_pct_rise 50\n\ rc_input_threshold_pct_fall 50\n\ rc_output_threshold_pct_rise 50\n\ rc_output_threshold_pct_fall 50 W DES-022 These environment variables have an incorrect value below 1.0.\n\ The range for these variables is between 0 and 100. Default values are used.\n\ Please set correct values.\n\ Variable name Default\n\ -------------------------------------------\n\ rc_slew_lower_threshold_pct_rise 20\n\ rc_slew_lower_threshold_pct_fall 20\n\ rc_slew_upper_threshold_pct_rise 80\n\ rc_slew_upper_threshold_pct_fall 80\n\ rc_input_threshold_pct_rise 50\n\ rc_input_threshold_pct_rise 50\n\ rc_output_threshold_pct_rise 50\n\ rc_output_threshold_pct_rise 50\n W DES-023 Net '%s' is multi-driven.\n RC calculation cannot be performed. Using lumped capacitance. W DES-024 Net '%s' has an incomplete RC network. E DES-025 Pin '%s' is not connected to\n net '%s'.\n Ignoring annotation on net '%s'. E DES-026 %s pin '%s' is not connected to RC\n network of net '%s'\n RC network on that net is incomplete, so it is ignored. W DES-027 net '%s' has too many (%d) RC elements.\n Lumped capacitance is used. I DES-028 Derived library resitance unit is %.3f Kohm (Time unit is %.3f ns, and Capacitance unit is %.3f pF). E DES-029 Library '%s' has no voltage rails defined. E DES-030 cannot find rail voltage '%s' in library '%s'. E DES-031 Variables rc_slew_lower_threshold_pct_* and rc_slew_upper_threshold_pct_* cannot have the same value. E DFI-1 Could not open viewpoint '%s' E DFI-2 Error in traversing design viewpoint '%s' E DFI-3 Could not find referenced design for instance '%s' E DFI-4 Could not add design '%s' E DFI-5 Could not add port '%s' for design '%s' E DFI-6 Could not add instance '%s' for design '%s' W DFI-7 Design '%s' contains no instance W DFI-8 Both '%s' and '%s' has the same design name '%s' W DFI-9 Design in path '%s' is renamed to '%s' W DFI-10 Property '%s' is not visible, port will have unknown direction W DFI-11 Property '%s' for '%s' is not visible E DFI-12 Can't connect pin '%s' of instance '%s' E DFI-13 Could not find referenced design '%s' E DFI-14 Bus '%s' contains ports of different types E DFI-15 Can't add bus '%s' E DFI-16 Can't write '%s' db file E DFI-17 Port '%s' is missing in the interface of design '%s' E DFI-18 Can't connect '%s' to '%s' net W DFI-19 Could not add bus port '%s' for design '%s' because %s W DTC-1 The scaling factor given for %s is invalid. Using default value of 1.0. W DTC-2 Unable to create clock on pin '%s' (%s). E DWSC-2 Port number %d of implementation '%s' of\n\ \tsynthetic module '%s' should be '%s'. E DWSC-3 Direction of port '%s' in implementation '%s'\n\ \tdoes not match the declared synthetic module '%s'. E DWSC-4 Width of port '%s' in implementation '%s'\n\ \tdoes not match the declared synthetic module '%s'. E DWSC-5 Port '%s' in implementation '%s'\n\ \t is not declared in the synthetic module '%s'. W DWSC-6 The dont_touch on the synthetic library implementation\n\ \t'%s' (module '%s') will be ignored during model generation. E DWSC-7 Design hierarchy is not allowed inside a\n \ \tsynthetic library part. The module '%s' implementation '%s'\n\ has hierarchy in it. E DWSC-8 The synthetic library module '%s'\n\ \timplementation '%s' failed to link. I DWSC-9 Modeled %s(%s).\n\ \t(Wire load = %s Operating Conditions = %s) I DWSC-10 The synthetic model '%s' was read from a cache. I DWSC-11 Read %s as a cache element. I DWSC-12 The cache entry '%s'\n\ \tis out of date with respect to the information\n\ \tin the design library or the generator '%s'\n\ \t(module '%s', implementation '%s').\n\ \tThe cache entry has been removed. W DWSC-13 The cache entry '%s'\n\ \tshould be removed, but the attempt to remove it has failed.\n\ \tThe entry is either out of date or corrupted with respect to its entry\n\ \tin the design library or the generator '%s'\n\ \t(module '%s', implementation '%s'). I DWSC-14 The cache entry '%s'\n\ \tis out of date with respect to its target library '%s'.\n\ \tThe cache entry has been removed. W DWSC-15 The cache entry '%s'\n\ \tshould be removed, but the attempt to remove it has failed.\n\ \tThe entry should be removed because either it is corrupted\n\ \tor it is out of date due to newer target library '%s'. I DWSC-16 The v3.3b cache element format has changed. \n\ \tThe cache entry, '%s', is being removed.\n W DWSC-17 The cache entry '%s'\n\ \tshould be removed, but the attempt to remove it has failed.\n\ \tThe entry should be removed because it is written in the older format, v3.3b. I DWSC-18 The cache entry '%s'\n\ \thas been corrupted, so it is being removed. W DWSC-19 The cache entry '%s'\n\ \tshould be removed, but the attempt to remove it has failed.\n\ \tThe entry should be removed because it is either corrupted or obsolete. W DWSC-20 Improper octal value for variable cache_file_chmod_octal or cache_dir_chmod_octal: %s W DWSC-21 Cannot set protections on the cache directory %s. I DWSC-22 Wrote %s as cache element. W DWSC-23 Cannot set protections on the cache file %s. W DWSC-24 Cache element %s could not be written. E DWSC-25 Unable to resolve environment variable %s for generator %s. I DWSC-26 User interrupted execution of generator. E DWSC-27 Synthetic library '%s'\n\ \tis from an incompatible version of the software. W DWSC-28 Inout port type on port %s is currently not supported. W DWSC-29 Unknown input oper_pin '%s' specified as permutable. W DWSC-30 Input oper_pin '%s' multiply specified as permutable. E DWSC-31 Unable to find the generator at '%s'. E DWSC-32 %s. E DWSC-33 Parameter '%s' does not evaluate to a numeric value %s. I DWSC-34 The cache entry '%s'\n\ \tis out of date with respect to the information\n\ \tin the synthethic library '%s'\n\ \t(module '%s', implementation '%s').\n\ \tThe cache entry has been removed. W DWSC-35 The cache entry '%s'\n\ \tshould be removed, but the attempt to remove it has failed.\n\ \tThe entry is either out of date or corrupted with respect to its entry\n\ \tin the synthetic library '%s'\n\ \t(module '%s', implementation '%s'). W DWSC-36 Could not find port '%s' in implementation %s\n\ \tof synthetic module '%s'. E DWSI-1 Parameter '%s' does not evaluate to a positive value\n\t%s. I DWSI-2 Re-generating implementation '%s' for '%s' with timing context. E ECO-1 The subdesign '%s' has %d %s cells. E ECO-2 Current design pair is not defined. E ECO-3 Cannot set a design in current design pair to library design '%s'. E ECO-4 Some black box cells cannot be handled \n\ \tin design '%s'. E ECO-5 The current design pair is inappropriate for the command. E ECO-6 Design %s is a limited design and can not be processed by ECO Compiler. E ECO-7 Do not use on cell '%s' attributes eco_spare and eco_obsolete\n\ \ttogether with set_eco_unique, set_eco_align, and set_eco_reuse. I ECO-8 In design '%s' cell '%s' has unique name to avoid collision. E ECO-9 Exactly one target must be specified to set_eco_target. E ECO-10 Missing library cell '%s' for cell '%s' in '%s'.\n\ \tMake sure the dont_use attribute is not on target_library cell. I ECO-11 The verification limit was reached for some ECO endpoints: E ECO-12 The designs of the current design pair have incongruent hierarchies. W ECO-14 The library cells of cell %s and %s have the same names\ but have different functionality. W ECO-15 Specifying high effort level for the eco_implement\n\ command may lead to excessive run-times. I ECO-16 If you would like eco_implement to work harder on\n\ these endpoints, try setting the eco_implement_effort_level\n\ variable to 'high'. I ECO-17 Uniquifying design %s in order to change the reference design of cell %s/%s. E ECO-18 Identical DB reference '%s' for the instances\n\ \t'%s' and '%s'. E ECO-19 The following DesignWare designs are instantiated in\n\ \tboth hierarchies. E ECO-20 The following DesignWare designs are instantiated more\n\ \tthan once in the %s. E ECO-21 Do not apply both set_eco_align and %s attribute on cell '%s'. E ECO-22 Design '%s' has '%d' black boxes but \n\ \tdesign '%s' has '%d' black boxes. E ECO-23 cell '%s''%s' is a unalignable black box. W ECO-24 The following hierarchical cells of the old netlist have the same \n\ \tDB reference as some cells in the new netlist due to the set_eco_reuse \n\ \tcommand. This can cause inaccuracies in the output. E ECO-25 set_eco_reuse applies only to netlist design pair. I ECO-26 Ignoring eco_spare attribute on hierarchical cell %s\n\ \tof %s:%s E ECO-40 Remapping of registers failed. W ECO-41 Some registers in old implementation could not be re-mapped: I ECO-42 Some new register types were used to remap some old registers: I ECO-43 Continuing with some non-pin-compatible registers. I ECO-44 Some old register types were used to remap some new registers: W ECO-45 Some registers in new implementation could not be re-mapped: I ECO-46 Because, the reference type associated with the corresponding\n\ aligned register in the %s implementation is not present in the\n\ target library. I ECO-70 Accepting logic in the transitive fan-in of object\n\ \t'%s' in design '%s'. E ECO-71 Can't set eco_accept_endpoint directive on unique object '%s'. E ECO-72 Can't set object '%s' unique because it has the eco_accept_endpoint directive. W ECO-73 Ignoring eco_accept_endpoint directive on %s %s. I ECO-74 Because, parent DesignWare cell has the set_eco_reuse directive. I ECO-75 Because, pin '%s' in level hierarchy '%s' can not be found. I ECO-76 Because, endpoint is not aligned. I ECO-77 Because, the eco_accept_endpoint directive is also applied to the corresponding aligned endpoint "%s" in the new netlist. I ECO-78 Because the following startpoints in the support of end-point "%s" in the old netlist are not aligned with any startpoints in the support of endpoint "%s" in the new netlist. I ECO-79 The following start-points in the support of end-point "%s" in the new netlist are not aligned with any start-points in the support of frozen end-point "%s" in the old netlist. E ECO-82 Error encountered during unique directives processing. E ECO-83 Complete alignment of all ports and registers not satisfied. I ECO-84 %s objects '%s' and '%s' in designs\n\ \t'%s' and\n\ \t'%s'. I ECO-85 Object '%s' will be considered unique in design \n\ \t'%s'. I ECO-86 Performing %s on object '%s'. I ECO-87 No DB reference designs for cells:\n\ \t'%s' and\n\ \t'%s'. E ECO-88 No DB reference design for %s cell '%s'. E ECO-89 set_eco_reuse cannot change link of unresolved reference. E ECO-90 Must align DesignWare cell '%s' before aligning its pins. E ECO-91 The design cells are from different libraries. E ECO-92 One cell is Designware and the other is not. E ECO-93 Some pins on cell '%s' are not alignable by name on cell '%s': W ECO-94 Combinational feedback loops found in design\n\ \t'%s'. E ECO-95 Alignment not complete. Must use eco_align_design command. W ECO-96 ECO target '%s' not found in design instance\n\ \t'%s'. W ECO-97 ECO tap '%s' not found in design\n\ \t'%s'. I ECO-98 Boundary optimization prevents identical endpoints computation in\n\ \t'%s'. I ECO-99 Changing ECO subdesign instance name from %s to %s. E ECO-100 -struct, -functional, -big_fish and -reusable\ \tflags are exclusive. E ECO-101 Four designs expected as arguments. E ECO-102 Design '%s' is specified twice in the argument list. E ECO-103 Two or zero designs expected as an argument. E ECO-104 Can't specify -all along with designs. E ECO-105 No directives has been specified. No script\n\ \twritten. E ECO-106 Hierarchical names are not allowed: '%s' E ECO-107 Parent design for object '%s' not found.\n\ \tPlease report this message to Synopsys immediately. E ECO-108 Parent designs '%s' and '%s' of the specified\ \tobjects have the same DB references. E ECO-109 Objects '%s' and '%s'\n\ \thave the same DB reference, corresponding designs %s are:\n\ \t'%s' and '%s'. Please notify Synopsys. E ECO-110 Ports/pins '%s' and '%s' have\n\ \tdifferent direction types. E ECO-111 Ports/pins are not of the required type. E ECO-112 Number of input/outputs are different for the\n\ \tspecified objects. E ECO-113 '%s' is an invalid category. It must be\n\ \teither 'first' or 'second'. E ECO-114 Object '%s' not found in the design\n\ \tof eco pair. E ECO-115 Port '%s' is not an input port. E ECO-116 Pin '%s' is not an output pin of a cell. E ECO-117 Object '%s' is not a pin or a port. W ECO-118 Discarding set_eco_target command not pertaining to old netlist,\n\ \tbut to design '%s'. E ECO-119 The two designs have the same DB reference. E ECO-120 In the %s hierarchy, object '%s' could not be found in design\n\ \t'%s'. E ECO-121 Attribute not set on any object. E ECO-122 No tap points were specified to set_eco_target. W ECO-200 The design '%s' is hierarchical;\n\ \tno sharing of cells among different levels of hierarchy possible. W ECO-201 The design '%s' has no physical information (pdef) available. E ECO-202 Cannot use respect_physical_hier or respect_distance\n\ \twithout annotated pdef information. E ECO-203 Cannot find library cell of cell %s in the target library. W ECO-204 No location information for cell %s available. E ECO-205 Current_design has not been set. E ECO-206 Cell %s is not a valid resource cell. E ECO-207 Missing distance value to option respect_distance. E ECO-208 Resource cell %s is driving a non-resource cell. E ECO-220 The given directive will be ignored because it already is specified. E ECO-221 The specified directive cannot be removed because it is not in\ the set of already stored directives. E ECO-222 The specified directive cannot be applied because the cell %s \ is not found in the current design. E ECO-223 The recycle directive for cell %s and cell %s cannot be applied\ because the cells are in different categories. E ECO-224 The specified cell %s is not a resource cell. E ECO-225 The specified cell %s is not a new cell. E ECO-226 The specified cell %s is not an old or a recycled cell. W ECO-227 The \fBset_eco_obsolete\fP doesn't provide a new name. A new name will be automatically generated. W ECO-228 The specified new name %s is not unique in the design. W ECO-229 Skipping directive because specified resource cell %s is already used. W ECO-230 Skipping directive because the specified new cell %s is already mapped. E ECO-231 The directive couldn't be applied because the new cell %s\ and the resource cell %s are not in the same level of the hierarchy W ECO-232 The new cell %s couldn't be mapped to the resource cell %s because \ it has more inputs than the resource cell. E ECO-233 The directive couldn't be applied because the directive\ specified multiple output gates. W ECO-234 The new cell %s couldn't be mapped to the resource cell %s \ because there are not enough inverters available. E ECO-235 Force mapping of the resource cell %s to the new cell %s\ is impossible. W ECO-236 The specified new cell %s could not be found. W ECO-237 The specified new cell %s is not a new cell. W ECO-238 The specified resource cell %s could not be found. W ECO-239 The specified resource cell %s is not a resource cell. E ECO-240 The specified cell %s is not a reused cell. E ECO-241 The specified new name %s is already used. E ECO-242 The set_eco_obsolete command requires a cell name as an option E ECO-243 The set_eco_recycle command requires as arguments\ the name of a new cell as well as the name of a resource cell. W ECO-300 Removing dont_touch attribute from design '%s'. W EDFN-1 Line %d: A port is declared without a name. Using "DUMMY_NAME_xx". E EDFN-2 Line %d: Too few elements in %s form. E EDFN-3 Line %d: Incorrect number of elements in %s form. E EDFN-4 Line %d: Expected a list. W EDFN-5 Line %d: Unknown function is being ignored. E EDFN-6 Line %d: Expected a parenthesis. E EDFN-7 Line %d: Expected a non-empty list. W EDFN-8 Line %d: Multiple views not supported. View '%s' of cell '%s' ignored. E EDFN-9 Line %d: Can not add the design to the root. E EDFN-10 Line %d: Instance specified without cell ref in view ref. E EDFN-11 Line %d: Can not find the design %s of the cell. E EDFN-12 Line %d: Cannot add the cell reference to the design. E EDFN-13 Line %d: Cell ref specified that is not defined in this file. W EDFN-14 Line %d: Duplicate instance '%s' renamed as '%s' in design '%s'. E EDFN-15 Line %d: Can not add the instance to the design. E EDFN-16 Line %d: Cannot build the array specification. E EDFN-17 Line %d: Cannot build the symbol specification. E EDFN-18 Line %d: Cannot add the nets. E EDFN-19 Line %d: Cannot add the net. E EDFN-20 Line %d: Cannot add the net to the design. E EDFN-21 Line %d: Cannot connect the object to the net. E EDFN-22 Line %d: Port or instance reference count exceeds net array size. E EDFN-23 Line %d: Port is not an array member. E EDFN-24 Line %d: Port reference %s count of %d exceeds net size. W EDFN-25 Line %d: The net %s is not an array. E EDFN-26 Line %d: Instance is not an array member. E EDFN-27 Line %d: Instance reference count exceeds net array size. E EDFN-28 Line %d: Nets cannot be connected to an array of ports on an array of instances. E EDFN-29 Line %d: Can not find the pin on the cell. E EDFN-30 Line %d: Port (on instance) reference count exceeds net array size. E EDFN-31 Line %d: Net array size exceeds port reference count. E EDFN-32 Line %d: Can not add the port. E EDFN-33 Line %d: unrecognized keyword: %s. E EDFN-34 Line %d: Can not add the port to the design. E EDFN-35 Line %d: Cannot add the power or ground cell to the design. E EDFN-36 Line %d: Cannot add the power or ground net to the design. E EDFN-37 Line %d: Cannot add the array. E EDFN-38 Line %d: Index array value exceeds bounding array value. E EDFN-39 Line %d: multiple definition of %s '%s' in %s '%s', or there is a missing construct prior to the specified EDIF construct. W EDFN-40 Line %d: Ending %s name space with %s name space (mismatch). E EDFN-41 Line %d: Cannot find %s '%s' in definition of %s '%s'. E EDFN-42 Line %d: The %s reference has a missing or invalid name. E EDFN-43 Line %d: The %s reference has a missing or invalid %s reference. E EDFN-44 Line %d: Cannot find the current %s symbol specification. E EDFN-45 Line %d: Value of %s:%s not successfully interpreted. E EDFN-46 Line %d: unmatched right parenthesis. E EDFN-47 Line %d: missing left parenthesis. E EDFN-48 Line %d: misplaced '%%'. E EDFN-49 Line %d: unrecognized token. E EDFN-50 Line %d: missing right parenthesis. E EDFN-51 Line %d: No edif design encountered. E EDFN-52 Line %d: ASCII character is not between 0 and 127. E EDFN-53 Line %d: invalid string token. E EDFN-54 Line %d: Expected an arc or point. E EDFN-55 Line %d: Expected a rectangle. E EDFN-56 Line %d: Expected a curve. E EDFN-57 Line %d: Expected a point. E EDFN-58 Line %d: Expected a number. E EDFN-59 Line %d: Expected a name. E EDFN-60 Could not open file '%s'. W EDFN-61 Line %d: Edifin_lib_%s_symbol '%s' not found in library '%s'. E EDFN-62 Line %d: 'DISTANCE' scale not defined for library '%s'. I EDFN-63 Line %d: Could not find port connect location. Using derived connect \ location from '%s' viewRef, '%s' cellRef, or '%s' libraryRef. E EDFN-64 Line %d: Connect location derived for '%s' viewRef of '%s' cellRef of '%s' libraryRef is not equal to previously derived location. W EDFN-65 Line %d: No connect location found for '%s' viewRef, '%s' cellRef,\ or '%s' libraryRef. W EDFN-66 Line %d: Derived connect location rejected for '%s' viewRef, '%s' cellRef,\ and '%s' libraryRef. E EDFN-67 Line %d: The %s element within the '%s' construct must be %s. E EDFN-68 Line %d: The keywordAlias construct is only valid in \ keywordLevel 1 or higher. E EDFN-69 Line %d: Expected an identifier. W EDFN-70 Could not find template symbol '%s' for sheet\ size '%s' or orientation '%s' in library '%s'. E EDFN-71 Line %d: The points defining the arc are not distinct. E EDFN-72 Line %d: Can not create attribute '%s' on the cell instance. E EDFN-73 Line %d: Can not set attribute '%s' on the cell instance. E EDFN-74 Line %d: There is no pin named '%s' on the cell instance. E EDFN-75 Line %d: Can not create attribute '%s' on pin '%s'. E EDFN-76 Line %d: Can not set attribute '%s' on pin '%s'. E EDFN-77 Line %d: Can not create attribute '%s' on port '%s'. E EDFN-78 Line %d: Can not set attribute '%s' on port '%s'. E EDFN-79 Line %d: The attribute 'disabled' may not be set on power or ground port '%s'. E EDFN-80 Line %d: Duplicate view property name in library '%s'.\n\ View '%s' of cell '%s' has the same view\n\ identifier '%s' property value of '%s' as\n\ view '%s' of cell '%s'. E EDFN-81 Line %d: Duplicate design name in library '%s'.\n\ View '%s' of cell '%s' already has a view\n\ identifier '%s' property value of '%s'. E EDFN-82 The value of variable '%s' isn't valid. E EDFN-83 Line %d: The range from %d to %d of array '%s' does not match its width. E EDFN-84 Line %d: Multiple cells of the same name are not supported. W EDFN-85 Line %d: Cannot create attribute '%s' on net '%s'. W EDFN-86 Line %d: Cannot set attribute '%s' on net '%s'. W EDFN-87 Line %d: Cannot create attribute '%s' on design '%s'. W EDFN-88 Line %d: Cannot set attribute '%s' on design '%s'. E EDFN-89 Line %d: Library '%s' is corrupted.\ Not all view identifier properties of cell '%s' are found. E EDFN-90 Line %d: The port '%s' on instance '%s' isn't an array. W EDFN-91 Line %d: The value '%s' of the duplicate %s\ property '%s' is ignored. W EDFN-92 Line %d: Cannot create attribute '%s' on the cell instance. W EDFN-93 Line %d: Cannot set attribute '%s' on the cell instance. W EDFN-94 Line %d: Cannot create attribute '%s' on pin '%s'. W EDFN-95 Line %d: Cannot set attribute '%s' on pin '%s'. W EDFN-96 Line %d: Cannot create attribute '%s' on port '%s'. W EDFN-97 Line %d: Cannot set attribute '%s' on port '%s'. W EDFN-98 Line %d: Net bus not added to the design because a\ %s by that name has been added previously (adding this\ net's connections to the previously added net). W EDFN-99 Line %d: Port array connected to a net that is not an \ array. W EDFN-100 Line %d: Port (on instance) array connected to a net that is not an array. E EDFN-101 Line %d: The portBundle is not supported. I EDFN-102 Line %d: Defining view '%s' of cell '%s'\ to be the bus ripper. I EDFN-103 Line %d: Defining view '%s' of cell '%s'\ to be the bus ripper. W EDFN-104 Line %d: \n\ \tNo symbol created for cell '%s' \n\ \tbecause the view that has been defined to be the \n\ \tcorrect view of the bus ripper cell (by setting \n\ \tthe variable edifin_lib_ripper_view_name) was not \n\ \tfound. \n\ \t E EDFN-105 Line %d: invalid identifier token. E EDFN-106 Line %d: invalid integer token. W EDFN-107 Line %d: Expected an identifier. W EDFN-108 Line %d: Expected a nameDef. W EDFN-109 Line %d: Expected a nameRef. W EDFN-110 Line %d: No connect location recognized. W EDFN-111 Line %d: Multiple connect location ignored. W EDFN-112 Line %d: Ignoring explicit bus declaration\ because the variable 'bus_inference_style' is set; individual\ port members will be added instead. Port busses will be\ inferred after all design objects are read. W EDFN-113 Line %d: Duplicate base name '%s' for %s bus. Using '%s' for base name instead. E EDFN-114 File %s,\n\ Line %d and\n\ File %s, \n\ Line %d: %s '%s' and %s '%s' both are changed to '%s' in '%s'. E EDFN-115 port '%s' and port '%s' both are changed to '%s' in cell '%s' according to your names file. I EDFN-116 Line %d: On cell '%s', defining view '%s'\ to be the bus ripper. I EDFN-117 Line %d: On cell '%s', defining view '%s' \ to be the bus ripper. W EDFN-118 Line %d: Base name and range extraction are\ not supported for multidimensional %s array '%s'. W EDFN-119 Line %d: Ignoring the ripper cell attributes specified\ here for cell '%s'; the attributes have already been included on cell '%s'. W EDFN-120 Line %d: \n\ \tNo symbol created for cell '%s' \n\ \tbecause the view that has been defined to be the \n\ \tcorrect view of the bus ripper cell (by setting \n\ \tthe variable edifin_lib_ripper_view_name) was not \n\ \tfound. \n\ \t W EDFN-121 Line %d: \n\ \tNo symbol created for cell '%s' \n\ \tbecause the view that has been defined to be the \n\ \tcorrect view of the bus ripper cell (by setting \n\ \tthe variable edifin_lib_ripper_view_name) was not \n\ \tfound. \n\ \t I EDFN-122 Line %d:\ On cell '%s', defining view '%s' to be the bus ripper. I EDFN-123 Line %d: On cell '%s', defining view '%s'\ to be the bus ripper. E EDFN-124 Line %d: \n\ \tA connection to a pin on a member of an array of ripper cell \n\ \tinstances is not supported. \n\ \t E EDFN-125 Line %d: A portRef member construct referencing a port that is not an array is not valid. E EDFN-126 Line %d: The ripper cell instance is corrupt. W EDFN-127 Line %d: \n\ \tConnections to a ripper with more than two pins are not supported. \n\ \t E EDFN-128 Line %d: \ \tA ripper with pins of different widths is not valid.\n E EDFN-129 Line %d: An array member index less than 0 is not valid. E EDFN-130 Line %d: The array member index is greater than the size of the referenced array. E EDFN-131 Line %d: A ripper with a multi-dimensional port array is not supported. E EDFN-132 Line %d: \n\ \tThe dimension of the %sRef member construct does not match \n\ \tthe dimension of the %s array being referenced. \n\ \t E EDFN-133 Line %d: The ripper cell is corrupt. W EDFO-1 Some designs have no schematic. E EDFO-2 The meter scales in libraries '%s' and '%s' aren't equal. E EDFO-3 The meter scale in library '%s' and external scale in library '%s' aren't equal. E EDFO-4 The external scales in libraries '%s' and '%s' aren't equal. E EDFO-5 The external scale in library '%s' and meter scale in library '%s' aren't equal. W EDFO-6 No meter scale found for symbol libraries--using external scale. W EDFO-7 No meter scale or external scale found for symbol libraries. E EDFO-8 %s '%s' has no symbol. E EDFO-9 A pin on cell '%s' has no port reference. I EDFO-10 Net '%s' is renamed to '%s' in design '%s' because it's connected to the port by that name. W EDFO-11 Net '%s' is renamed to '%s' in design '%s' because it's not connected to the port by that name. E EDFO-12 There's %s in %s '%s' that has no name. E EDFO-13 The value of variable '%s' isn't valid. W EDFO-14 The variable 'edifout_power_and_ground_representation'\ is not defined using 'cell'. E EDFO-15 The symbols '%s' and '%s' are both used as %s symbols. E EDFO-16 The schematic '%s' was created %s the "-no_bus" option, \n\ \tbut the schematic '%s' was created %s the "-no_bus" option. E EDFO-17 The width of bussed port '%s' in design '%s' can't be resolved. E EDFO-18 The library of cell '%s' is corrupted.\n\ \tNot all view identifier properties of the cell are found. W EDFO-19 The library of cell '%s' is corrupted.\n\ \tNot all view identifier properties of the cell are found. W EDFO-20 Change '%s' of type %s to '%s' to match vhdl name. E EDFO-21 A bussed off-sheet connector of width %d and an off-sheet \n\ \tconnector are both named '%s'. E EDFO-22 Two bussed off-sheet connectors of width %d and of width %d \n\ \tare both named '%s'. E EDFO-23 One of the pins or ports in %s '%s' is corrupted. E EDFO-24 Port reference '%s' on cell '%s' has no design reference. E EDFO-25 There's no port for port reference '%s' on design '%s'. E EDFO-26 One of the nets in schematic '%s' is corrupted. E EDFO-27 The schematic '%s' is corrupted. E EDFO-28 The schematic '%s' was created with the "-bit_mappers" option. E EDFO-29 The schematic '%s' was created with the "-implicit" option. E EDFO-30 The symbol for '%s' is corrupted. I EDFO-31 Schematic '%s' might have been modified due to netcon insertion. E EDFO-32 The cell for '%s' is corrupted. E EDFO-33 The special symbols in the schematic '%s' are not the \n\ \tsame as the special symbols in the schematic '%s'. E EDFO-34 Library '%s' has no symbols. E EDFO-35 The library '%s' is corrupted. E EDFO-36 The schematic '%s' was created with the "-no_rip" option. W EDFO-37 The variable '%s' is obsolete. E EDFO-38 The values of variables '%s' \n\ \tand '%s' aren't compatible. E EDFO-39 The values of variables '%s' \n\ \tand '%s' aren't compatible. W EDFO-40 Bussed port '%s' in design '%s' \ cannot be represented as a multidimension array. E EDFO-41 One of the bussed pins or ports in design '%s' \n\ \tcan't be represented as a numerical array. E EDFO-42 The power or ground reference is corrupted. E EDFO-43 Specified to write the power cell in the external \n\ \tlibrary that actually contains the ground cell and to write the \n\ \tground cell in the external library that actually contains the \n\ \tpower cell. This is not supported. E EDFO-44 %s '%s' in %s '%s' is corrupted. I EDFO-45 The design '%s' \n\ \tuses the logic %s reference '%s' \n\ \tin the library '%s'. W EDFO-46 The design '%s' uses the built-in Synopsys logic %s reference. W EDFO-47 File %s, line %d: '%s' '%s' cannot change to existing '%s' '%s'. E ELAB-1 Generic error: %s W ELAB-3 Extraneous argument for system function/task %s ignored. W ELAB-4 Other simulators require that function call %s not have parenthesis without parameters. W ELAB-21 Intraassignment delays for blocking assignments are ignored. W ELAB-22 Intraassignment delays for non-blocking assignments are ignored. E ELAB-23 Intraassignment events for blocking assignments are ignored. E ELAB-24 Intraassignment events for non-blocking assignments are not currently supported. W ELAB-25 Intraassignment repeat event controls for blocking assignments are ignored. W ELAB-26 Intraassignment repeat event controls for non-blocking assignment are ignored. W ELAB-28 SCALARED keywords are ignored. W ELAB-29 VECTORED keywords are ignored. W ELAB-32 DELAY specification for gate instantiation is ignored. W ELAB-33 DELAY specification for tri-state gate instantiation is ignored. W ELAB-34 DELAY specification for mos switch instantiation is ignored. W ELAB-35 DELAY specification for cmos switch instantiation is ignored. W ELAB-36 DELAY specification for bi-directional switch instantiation is ignored. W ELAB-37 DELAY specification for pull gate instantiation is ignored. W ELAB-38 DELAY specification for net declaration is ignored. W ELAB-39 STRENGTH specification for net declaration is ignored. W ELAB-40 DRIVE STRENGTH specification for gate instantiation is ignored. W ELAB-41 DRIVE STRENGTH specification for tri-state gate instantiation is ignored. W ELAB-42 DRIVE STRENGTH specification for pull gate instantiation is ignored. W ELAB-43 DRIVE STRENGTH specification for module instantiation is ignored. W ELAB-44 DRIVE STRENGTH specification for continuous assignment is ignored. W ELAB-45 REAL declarations are not supported by synthesis. W ELAB-46 REALTIME declarations are not supported by synthesis. W ELAB-47 TRIAND declarations are not supported by synthesis. W ELAB-48 TRIOR declarations are not supported by synthesis. W ELAB-49 TRI0 declarations are not supported by synthesis. W ELAB-50 TRI1 declarations are not supported by synthesis. W ELAB-51 TRIREG declarations are not supported by synthesis. W ELAB-52 PULLDOWN declarations are not supported by synthesis. W ELAB-53 PULLUP declarations are not supported by synthesis. W ELAB-54 User-defined primitives (UDP's) are not supported by synthesis. W ELAB-55 REPEAT constructs are not supported by synthesis. W ELAB-56 FORK and JOIN constructs are not supported by synthesis. W ELAB-57 WAIT statements are not supported by synthesis. W ELAB-58 CASE EQUALITY (===) is not supported by synthesis. W ELAB-59 CASE INEQUALITY (!==) is not supported by synthesis. W ELAB-60 TIME declarations are not supported by synthesis. W ELAB-61 EVENT declarations are not supported by synthesis. W ELAB-62 INITIAL statements are not supported by synthesis. W ELAB-63 Nonblocking assignments are allowed only when no blocking delays are used in the same process for synthesis. W ELAB-64 Blocking delays are allowed only when no nonblocking assignments are used in the same process for synthesis. W ELAB-65 Always block that has both a timing control statement as well as embedded event (@) expression is not supported by synthesis. W ELAB-66 The event depends on both edge and non-edge expression is not supported by synthesis. W ELAB-67 Only simple variables are allowed in the sensitivity list for synthesis. W ELAB-68 The event depends on two edges of the same variable is not supported by synthesis. W ELAB-69 In the event expression with 'posedge' or 'negedge' qualifier, only simple variables are allowed in synthesis. E ELAB-88 Nonblocking assignments are allowed only when no blocking delays are used in the same process for synthesis. E ELAB-89 Blocking delays are allowed only when no nonblocking assignments are used in the same process for synthesis. E ELAB-90 Always block that has both a timing control statement as well as embedded event (@) expression is not supported by synthesis. E ELAB-91 The event depends on both edge and non-edge expression is not supported by synthesis. W ELAB-92 Only simple variables are allowed in the sensitivity list for synthesis. E ELAB-93 Events which depend on two edges of the same variable are not supported by synthesis. E ELAB-94 In the event expression with 'posedge' or 'negedge' qualifier, only simple variables are allowed in synthesis. E ELAB-103 Block name symbol %s already defined E ELAB-104 Instance name symbol %s already defined E ELAB-107 Error in edge control specifier E ELAB-108 Event symbol %s already defined E ELAB-109 Unable to open file `%s': %s E ELAB-110 `%s' is not a regular file E ELAB-113 Function call %s should not have parenthesis unless it has a parameter. E ELAB-114 Function symbol %s already defined E ELAB-115 Functions cannot contain delays E ELAB-116 Functions cannot contain event control statements E ELAB-117 Inout declarations not supported in functions E ELAB-118 Function %s not defined E ELAB-119 Output declarations not supported in functions E ELAB-120 C-style function parameters found; use input declarations instead E ELAB-121 Functions cannot enable tasks E ELAB-122 function %s used as a value E ELAB-123 Functions cannot contain wait statements E ELAB-136 Redefinition of compiler directive %s not supported E ELAB-154 Parameter symbol %s already defined E ELAB-155 Unwritable parameter; only a register may be passed to an OUTPUT or INOUT formal parameter of a task (%s). E ELAB-156 A constant cannot be passed to an OUTPUT or INOUT formal parameter of a task. E ELAB-157 Mismatch in arguments to task or function %s E ELAB-159 Port %s not declared as input, output, or inout E ELAB-160 Redefinition of %s as port E ELAB-161 Port %s redeclared. E ELAB-162 Assign destination must not contain a bit- or part-select E ELAB-163 Real symbol %s already defined E ELAB-164 Symbol %s redeclared. E ELAB-165 Assignment output %s must be a register E ELAB-166 Deassign argument %s must be a register E ELAB-167 Register symbol %s already defined E ELAB-168 Assign output %s must be a register E ELAB-172 Symbol %s is not defined E ELAB-173 %s E ELAB-178 Verilog task arguments must be specified E ELAB-179 Called task %s not defined as a task E ELAB-180 Enabled task %s not defined as a task E ELAB-181 Task %s is not defined E ELAB-182 Task call %s should not have parenthesis unless it has a parameter. E ELAB-184 Too many delay values supplied E ELAB-186 Triggered event %s not defined E ELAB-187 Triggered event %s not defined as an event E ELAB-188 Lack of register declaration requires combinational primitive E ELAB-194 Register declaration %s supported only for output E ELAB-195 Existence of register declaration requires sequential primitive E ELAB-201 Part-select of a memory %s not supported E ELAB-202 Identifier %s incompatibly declared as scalar and vector E ELAB-204 EOF found in a %s block E ELAB-205 Illegal reference to event %s. E ELAB-206 Illegal attempt to declare hierarchical reference %s. E ELAB-207 malformed specify block E ELAB-208 specparam symbol %s already defined E ELAB-234 CMOS switches are not supported. E ELAB-235 NMOS switches are not supported. E ELAB-236 PMOS switches are not supported. E ELAB-249 QUASICONTINUOUS assignments are not supported. E ELAB-250 FORCE statements are not supported. E ELAB-251 RELEASE statements are not supported. E ELAB-252 DEASSIGN statements are not supported. E ELAB-253 Register (%s) is the target of both blocking and non blocking assignment in the same process; set hdlin_allow_mixed_blocking_and_nonblocking to true to permit this. F ELAB-255 Internal error in %s at line %d E ELAB-275 Must specify a named block with infer_mux when used outside a case statement. W ELAB-276 Both all symbols and listed symbols designated as %s set/reset in block '%s'; using all W ELAB-277 More than one multibit pragma specified for symbol '%s'; using '%s' W ELAB-278 The pragma '%s' for object '%s' will be ignored because the object could not be found E ELAB-281 Default branch isn't the last branch in the case statement. W ELAB-282 Parameter range specification is only meaningful to synthesis. Different result may exist from simulations. W ELAB-283 Function '%s' is mapped to module '%s' but body is non-empty; body will be ignored. E ELAB-284 Return port name '%s' conflicts with names of function input parameters. W ELAB-292 '%s' is read but does not appear in the sensitivity list of this 'always' block. W ELAB-293 Variable '%s' %s read before being assigned; the synthesized result may not match simulations. W ELAB-294 Floating pin '%s' connected to ground. E ELAB-295 Number of actual arguments in task or function call does not match the number of formals. E ELAB-296 Index bounds '%s' for vector '%s' must be integer. E ELAB-297 '%s' is a task and not a function. E ELAB-298 Array index out of bounds %s. E ELAB-299 Array index out of bounds %s. E ELAB-300 Can't test variable '%s' because it wasn't in the event expression W ELAB-301 Only constant-valued subscripts are checked in the senstivity list; other subscripted expressions are ignored. E ELAB-302 The statements in this 'always' block are outside the scope of the synthesis policy. Only an IF statement is allowed at the top level in this 'always' block. E ELAB-303 The expression in the reset condition of the 'if' statement in this 'always' block can only be a simple identifier or its negation W ELAB-304 Case has an infer_mux attribute, but also has default branch or incomplete mapping. This could cause nonoptimal logic if a mux is infered. %s E ELAB-305 Clock used as data. F ELAB-306 Illegal use of tristate value (HDL-140) E ELAB-307 in %s at line %d: Case labels are not parallel. MUX_OP can't be inferred. W ELAB-308 Mismatch between simulation and synthesis may occur due to three-state value (HDL-320) W ELAB-309 in %s at line %d: MUX_OP can't be inferred W ELAB-310 Comparison against '?', 'x', or 'z' values not inside a casex or casez is always false. W ELAB-311 DEFAULT branch of CASE statement cannot be reached. W ELAB-312 Out of bounds bit select replaced with x. E ELAB-313 Repetition multiplier in a concatenation is not constant expression W ELAB-314 Case branch%s unreachable. E ELAB-315 Tried to read a three-state value. E ELAB-316 Tried to read an 'x', '?', or three-state value. E ELAB-317 Tried to read an 'x', '?', or three-state value in a case expression. F ELAB-318 Unable to read from modfile %s: %s I ELAB-319 Reading module %s from file %s. W ELAB-320 File %s for module %s cannot be found. E ELAB-321 Number of ports on reference design '%s' is inconsistent with specified instance '%s'. E ELAB-322 Width of port '%s' on reference design '%s' is inconsistent with specified instance '%s'. E ELAB-323 Too many ports found on gate instantiation E ELAB-324 Too many ports passed to instance %s E ELAB-325 Unknown port %s in instance %s in module %s F ELAB-326 module data file revision mismatch: Expected %d, got %d F ELAB-327 Cannot resolve pin %s on cell %s:%s. E ELAB-328 Repetition multipler in concatenation contains 'x' or 'z'. W ELAB-329 A 'disable' statement for block '%s' appears outside the block and is being ignored. W ELAB-330 Attempt to disable block '%s' out of function scope is not supported. W ELAB-331 Attempt to disable block '%s' out of task scope is not supported. W ELAB-332 Concatenations cannot have unsized numbers; assuming 32 bits F ELAB-334 Part-select direction doesn't match declared direction of symbol '%s' (declared [%d:%d], part-select is [%d:%d]). W ELAB-335 'Case' statement is full and has one branch; it will be inlined. E ELAB-336 Presto does not yet support processes with multiple event statements. W ELAB-337 Assignment to supply0/1 variable '%s' is ignored. W ELAB-338 Module '%s' contains a supply0 variable '%s'. Replacing with wire driven by a continuous assignment to 0. W ELAB-339 Symbol '%s', declared as an enum, may be assigned non-enum values. E ELAB-340 Enumerated type '%s' is not compatible with type of symbol '%s'. E ELAB-341 The number of enum encodings given doesn't match the number of literals. F ELAB-900 'while' loop exceeded maximum iteration limit. F ELAB-901 Function call stack exceeded maximum depth. W ELAB-902 In the call to '$display', the '%%%c' format specifier is not supported. W ELAB-903 Insufficient pins supplied to array of modules for instance '%s' of design '%s'. W ELAB-904 When instantiating '%s' array of modules, the implementation design '%s' must be available. E ENV-1 Variable '%s' is not defined. E ENV-001 Value for %s cannot be larger than the %s value. W ENV-002 Invalid value '%s' for variable '%s'.\n\t%s I ENV-003 Using automatic %s wire load selection group '%s'%s. E EQN-1 Undefined variable on or near line %d at or near '%s'. E EQN-2 Undefined operator on or near line %d at or near '%s'. E EQN-3 Incorrect number of operands on or near line %d at or near '%s'. E EQN-4 Operator can not process operand of this type\n\ \ton or near line %d at or near '%s'. E EQN-5 Evaluation error on or near line %d at or near '%s'. E EQN-6 Internal error. E EQN-7 Evaluation error on or near line %d at or near '%s'. E EQN-8 Error on or near line %d at or near '%s'\n\ %s E EQN-9 Operator used in bad context on or near line %d at or near '%s'. W EQN-10 Defining new variable '%s'. E EQN-11 Could not write file '%s'. E EQN-12 Break statement not enclosed in loop on or near line %d. E EQN-13 Continue statement not enclosed in loop on or near line %d. E EQN-14 Can't execute command '%s' in this context on or near line %d. E EQN-15 Can't divide by zero on or near line %d at or near '%s'. E EQN-16 Operand must be positive on or near line %d at or near '%s'. E EQN-17 The abbreviated option '%s' matches more than 1\n\ \t argument for this command. E EQN-18 Unexpected argument '%s'. E EQN-19 %s required for the '%s' argument. E EQN-20 Arithmetic overflow or exception encountered. W EQN-21 Function '%s' leaked %d allocations for %d bytes. I EQN-22 Additional information in file '%s'. E EQN-23 That is an invalid name for a user defined function. E EQN-24 define_function cannot be used to redefine the builtin '%s' command. E EQN-25 The %s command cannot be used outside of a user defined function. E EQN-26 Cannot use both -remainder and -option for the get_parameter command on line %d. E EQN-27 Type '%s' is not a valid variable type for %s call on line %d. E EQN-28 Variable '%s' cannot be redefined by %s on line %d. E EQN-29 A value is required for the '%s' option of user\n\ \t function '%s' on line %d. get_parameter call on line %d fails. E EQN-30 Argument %s is required for calls to user\n\ \t function '%s' on line %d. get_parameter call on line %d fails. E EQN-31 Cannot convert value %s to type %s, %s call on line %d. E EQN-32 User function \"%s\" is not defined. E EQN-33 Specify only one of -local and -global. E EQN-34 Variable %s not defined in %s scope. E EQN-35 Variable %s not defined. E EQN-36 Variable '%s' is protected. E EQN-37 Specify either a default value, or a variable type. E EQN-38 Cannot list builtin command '%s'. E EQN-39 Cannot remove builtin command '%s'. W EQN-40 Undefined command name '%s' encountered. W EQN-41 Syntax or context checking is not supported for '%s'. E EQN-42 Argument '%s' has been specified more than once. E EQNI-1 Illegal left hand side at line %d. E EQNI-2 Illegal function at line %d. E EQNI-3 Invalid use of '?' in token '%s' at line %d. E EQNI-4 Design name must be specified at line %d. E EQNI-5 Signal ?%s set a second time at line %d. E EQNI-6 Signal %s set a second time at line %d. E EQNI-7 Invalid use of '?' in input '%s'. E EQNI-8 Port %s declared twice at line %d. E EQNI-9 Invalid use of '?' in output '%s'. W EQNI-10 Unknown command \"%s\" ignored at line %d. E EQNI-11 Can't read file \"%s\". E EQNO-0 Invalid design to write out as equations. E EQNO-1 Cannot write out design with non-combinational cell(s). E EQNO-2 Cannot write out design with INOUT ports. E EQNO-3 Cannot write out design with ports with unknown direction. W EQNO-4 The value of variable 'equationout_%s' isn't valid--using '%s'. W EST-1 The '%s' command is not supported by Estimator. The command is skipped. E EST-2 Estimator cannot proceed without an Estimation license. E EST-3 Invalid value '%s' for the 'estimate_resource_preference' variable. E EST-4 Invalid value '%s' for the 'estimate -resource_preference' option. E EST-5 The design '%s' has not been read in. E EST-6 The current design is not defined. E EST-7 Estimation terminated with errors. E EST-8 Estimation of synthetic parts failed. E EST-9 Cannot run the '%s' command on the design '%s' because it is an estimated design. E EST-10 Estimator does not support FPGA libraries. W EST-11 Estimator does not support FPGA-specific Library Component optimization. FPGA-specific optimization disabled. W EST-12 The effort level for 'flattening' was automatically reduced from 'high' to 'medium'. W EST-13 The design '%s' will be marked as an estimated design after ungrouping because one or more of its sub-designs are estimated. E EST-14 Cannot write out an estimated design in non-db format. W EST-15 The gtech design generated from this HDL compilation can be used for Estimation only. W EST-16 The current design is an estimated design : The ATPG vectors will not be saved. E EST-17 Illegal operation if an Estimator key is not checked out. W EST-18 Power constraints will be ignored during Estimation. E EST-19 The security handshake for Estimator failed. E EST-20 Cannot run Estimator stand-alone. It must be run through Chip Architect. E EXPT-1 The variable '%s' isn't defined. E EXPT-2 The variable '%s' is of an unsupported external export option type. E EXPT-3 Unknown export format '%s'. E EXPT-4 Can't open export file '%s'. E EXPT-5 Cannot execute '%s'. W EXPT-6 Library '%s' used which wasn't created by %s interface. E EXPT-8 Unable to find an external scale attribute for schematic '%s'. E EXPT-9 The external scales in libraries '%s' and '%s' aren't equal. E EXPT-10 The route grids in libraries '%s' and '%s' aren't equal. I EXPT-11 %s name '%s' changed to '%s'. I EXPT-12 Design '%s' had %d name changes. E EXPT-13 Schematic '%s' was created with an invalid \n\ \tsetting for the variable '%s'. W EXPT-14 The %s name '%s' is corrupted. W EXPT-15 The name of net '%s' in design '%s' can't be \n\ \tchanged to the name of both ports '%s' and '%s' to which it's connected. E EXPT-16 One of the %s has no name. E EXPT-17 The schematic is corrupted or is an old version. E EXPT-18 %s '%s' is corrupted. E EXPT-19 Schematic '%s' was created with incompatible \n\ \tvalues for the variables '%s' \n\ \tand '%s'. E EXPT-20 Ripper symbol '%s' in library '%s' \n\ \tis corrupted; it does not have the attribute 'ripped_pin'. E EXPT_7 %s '%s' in design '%s' has no symbol library. E FILE-1 Can't open file '%s'. E FILE-2 Can't create file '%s'. E FILE-3 Can't close file '%s'. E FILE-4 Can't close file stream for '%s'. E FILE-5 Invalid data format encountered. E FILE-6 Alias '%s' depends on itself. E FILE-7 Invalid history syntax. E FILE-8 There is no previous command. E FILE-9 Command '%d' not found; out of range. E FILE-10 '%s' not found in history. E FILE-11 Can't find file '%s'. I FLT-002 Errors preprocessing compiled filter. E FLT-003 while parsing filter expression: %s\n\tat '%s' E FLT-005 Unknown identifier: '%s' E FLT-006 Type mismatch between '%s' and '%s'. E FLT-007 Invalid operator '%s' for '%s' and '%s'. W FSM_COMP-36 For %s encoding style, all existing encodings are ignored. W FSM_COMP-37 Number of state bits reset to %d inorder to encode %d states for the %s encoding style. W FSM_COMP-38 Length of specified encodings extended to match number of state bits. W FSM_COMP-39 Number of state bits reset to length of specified encodings. E FSM_COMP-40 Can not perform %s encoding on more than 30 bits. E FSM_COMP-76 Encoding length of %d bits is too few to encode %d states. W FSM_COMP-77 State assignment used %d bits and is truncating state vector. W FSM_COMP-92 The design has zero states, consequently the design will be entirely combinational logic. W FSM_COMP-93 The design has one state, consequently the state will be removed and the design will be entirely combinational. W FSM_COMP-115 State table contains no rows. E FSM_ENC-81 Invalid base specification '%s' for encoding '%s'. E FSM_ENC-82 Invalid base specification '%s' for encoding '%s' (line: %d). E FSM_ENC-83 Invalid number specification '%s' with base '%s' for encoding '%s'. E FSM_ENC-84 Invalid number specification '%s' with base '%s' for encoding '%s' (line: %d). E FSM_ENC-85 Overflow for encoding '%s'. E FSM_EX-34 Design must have only input and output ports. E FSM_EX-47 Can not extract design where state vector is partially reset. E FSM_EX-48 Invalid reset for state vector '%s'. E FSM_EX-49 Multiple clock signals '%s' and '%s' not allowed. E FSM_EX-50 Multiple clock phases not allowed. E FSM_EX-51 Multiple reset signals '%s' and '%s' not allowed. E FSM_EX-52 Multiple reset phases not allowed. E FSM_EX-53 Multiple drivers on %s network not allowed. E FSM_EX-54 Illegal %s logic for state vector element '%s'. E FSM_EX-55 Net '%s' on %s network has no drivers. W FSM_EX-56 State vector for state table extraction not specified. W FSM_EX-57 Assuming all non-combinational cells are the state vector. E FSM_EX-58 Design has no flip-flop instances. E FSM_EX-59 State vector cell '%s' is not in design. E FSM_EX-60 Invalid non-combinational cell '%s'. E FSM_EX-61 State vector cell '%s' is not clocked. E FSM_EX-62 No state encodings provided for design...\n\ \tConsequently, the state vector can not be longer than 20. W FSM_EX-63 No state names provided for design.\n\ \tState names will automatically be generated. W FSM_EX-64 No state encodings provided for design.\n\ \tAll possible state codes will be used. E FSM_EX-65 For extraction, state codes must be specified with the state names. E FSM_EX-66 Reset state code '%s' is not a valid state. E FSM_EX-74 Could not convert flip-flops to generic. E FSM_EX-75 The specified state encodings are inconsistent with length of state vector. E FSM_EX-88 Can't extract design with combinational feedback loops. E FSM_EX-98 One or more starting states are required for extraction using reachability E FSM_EX-113 Design is already a state table. W FSM_EX-114 Extraction resulted in a state table with no rows. E FSM_EX-116 Asynchronous reset signal '%s' cannot drive combinational logic of the state machine. E FSM_EX-117 Clock signal '%s' cannot drive combinational logic of the state machine. E FSM_EX-126 Cannot extract multiple clocks feeding state vector element '%s'. E FSM_EX-127 Extraction is too expensive. W FSM_EX-133 Ignoring missing state vector cell '%s'. E FSM_EX-134 State vector for state table extraction must be specified. E FSM_EX-140 State encoding '%s' for state '%s' is invalid. W FSM_EX-141 The output function for state '%s' is too large to be represented. W FSM_EX-142 The transition function for state '%s' is too large to be represented. E FSM_GRP-59 State vector cell '%s' is not in design. E FSM_GRP-87 No state vector specified for grouping of FSM. E FSM_IN-0 Can not read file '%s'. W FSM_IN-1 Illegal command '%s' (line: %d). E FSM_IN-2 Input port '%s' declared twice (line: %d). E FSM_IN-3 Output port '%s' declared twice (line: %d). W FSM_IN-4 Only one %s command allowed (line: %d). E FSM_IN-5 Missing %s (line: %d). E FSM_IN-6 %s signal '%s' is not an input port (line: %d). E FSM_IN-7 Invalid %s sense '%s' (line: %d). E FSM_IN-10 State '%s' is not a state in the state table (line: %d). E FSM_IN-11 State '%s' used multiple times in .encoding (line: %d). E FSM_IN-13 Binary encoding '%s' used multiple times ('%s' at line %d and '%s' at line %d). E FSM_IN-15 State table must have a clock specified. E FSM_IN-16 State table must have at least one %s. E FSM_IN-17 Mismatched number of %s. E FSM_IN-19 The clock and reset can not be the same input port. E FSM_IN-21 Too few binary inputs (line: %d). E FSM_IN-22 Too many binary inputs (line: %d). E FSM_IN-23 Invalid character '%c' for binary input (line: %d). E FSM_IN-24 Could not read present state (line: %d). E FSM_IN-25 Illegal present state '%s' (line: %d). E FSM_IN-26 Could not read next state (line: %d). E FSM_IN-27 Illegal next state '%s' (line: %d). E FSM_IN-28 Could not read binary outputs (line: %d). E FSM_IN-29 Too few binary outputs (line: %d). E FSM_IN-30 Too many binary outputs (line: %d). E FSM_IN-31 Invalid character '%c' for binary output (line: %d). E FSM_IN-78 Unknown port '%s' in .field statement (line: %d). E FSM_IN-79 Invalid order of input and output ports at '%s' (line: %d). E FSM_IN-86 Can not transition to invalid next state (line: %d). W FSM_IN-89 The state table has zero states. E FSM_IN-103 Ambiguous output values specified at lines %d and %d. W FSM_IN-115 State table contains no rows. E FSM_IN-129 The use of the percent operator has resulted in an ambiguous specification. W FSM_IN-131 Ignoring row at line %d since previous row(s) containing the percent operator cover all input conditions implied by this row. W FSM_LINT-104 In design '%s', the next state is unspecified for some transitions. W FSM_LINT-105 In design '%s', the next state is unspecified for some transitions from state '%s'. W FSM_LINT-106 In design '%s', some output values are unspecified. W FSM_LINT-107 In design '%s', the value for output '%s' is unspecified for some transitions from state '%s'. W FSM_LINT-108 In design '%s', no transitions are specified from some states. W FSM_LINT-109 In design '%s', no transitions are specified from state '%s'. W FSM_LINT-110 In design '%s', no transitions are specified to some states. W FSM_LINT-111 In design '%s', no transitions are specified to state '%s'. W FSM_LINT-112 In design '%s', the state graph is disconnected. W FSM_LINT-141 FSM for design %s is very large. Consider partitioning the design for better results. W FSM_LINT-142 FSM size is very large. Consider partitioning your original design. E FSM_LINT-143 The number of outputs in the state table is %d\ but the number of outputs in the design is %d. W FSM_LINT-151 The output port '%s' has no drivers. E FSM_OUT-32 Design %s is not a state table. E FSM_OUT-34 Design must have only input and output ports. W FSM_OUT-115 State table contains no rows. I FSM_RED-143 reduce_fsm is too expensive...unable to complete E FSM_UI-32 Design %s is not a state table. W FSM_UI-94 State minimization found all states equivalent, consequently the design will be entirely combinational. E FSM_VER-68 The two state machines do not have the same number of ports. E FSM_VER-69 The two state machines do not have identical ports. E FSM_VER-70 The two state machines do not have the same number of states. E FSM_VER-71 The two state machines do not have identical states. E FSM_VER-72 The two state machines are not equivalent. I FSM_VER-73 The two state machines are equivalent. E FSM_VER-96 Design '%s' requires a single reset state for verification. E FSM_VER-97 Design '%s' requires a state vector for verification. E FSM_VER-130 The length of the encoding for the initial state for design '%s' is inconsistent with the length of the state vector. E FSM_VER-132 The two designs must be netlists for verification. E FSM_VER-135 Design '%s' must have only input and output ports. E FSM_VER-136 Design '%s' contains invalid non-combinational cell '%s'. E FSM_VER-137 Design '%s' contains combinational feedback loops. W FSM_VER-138 Ignoring missing state vector cell '%s' in design '%s'. E FV-1 The design to align '%s' is not in the original hierarchy. W FV-2 These endpoints are driven by combinational feedback loops.\n\ \tThey will be set to logic zero during verification. I FV-3 Setting input port '%s' to logic %s in design %s.\n\ The 'test_hold' attribute has value %d. E FV-4 This message is not currently used. E FV-5 Cannot find cell in original design with name '%s'. I FV-6 Setting JTAG Instruction Register outputs to logic one in design '%s'. I FV-7 Ignoring JTAG Test Data Out port in design '%s'. W FV-8 No JTAG Test Data Out port was found. I FV-12 Setting scan input port '%s' to logic %s in design %s. W FV-13 Verification failures may be caused by the level_sensitive\n\ or clocked_on_also attribute on port '%s'. E FV-14 The following involve unconnected endpoints: E FV-15 Could not align these output ports in %s design '%s': I FV-16 No logical constant assignments were made to JTAG\n\ pins in design '%s'. E FV-17 Could not align subdesign '%s'. W FV-18 Accepting design '%s' because its DB reference design,\n\ '%s', is the same in both hierarchies. E FV-19 First design '%s' has %0d subdesigns, \n\ \tbut second design '%s' has %0d subdesigns. E FV-20 Could not open file: '%s'. E FV-21 This message is not currently used. W FV-22 Cell '%s' is an empty subdesign in design\ '%s'.\ The inputs of the cell will be ignored, not treated as verification endpoints. I FV-23 This message is not currently used. W FV-24 The two designs have the same DB reference. I FV-25 Interpreting '%s' in %s design as %s. E FV-26 Scan style '%s' not supported in compare_design or compile." I FV-27 Using non-hierarchical verification because of boundary optimization. E FV-28 Original and optimized designs have different scan styles: '%s' '%s'. I FV-29 Using non-hierarchical verification because of scan insertion. E FV-30 This message is not currently used. E FV-31 Cannot find the clock pin on the sequential cell '%s'. W FV-32 Discarding Dont-Care information on DB subdesign '%s'. E FV-33 Could not open fv_report file. E FV-34 This message is not currently used. E FV-38 Cannot find port or combinational cell '%s' in design '%s'. E FV-39 Null token in pathname '%s'. E FV-40 Cannot find cell '%s' in design '%s'. E FV-41 Cannot find pin '%s' on hierarchical cell '%s' in design '%s'. E FV-42 The name '%s' is a pathname, not a port, sequential cell, or cell/pin name. E FV-43 There are no exact name matches in subdesign '%s' for: E FV-45 Expecting an instance pathname of subdesign, or '%s';\n\ \tnot '%s'. E FV-46 Cannot find design hierarchy '%s'. E FV-47 Cannot find instance '%s' within design '%s'. E FV-48 List of points to align does not have even number of names. W FV-49 Subdesign '%s' being accepted more than once. E FV-50 The list of designs to accept does not have even number of names. E FV-51 These points appear more than once in following -invert_phase option for design '%s': E FV-52 These points appear more than once in -invert_phase lists for design '%s': E FV-53 Cannot combine an -only script entry with other -only\ entries or with an -ignore entry. E FV-56 No pathname specified in the following script entry: E FV-57 Two pathnames specified in %s script entry: '%s' '%s'. E FV-58 Cannot process script entry: I FV-59 Not assigning input scan port '%s' in second design, \n\ \t because port is connected in first design. E FV-60 Attempted to invert phase of sequential cell with non-complementary outputs: '%s'. E FV-61 The point to phase invert is not a port or sequential cell: '%s'. E FV-62 Cannot find sequential cell or port '%s' in design '%s'. W FV-63 Some black-box cells exist during verification W FV-64 An inout port has different interpretations in verification: W FV-65 Ignoring %s option for points in original design '%s': I FV-66 In verifying the %s design, these are treated as %s: E FV-69 This message is not currently used. E FV-70 The endpoint to ignore, '%s', is not an output port, \ a register, or a hierarchical cell of design '%s'. E FV-72 The point to check for redundancy, '%s', in design '%s' is not a source point. E FV-73 The original design, '%s', was found to have these scan\ ports, illegal in verification: E FV-74 Failure in applying set_compare_design_script. W FV-75 The following points in design '%s' were aligned more than once: W FV-76 The following points were aligned more than once to points in design '%s': W FV-77 Realigning point '%s' in design '%s'\n\ \t and unaligning point '%s' in design '%s'. E FV-78 Cannot align these two points: '%s/%s' and '%s/%s'." E FV-80 Attempted to align design '%s' with both design '%s' and design '%s'." E FV-81 Cannot '%s' designs '%s' and '%s', at different depths in hierarchies. E FV-83 In %s design %s, cell '%s' is an empty subdesign.\n\ \tIn %s design %s, you must ungroup unaligned cell '%s'. I FV-84 In %s design %s there is %s unique to E GEN-1 Cell '%s' instance '%s' pin '%s' has same Y coordinate as cell '%s' instance '%s' pin '%s'. E GEN-2 Pin '%s' on Cell '%s' does not lie on a grid. W GEN-3 Creating a symbol for cell '%s' of type '%s'. E GEN-4 Could not find pin: '%s', in cell: '%s' in schematic library '%s'. E GEN-5 Symbol library doesn't have off-sheet connectors. W GEN-6 Symbol exceeds sheet size. W GEN-7 Maximum ports on symbol side limit of '%d' exceeded. W GEN-8 Can't rename off-sheet connector of net '%s'\n\ to the name of its port '%s'\n\ because net '%s' already exists. W GEN-10 Couldn't find all the port symbols in the generic symbol library. E GEN-11 Couldn't find pin name '%s' in ripper symbol '%s'. E GEN-12 Couldn't find a ripper symbol for creating a bussed schematic. E GEN-13 Annotator '%s' has an invalid format specification '%s'. E GEN-14 An unnamed annotator has an invalid format specification '%s'. E GEN-15 Annotator '%s' has more than %d '%%s' specifications \n\ \tin the format string. E GEN-16 An unnamed annotator has more than %d '%%s' \n\ \tspecifications in the format string. E GEN-17 Annotator '%s' has an invalid expression '%s'. E GEN-18 An unnamed annotator has an invalid expression '%s'. W GEN-19 The symbol for cell '%s' has a pin off the route grid.\n\ \tYou may be mixing symbol libraries with different route grids. E GEN-20 One of the pins or port busses is corrupted. E GEN-21 Cell %s's pin %s is on wrong side. E GEN-22 Net %s connects pins of different widths. W GEN-23 The netlist contains bus-to-bus connections. Any \n\t nets involved in inter-bus connections will be \n\t displayed as disconnected in the no-ripper schematic. E GEN-24 Could not find the type mapper symbol in the \n generic symbol library. The generic symbol library \n is probably old - Please use a new library and \n recreate the schematic. W GEN-25 All cells are power/ground or have no connection. E GEN-26 member '%d not found in bus '%s' . Only following members present : '%s'. The design is corrupted. E GLO-1 %s W GR-1 Route %% changed to %3.1f for %s route layers. W GR-2 Cell locations will not be used for IPO delay updates. W GR-3 Location based optimizations disabled. I GR-4 %s - horizontal: %.2g vertical: %.2g I GR-5 Using user specified R and C coefficients. I GR-6 Using edge_capacity_x: %g, edge_capacity_y: %g. gcell_size: %d. I GR-7 Capacitance and Resistance Units I GR-8 Using derived R and C coefficients. E HDL-1 Can't open Synopsys primitive package '%s' E HDL-2 Corrupt Synopsys primitve package E HDL-3 Can't find primitive \"%s\" %s E HDL-4 Condition of 'if' statement must be a single bit %s E HDL-5 Loop increment is zero %s W HDL-6 Loop body will iterate zero times %s E HDL-7 Loop will iterate over 1,000 times. (This will take a while.) %s E HDL-8 Illegal exit to block %s E HDL-9 Illegal exit to block %s %s E HDL-10 Connection to port%s may not be a string %s E HDL-11 Connection to port%s must be a variable %s E HDL-12 Used constant%s which has not been given a value %s E HDL-14 Tried to assign a value to a literal %s E HDL-15 Literal may contain only '0', '1', 'Z', 'D', or 'U' %s E HDL-16 Type of '%s' is unconstrained %s E HDL-17 Untyped variable%s used %s E HDL-18 Tried to read from a block with no direction %s E HDL-19 Tried to write to a block with no direction %s E HDL-20 Block expects value, but none was supplied %s E HDL-21 Block returns value, but was assigned one %s E HDL-22 Can't resolve goto to label '%s' %s E HDL-23 Array index out of bounds %s. E HDL-25 Range is unconstrained %s E HDL-26 Found a negative value where a unsigned value was expected %s E HDL-27 Constant value required %s E HDL-28 Operand is not a value %s E HDL-29 Operand is not a type %s E HDL-30 Operand is not a string %s E HDL-31 Too few input operands on dnode %s E HDL-32 Too many input operands on dnode %s E HDL-33 Too few output operands on dnode %s E HDL-34 Too many output operands on dnode %s E HDL-36 Source type of assignment is unconstrained %s E HDL-37 Tried to assign a value to an invalid symbol %s E HDL-38 Type mismatch %s. E HDL-39 Tried to assign a type to an invalid symbol %s E HDL-40 Target %s is incompatible with assigned value\n\ \t%s E HDL-41 Expected %s but was supplied %s %s E HDL-42 Port%s has no type %s E HDL-43 Tried to take a slice out of a non-array %s E HDL-44 Arguments to '%s' are not the same size %s E HDL-47 Divide by zero %s E HDL-48 Negative exponent %s E HDL-50 Can't get member of array %s E HDL-51 Indexing into a non-array variable is not supported %s. E HDL-52 AGG major type must be an array %s E HDL-53 Tried to take a member from a non-array %s E HDL-54 Subtype in aggregate was not a submember or subrange %s E HDL-55 Source and target of slice assignment are not the same size %s E HDL-56 Not enough args to 'lagg' %s E HDL-57 Argument to '%s' is not an array or range %s E HDL-58 Argument to '%s' is unconstrained %s E HDL-60 Casted from an unconstrained type %s E HDL-61 Direction ('to' or 'downto') does not agree with 'first'\n\ \tand 'last' values in range %s E HDL-62 'binned_range' requires at least one operand %s E HDL-63 Last name has no encoding %s E HDL-64 %s was assigned values of different sizes %s E HDL-65 %s %s E HDL-66 Was expecting a positive number, got %d instead %s E HDL-67 Duplicate name in enum definition: '%s' %s E HDL-68 Encoding '%s' for '%s' is not valid. E HDL-69 Can't find a design or function '%s' to overload %s E HDL-70 Can't find lvalue version of design '%s' %s E HDL-71 Constant value %d overflowed '%s' %s E HDL-72 Slice width '%d' is not positive %s E HDL-73 Can't overload design '%s' uniquely %s E HDL-74 At least one argument required for '%s' %s E HDL-76 'others', vhdl range choices, and multiple choices\n\ \tin left-hand-side aggregates must be connected to OPEN%s E HDL-77 Tried to change the type of %s %s E HDL-78 Tried to assign an unconstrained type to variable%s %s E HDL-79 Illegal open connection to builtin function %s E HDL-80 Variable%s has an uninitialized type %s E HDL-81 Can't find a design '%s' that has correct parameter profile\n\ \t(Could be a type mismatch)%s E HDL-82 Unknown HDL format '%s' E HDL-83 Can't open %s primitive package '%s' E HDL-84 Was expecting a non-negative number, got %d instead %s E HDL-85 Subprogram body or architecture for '%s' was not defined %s. E HDL-86 Subprogram '%s' was used but has no body defined %s E HDL-87 Value cannot be interpreted as a boolean %s E HDL-90 Slice direction does not match array direction %s W HDL-91 Can't find '%s' referred to by the '%s' attribute %s W HDL-92 Ignored illegal EQUAL or OPPOSITE attribute %s W HDL-93 %s %s E HDL-94 Aggregate contains too many elements %s. E HDL-95 Aggregate contains too few elements %s. E HDL-96 Infinite recursion detected %s E HDL-97 Can't determine type of operand %s E HDL-98 Non-static loop or event waits in only some branches detected %s E HDL-99 Tried to use the value of an instance which does not return a value %s E HDL-100 Aggregate type is an unconstrained array %s E HDL-101 Argument must be a constrained array %s W HDL-103 Function may be completed without returning a value %s E HDL-104 Can't get width of port %s %s E HDL-105 HDL translation aborted. E HDL-106 Bits of range driven differently %s E HDL-107 Tried to use a synchronized value %s E HDL-108 Tried to use a conditionally driven value%s %s E HDL-109 This use of clock edge specification not supported %s E HDL-110 Illegal assignment to '%s'. It depends on a non-edge %s E HDL-111 Illegally declared clock edge specification %s. E HDL-112 Range (integer) types are illegal on inout (out) signal parameters to procedures %s. E HDL-113 Width of port %s is inconsistent with other instances %s E HDL-114 Number of ports of instance is inconsistent with other instances %s E HDL-115 Illegal mixing of named and unnamed port association %s E HDL-116 Parameter%s must be associated with a constant %s E HDL-117 Register inference not supported if "hdlin_infer_reg_and_latch" is false %s E HDL-118 Single bit value expected %s E HDL-123 Can't determine type of aggregate or concat %s E HDL-124 Elements of aggregate or string literal are\n\ \tout of bounds, overlap, or do not cover all cases %s E HDL-127 Argument to concat has incorrect size %s E HDL-130 Could not find synthetic_library '%s' E HDL-131 synthetic_library '%s' is not a valid library W HDL-135 In resource '%s' %s\nOPS entry '%s' is already included in resource '%s' %s.\nEntry ignored. E HDL-139 %s '%s' could not be found in the search path %s. E HDL-140 Tried to read a %s value%s %s W HDL-141 '%s' does not indicate a unique instance or resource in resource '%s' %s W HDL-142 Instance or resource '%s' not found in resource '%s' %s W HDL-143 Subroutine label '%s' is not unique in scope. Label ignored. %s */ W HDL-144 No appropriate operation, procedure or function to which label '%s' can be bound E HDL-145 Label '%s' used on more than one resource in same scope %s E HDL-146 Type function '%s' not found %s E HDL-147 Ports of type function '%s' don't match %s E HDL-148 Invalid constraint on an enumeration type %s E HDL-149 Synthetic library has no one-bit multiplexor. E HDL-150 Component implication (map_to_entity) subprogram port\n\ \t'%s' has an unconstrained type %s E HDL-151 You are only allowed to use state vector '%s' in one process per design. E HDL-152 Expected an enumeration literal %s E HDL-153 Share effort '%s' is not supported E HDL-154 Inconsistent port declaration detected for port%s %s E HDL-155 value '%d' is not within array bounds [%d, %d] %s E HDL-156 Index range [%d,%d] is not within array bounds [%d,%d] %s W HDL-158 State vector '%s' was specified, but is not a valid\ state vector. E HDL-159 Operator '%s' not found in synthetic library. W HDL-160 No synthetic_library specified. Resource sharing is disabled. W HDL-162 may_merge_with and dont_merge_with conflict in resource '%s'\n\ \tmay_merge_with ignored %s E HDL-163 Resolution function '%s' must be labeled with a "resolution_method" pragma\n\ \t. Resolution functon ignored %s. E HDL-164 Resolution function '%s' is not legal for variable or type %s\n\ \tUse "wired_and", "wired_or", or "three_state" %s. E HDL-165 Cannot find resolution function '%s'.\n\ \tResolution function ignored. E HDL-167 %s contains the invalid string '%s'. W HDL-169 The state-vector does not fan out. It's flip-flops are being deleted. W HDL-170 Comparisons to a '%s' are treated as always being false %s\n\ \tThis may cause simulation to disagree with synthesis. E HDL-172 Variable%s, which is assigned using RTL\ assignment, cannot accept return values from a task call%s. W HDL-173 Add_ops attribute value "%s" is not valid for resource '%s'.\n\ \tAttribute value is assumed to be "false". E HDL-174 Variable%s of type 'wire' cannot accept return values from a task call%s. E HDL-175 Clock variable '%s' is being used as data %s. W HDL-176 Variable '%s' is being read asynchronously %s.\n\ \tThis may cause simulation-synthesis mismatches. W HDL-177 Local variable '%s' is being read before its value is assigned,\n\ \t%s.\n\ \tThis may cause simulation not to match synthesis. W HDL-178 Only simple variables are checked in the sensitivity list. The variable in the sensitivity list\n\ \ton line %d will be ignored. W HDL-179 Variable '%s' is being read %s, \n\ \tbut is not in the process sensitivity list of the block which begins \n\ \tthere. W HDL-180 Variable '%s' is being read %s,\n\ \tbut does not occur in the timing control of the block which begins\n\ \tthere. E HDL-183 The multi-bit clock '%s' is not supported %s. E HDL-184 Case statement was not fully specified.\n\ \t(There exists no TRUE branch)%s E HDL-185 Couldn't find the package '%s' in memory. E HDL-186 An order based parameter was specified after a name \ based\n\ \tparameter for the template '%s' %s E HDL-187 Too many parameters were specified for the template '%s'. E HDL-188 The parameter '%s' does not exist on template '%s'. E HDL-189 Couldn't find the template '%s' in memory. E HDL-190 The variable '%s' has an illegal format.\n\ \tPlease check documentation. E HDL-191 The parameter '%s' is not a valid integer. W HDL-192 '%s' is an invalid argument for variable '%s'. I HDL-193 Building the design '%s'%s. E HDL-194 Could not find the template %s E HDL-195 Couldn't find the symbol '%s'.\n\ \tThis is probably because the %s '%s' is not\n\ \tthe same %s that the %s '%s'\n\ \twas analyzed with. E HDL-200 clause must be the last clause in a case statement. E HDL-201 Character '%c' is not allowed in the variable '%s'. I HDL-202 Saving the %s '%s'. I HDL-203 Overwriting the %s '%s'. E HDL-204 Too many generics were specified%s E HDL-205 The value specified for generic '%s' is out of range%s E HDL-206 Cannot determine type of the aggregate %s\n\ \t(This error can occur if an aggregate and a generic appear in the\n\ \tsame component instantiation.) E HDL-207 %s contains the invalid list '%s'. W HDL-208 hdlin_source_to_gates_mode set to invalid value "%s", "off" will be used instead. W HDL-209 The VHDL design '%s' contains generics but was treated\n\ \tas a "design." To save as a "template", which can be instantiated\n\ \twith different parameters, use the "analyze" command. This is recommended\n\ \tsince this does not require changing HDL code or setting any variables.\n\ \tAlternately reread file(s) with '%s = "TRUE"', or insert the\n\ \tsynthetic comment "template" in the HDL source. E HDL-210 Can't find port '%s' on synthetic operator '%s' %s W HDL-211 Configurations are ignored during %s.\n\ \tThe %s/%s commands must be used\n\ \tto build a configuration. E HDL-213 The library '%s' is mapped to the directory '%s' which is not writable. The VHDL analyzer can not be invoked. W HDL-220 Variable '%s' is driven in more than one process or block \n\ \tin file %s\n\ \tThis may cause mismatch between simulation and synthesis. E HDL-222 Process %s\n\ \thas both a sensitivity list as well as embedded wait statements. E HDL-223 Always block %s\n\ \thas both a timing control statement as well embedded\n\ \tevent ('@') expressions. E HDL-224 Wait statements in process %s\n\ \tuse different clocks or clock edges. E HDL-225 Event ('@') expressions in always block %s\n\ \tuse different clocks or clock edges. E HDL-226 Process %s\n\ \tcontains unsupported wait statements. E HDL-227 Always block %s\n\ \tcontains unsupported event ('@') expressions. E HDL-230 '%s' is used as a name for an internal package. Please use\n\ \ta different name for your package. W HDL-231 The enum encoding '%s' is not a valid state machine encoding.\ \n\ \tThe state name for the state '%s' will not be saved. E HDL-232 The encoding '%s' for state '%s' is invalid. W HDL-233 The encoding '%s' for state '%s' is a duplicate\n\ \tof state '%s'. This state name will not be saved. W HDL-234 Design '%s' has multiple architectures defined.\n\ \tThe first architecture defined ('%s') will be\n\ \tused to build the design. E HDL-235 Could not read 'gtech.db' in the libraries/syn directory. W HDL-236 Non-constant case-item used in casex or casez.\n\ \tHDL Compiler assumes the expression is never 'x' or 'z' %s E HDL-240 Pragma map_to_entity is not supported for procedures with INOUT ports.\n\ \tPort '%s' is defined as an INOUT port '%s'. E HDL-241 Unable to resolve GTECH reference. E HDL-250 Can not synthesize logic for assignment of UNKNOWN to identifier %s\n\ \t%s. W HDL-260 The parameter '%s' is not a valid integer.\n\ \tTreated as uninitialized when using the get_attribute command. E HDL-270 An unsupported expression is assigned to constant '%s'\n\ \t%s. W HDL-272 Selector for MUX is always logic one - %s W HDL-281 Signal %s\n\ \thas the asynchronous set/reset attribute attached but not used\n\ \tfor set/reset in design '%s'. W HDL-282 Signal %s\n\ \thas the synchronous set/reset attribute attached but not used\n\ \tfor set/reset in design '%s'. W HDL-283 Signal '%s' has the asynchronous set/reset attribute\n\ \tattached in process %s but not used for set/reset in that process. W HDL-284 Signal '%s' has the synchronous set/reset attribute\n\ \tattached in process %s but not used for set/reset in that process. E HDL-285 Cannot find matching slave process '%s' for\n\ \tmaster process %s. W HDL-287 State output of master latch '%s' does not connect\n\ \tdirectly to input of salve latch '%s'.\n\ \tFail to infer master-slave latch. W HDL-288 Master latch '%s' and slave latch '%s'\n\ \thave independent asynchronous-clear controls.\n\ \tFail to infer master-slave latch. W HDL-289 Master latch '%s' and slave latch '%s'\n\ \thave independent asynchronous-set controls.\n\ \tFail to infer master-slave latch. W HDL-290 Master latch '%s' and slave latch '%s'\n\ \thave independent asynchronous-clear/set controls.\n\ \tFail to infer master-slave latch. W HDL-291 State output of master flip-flop '%s' does not connect\n\ \tdirectly to input of slave flip-flop '%s'.\n\ \tOr the input of slave flip-flop is driven by multiple sources including\n\ \tthe state output of master flip-flop.\n\ \tFail to infer master-slave flip-flop. W HDL-292 Master flip-flop '%s' and slave flip-flop '%s'\n\ \thave independent asynchronous-clear controls.\n\ \tFail to infer master-slave flip-flop. W HDL-293 Master flip-flop '%s' and slave flip-flop '%s'\n\ \thave independent asynchronous-set controls.\n\ \tFail to infer master-slave flip-flop. W HDL-294 Master flip-flop '%s' and slave flip-flop '%s'\n\ \thave independent asynchronous-load controls.\n\ \tFail to infer master-slave flip-flop. W HDL-295 Master flip-flop '%s' and slave flip-flop '%s'\n\ \thave different asynchronous data.\n\ \tFail to infer master-slave flip-flop. W HDL-296 Master flip-flop '%s' and slave flip-flop '%s'\n\ \thave independent asynchronous-clear/set controls.\n\ \tFail to infer master-slave flip-flop. W HDL-297 Slave flip-flop '%s' has synchronous-clear control,\n\ \tcannot be merged with master flip-flop '%s'.\n\ \tFail to infer master-slave flip-flop. W HDL-298 Slave flip-flop '%s' has synchronous-set control,\n\ \tcannot be merged with master flip-flop '%s'.\n\ \tFail to infer master-slave flip-flop. W HDL-299 Slave flip-flop '%s' has synchronous-toggle control,\n\ \tcannot be merged with master flip-flop '%s'.\n\ \tFail to infer master-slave flip-flop. W HDL-300 State output of master cell '%s' drives nets\n\ \tin addition to the input of slave cell '%s'.\n\ \tFail to infer master-slave latch/flip-flop. W HDL-301 Master latch '%s' cannot be merged with slave flip-flop '%s'.\n\ \tFail to infer master-slave latch/flip-flop. W HDL-302 Master flip-flop '%s' cannot be merged with slave latch '%s'.\n\ \tFail to infer master-slave latch/flip-flop. W HDL-303 Master cell '%s' cannot find its matching slave cell.\n\ \tFail to infer master-slave latch/flip-flop. W HDL-304 Slave cell '%s' cannot find its matching master cell.\n\ \tFail to infer master-slave latch/flip-flop. E HDL-305 '%s' is not a port or variable/signal, cannot be used\n\ \tfor asynchronous set/reset control in process %s. E HDL-306 '%s' is not a port or variable/signal, cannot be used\n\ \tfor synchronous set/reset control in process %s. W HDL-307 Latch inferred in design '%s' read with\n\ \t'hdlin_check_no_latch'. W HDL-308 One_hot/one_cold pragma containing '%s' and '%s'\n\ \tis used to optimize set/reset condition for cell '%s'.\n\ \tMake sure there is an assertion for this one_hot/one_cold pragma. W HDL-309 Object '%s' appears in two one_hot directives.\n\ \tThe directive containing this object is ignored. W HDL-310 Object '%s' appears in two one_cold directives.\n\ \tThe directive containing this object is ignored. W HDL-311 Object '%s' appears in an one_hot directive and an one_cold directive.\n\ \tThe directive containing this object is ignored. W HDL-312 The design being compiled contains %d operations.\n\ \tBecause of the large search space, resource sharing may\n\ \ttake a long time to complete. You might consider turning resource\n\ \tsharing and resource implementation to area only. W HDL-320 Mismatch between simulation and synthesis may occur because of\n\ \tthree-state value %s used %s.\n E HDL-321 Assignment to loop index '%s' is beyond synthesis policy\n\ \t%s.\n E HDL-322 Bad bus_naming_style variable '%s' used. E HDL-325 Constant propagation on constant larger than 32 bits is not supported %s.\n E HDL-326 Enumeration type defined in a generate statement is not supported %s.\n E HDL-327 Connection to instance port %s is too wide %s.\n E HDL-328 Connection to instance port %s is too narrow %s.\n E HDL-330 Port name '%s' mismatches names of synthetic operator %s.\n E HDL-350 %s\n\ \tin parsing parameter value: %s\n\ \tfor parameter '%s' E HDL-351 Specified value: %s \n\ \t for parameter '%s' has improperly sized array elements E HDL-352 Specified value: %s\n\ \tfor parameter '%s' is not the correct size E HDL-353 Can't find type information (.typ file) for type '%s'. E HDL-354 Can't find directory '%s'. W HDL-360 The variable hdlin_files is not supported for \ releases later than v3.3b. W HDL-361 The variable hdlin_source_to_gates_mode is \ obsolete with v3.3a. E HDL-362 Can't find design for cell '%s' on line %d in '%s'. W HDL-370 You are using the full_case directive \ with a case statement in which not all cases are covered. W HDL-371 You are using the parallel_case directive \ with a case statement in which some case-items may overlap. W HDL-380 No MUX_OP inferred for the case %s because it might lose the benefit of resource sharing. W HDL-381 A MUX_OP has been inferred for the case %s which may possibly lose the benefit of resource sharing. W HDL-382 A MUX_OP has been inferred for the case %s which has either a default clause or an incomplete mapping. W HDL-383 A MUX_OP was not inferred for the case %s because its branching factor of %d is greater than hdlin_mux_size_limit. W HDL-384 A MUX_OP for the case %s was not inferred because the variable hdlin_infer_mux was set to "none." W HDL-385 A MUX_OP for the case %s was inferred because the variable hdlin_infer_mux was set to "all." E HDL-386 Number of enumeration encoding values does not match the number of enumeration values. E HDL-387 Can't redefine reference named '%s' %s E HDL-388 Can't find declarative scope for component '%s' W HDL-389 The following design name is very long:\n\ \t'%s'\n W HDL-390 Statement not accelerated: Line %d, %s E HDL-391 Naming clash with %s E HDL-392 Combinational loop found on a sequential element \ pin (net; %s). W HDL-393 A MUX_OP was not inferred for the case %s because the ratio of MUX_OP data inputs to unique data inputs is %d, which exceeds the hdlin_mux_oversize_ratio. W HDL-394 Unconditional concurrent assignment to tristate value %s,\n\ \tmay not result in hardware. W HDL-395 The statement %s,\n\ \tis never reached. W HDL-396 The flip-flop/latch %s, has asynchronous feedback. \n\ this feedback will not be removed. W HDL-397 A feedback loop found at buffer or inverter '%s' E HDL-398 Loop index %s is not initialized %s W HDL-399 NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE \"%s\" %s W HDL-400 Clock signal is not in the sensitivity list. \"%s\" %s W HDL-401 The mode selected for resource implementation \n\ \tis use_fastest. The mode selected for resource allocation is \n\ \teither none or area_only. The fastest possible implementation \n\ \twill initially be selected for each resource. If you know that \n\ \ttiming will be met with the smallest implementations it might \n\ \tsave CPU time to set resource implementation to area_only. E HDL-402 No implementation is available for module %s. E HDL-403 You cannot use a "for" loop iterator \ that is more than 32 bits wide. E HDL-404 You cannot use a duplicate count of 0. W HDL-405 Local variable %s define %s is being read before it is fully assigned W HDL-410 The design being compiled contains %d\n\ \toperations. Because of the large search space, resource sharing\n\ \tmay take a long time to complete. You might consider turning\n\ \tresource allocation to area only. W HDL-411 The design being compiled contains %d\n\ \toperations. Because of the large search space, resource\n\ \timplementation may take a long time to complete. You might\n\ \tconsider turning resource implementation to area only. E HDLA-1 Design '%s' does not contain HDL analysis information. E HDLA-2 Errors detected while linking '%s' to '%s'. W HDLA-3 Errors detected while linking '%s' to '%s'. W HDLA-4 Port '%s' of GTECH design '%s' is not found in the mapped design. E HDLA-5 Design '%s' is multiply defined. E HDLA-6 Can't find instance '%s' in design '%s'. E HDLA-7 Design '%s' contains repeated instances.\n \ \tPlease use the uniquify or set_dont_touch commands on them. E HDLA-8 Can't find design '%s'. W HDLA-9 The GTECH design %s does not have HDL analysis information. W HDLA-10 Design '%s' does not contain HDL analysis information. E HDLA-11 Variable '%s' is not set. W HDLA-12 Variable '%s' is not set. E HDLA-13 Can't find '%s' in path '%s'. E HDLA-14 MainWin environment is not set up. E HDLA-15 Undefined Synopsys root directory. E HDLA-16 '%s' is not a directory. E HDLA-17 Can't read '%s'. W HDLA-18 Register or instantiated cell '%s' is missing in the mapped design %s. W HDLA-19 Pin '%s' does not exist on the instantiated mapped design %s. W HDLA-20 Pin '%s' does not exist on the instantiated library cell %s. E HDLA-21 Design '%s' appears multiple times in a hierarchy\n\ \tor in more than one hierarchy. W HDLA-22 Instantiated design '%s' of cell '%s' is empty. W HDLA-23 %s is out of date with respect to %s. W HDLA-24 Logic Inspector : %s I HDLA-25 Sorry: no link to help for that item. I HDLA-26 The selected object can not be linked to the design. Try selecting an output port or assignment statement. I HDLA-27 The selected object is not driven by boolean logic. This may be because Logic Inspector does not search through hierarchy boundaries, registers or designWare parts. Try selecting an output port or assignment statement. I HDLA-28 Unable to link back to the selected object. Try a lower reduction effort. I HDLA-29 No Design Data E HDLA-30 Please enter a value to search for. I HDLA-31 The string '%s' was not found. E HDLA-32 The GTECH design doesn't cover all of the constructs in\n\ %s.\n The GTECH design file(s) may be out of sync with respect to the HDL \ source, .bi, and .id files. Displayed results are probably wrong. E HDLA-33 Source file out of sync with GTECH design!\n %s\n\ probably was changed since the GTECH design was generated. E HDLA-34 Couldn't read HDL source file:\n %s\n E HDLA-35 Couldn't read .bi file:\n %s\n E HDLA-36 The data in .bi file:\n \ %s\n \ is not consistent with the text in HDL source file:\n \ %s.\n \ The HDL source file may have been changed since \ the .bi file was created. I HDLA-37 Stopped search after finding %d occurrence(s) \ of '%s'. Search again from a different starting location to find any additional occurrences. I HDLA-38 Found %d occurrence(s) of '%s'. I HDLA-39 Unable to find a path to or through the\ selected point. E HDLA-40 The selected object is not a design, cell, pin or port. E HDLA-41 No Path Displayed. E HDLA-42 Unable to map the start and end points\ of the current path to equivalent objects in the GTECH design. I HDLA-43 db file not loaded. E HDLA-44 Not available in this mode. E HDLA-45 Project variable %s not set. E HDLA-46 Help error: %s E HDLA-47 Could not open help context map file. I HDLA-48 Mapped domain of design '%s' is not loaded. W HDLA-49 '%s' is not a directory. W HDLA-50 Command line option '%s' is not unique. Possible completions are { %s }. W HDLA-51 The '%s' command is not supported in ra_shell. I HDLA-52 Couldn't find a path to or through the\ selected point. E HDLA-53 %s is not the name of a valid host. E HDLA-54 Project variable '%s' is not one of the following valid values : %s. E HDLA-55 Could not invoke %s on %s. W HDLA-56 Could not find or execute %s. E HDLA-57 Load Design failed. See error messages. E HDLA-58 Estimator terminated due to a fatal error. E HDLA-59 Estimator terminated due to an error. No Estimator\ results are available. I HDLA-60 Reload not needed. E HDLA-61 Unable to load the Estimated design. I HDLA-62 Estimator not enabled.\n \ \n\ To enable, ensure that an Estimator license is available and reinvoke \ RTL Analyzer with the -estimate command line option or \ with project variable enable_estimation set to TRUE. E HDLA-63 Could not change working directory to\n\ %s W HDLA-64 %s is not a valid command line option. W HDLA-65 Design %s is empty. It will be treated as an unresolved reference during link. W HDLA-66 %s was removed in version %s. W HDLA-67 %s will be removed in version %s. W HDLA-68 %s was made obsolete in version %s. Please use %s. W HDLA-69 %s will be obsolete in version %s. Please use %s. E HDLA-70 Build GTECH terminated due to a fatal error. E HDLA-71 Build GTECH terminated due to an error.\ No Build GTECH results are available. E HDLA-72 Unable to load the built GTECH design. W HDLA-73 Directory '%s' is not writable. E HDLA-74 The current path is not in the mapped design. E HDLA-75 Unable to correlate the path in the mapped design\ to a corresponding path in the GTECH design. W HDLA-76 %s is not a valid RTL Analyzer or BCView variable. W HDLA-77 %s are incompatable variables. Choosing '%s'. E HDLA-78 Design '%s' contains multiple instances. \ Please use the 'set_dont_touch' or 'uniquify' dc_shell commands to resolve this problem. W HDLA-79 No combinational loop found in circuit. W HDLA-80 Combinational loop found in circuit. Use "Data->Combinational Loop" in Path Browser to display the loop. W HDLA-81 Could not change directory to '%s' W HDLA-82 The command '%s" has been unaliased. E HDLA-83 Files '%s' and '%s' have the same basename. W HDLA-84 Rebuild design '%s' to obtain enhanced HDL tracing information. This design was built by Synopsys release '%s'. E HDLA-85 Dependency loop involving files '%s' and '%s' and the \ definition of '%s' detected. E HDLA-86 Parsing of '%s' failed with the following message: '%s'. E HDLA-87 Dependency loop involving the design '%s' detected. W HDLA-88 The design files define two differnt modules ('%s' and '%s') with \ the same name but only different spelling. W HDLA-89 Calculation of HDL tracing information has been disabled. W HDLA-90 The design %s does not have tracing information linking it to its HDL source. It might have not been processed with bc_enable_analysis_info set to true. I HDLA-91 You invoked this tool from Design Compiler or \ Design Analyzer. Please re-analyze and re-elaborate your design there \ and then reload it using the items in the File menu of HDL Browser. I HDLA-92 bc_view launched successfully with process-id %s. Please refer to the log\n\ \tin the xterm window titled 'bc_view' for further details. I HDLA-93 Reload done successfully in the existing bc_view with process-id %s. \n\ \tPlease refer to the log in the xterm window titled 'bc_view' for further details. W HDLA-94 The design '%s' is not in a stage which can be \ analyzed with bc_view.\n\ \tPlease make sure, that it is analyzed, and either checked or scheduled\n\ \twith variable '%s' set to 'true'. W HDLOUT-1 Expect to see the member name but found %s. E HLS-1 invokation '%s' of function '%s'\n\ \tconstrains the function input '%s' to be smaller\n\ \tthan its default. This is not currently\n\ \tsupported when elaborating for scheduling. E HLS-2 The task '%s' on line %d contains\n\ \tan inout parameter. This is not currently supported\n\ \twhen the task is being preserved using the\n\ \tpreserve_function pseudo-comment.\n E HLS-3 The call to procedure '%s' on line %d\n,\ \tcontains a complicated expression specified for parameter '%s'.\n\ \tThis is not currently supported when the procedure\n\ \tis being preserved using the preserve_function pragma\n\ \tand when the parameter is an out or inout parameter. E HLS-4 Could not link call to function '%s' at line %d.\n\ \tCould be a type or parameter mis-match.\n E HLS-5 No suitable process for HLS E HLS-6 '%s' is not a valid %s. Valid options are\n\ \t%s E HLS-7 Negative HLS timing constraint E HLS-8 Unrecognized HLS datapath topology identifier E HLS-9 No schedule data available E HLS-10 No scheduled process E HLS-11 Timing constraint across hierarchy E HLS-12 Timing constraint across loop(s) W HLS-13 The loop at line %d in file '%s'\n\tis not needed, so it was deleted. E HLS-14 non-block common schedule E HLS-15 Chained unrelated ops E HLS-16 inconsistent clock net ID E HLS-17 No clock exists W HLS-18 no reset net E HLS-19 non-unique path between locked operations E HLS-20 Indeterminate path length E HLS-21 Lock across lexical scopes E HLS-22 Lock with nonunique path source E HLS-23 Overconstrained timing. E HLS-24 The named reset net does not exist E HLS-25 Could not find an architecture for entity '%s'. E HLS-26 You specified variable '%s' as being mapped to a memory\n\tbut the variable was never used. E HLS-27 The signal or port '%s' was mapped to a memory.\n\tOnly variables can be mapped to a memory. W HLS-28 The variable '%s' was specified multiple times\n\ton the resource '%s'. E HLS-29 The variable '%s' was mapped to a memory, but its type\n\tis not an array type. E HLS-30 Binding %s of operator %s for processor %s (instance %s) not found E HLS-31 Illegal use of variable '%s' in function '%s'.\ Memory slices are not supported. E HLS-32 Illegal use of variable '%s' in design '%s'.\ Memory assignments without indexing are not supported. E HLS-33 Unanalyzable, unsatisfiable timing constraints. I HLS-34 The output of preserved function %s at line %d \n\ \thas type[%d:0]. W HLS-35 Unrolling the loop results in a large number of operations,\n\ \tthis may increase search space and slow down run time%s E HLS-37 No time to evaluate condition E HLS-38 chained loop begins (fixed i/o timing) I HLS-39 All wait statements are followed by an exit.\n\tA global synchronous reset with %s polarity has been inferred for %s. I HLS-40 All clock transitions are followed by a disable statement.\n\tA global synchronous reset with %s polarity has been inferred for %s. E HLS-41 Port '%s' was assigned to using a non-RTL\n\ \tassignment at line %d. Use the RTL assignment operator '<=' for\n\ \tassignments to ports. E HLS-42 The exit statement on line %d in file\n\t%s is illegal.\n\tOnly global reset exits are allowed to\n\tcross loop boundaries. E HLS-43 A write operation at the end of '%s'\n\t(%s) conflicts with the I/O at\n\tthe beginning of the loop (%s).\n\tWhen running in super state mode, please insert a wait statement\n\tafter the last write in the loop. E HLS-44 The write operation '%s' conflicts with\n\tI/O at the beginning of '%s'\n\t(%s).\n\tWhen running in super state mode, please make sure that the I/O is\n\tbroken by a clock boundary (e.g. just before the loop). E HLS-45 The write operation '%s' before the loop\n\t'%s' conflicts with I/O that occurs\n\tafter the loop (%s). E HLS-46 Write operations occur inside '%s'\n\tjust before an exit (%s)\n\tthat conflict with I/O that happens after\n\tthe loop (%s). E HLS-47 The design contains parallel paths where one path is broken\n\tby clock boundaries, and another path is not.\n\tThis is not allowed in super-state mode.\n\tThe paths start from the if/case statement on\n\tline%s in file %s.\n\tA wait statement is located on line %d in file %s. E HLS-48 Missing clocks in design. E HLS-49 No license for behavioral synthesis. W HLS-50 Reset declarations of user and HDL clash: non-equivalent simulation may result. E HLS-51 Unsatisfiable Timing Constraints E HLS-52 Fixed IO schedule is unsatisfiable E HLS-53 Error in building synthetic operators. E HLS-54 Clock sense is incompatible with HDL text. E HLS-55 At line %d, a clock event is being checked using an 'if'\n\tstatement. Checking for clock edges using if statements is not\n\tsupported when elaborating for scheduling. Please use wait\n\tstatements instead. E HLS-56 The always block at line %d checks a clock edge in its\n\ttiming control. When elaborating a design for scheduling, you\n\tare not allowed to check clock edges in the timing control of\n\talways blocks. Instead, clock edges should be checked for in\n\tthe body of the block. E HLS-57 When elaborating for scheduling, instantiated components\n\tare not supported. An instantiated component was found on line %d\n\tin file '%s' E HLS-58 When elaborating a design for scheduling, there only one\n\tblock is allowed. The design '%s' contains blocks at\n\tlines %d and %d. E HLS-59 The block at line %d has multiple clocks (%s and %s).\n\tMultiple clocks are not supported when elaborating\n\tfor scheduling. E HLS-60 When elaborating for scheduling, clocks must be\n\tsingle-bit ports. At line %d, variable %s\n\tis used as a clock. E HLS-61 When elaborating for scheduling, clocks must be\n\tsingle-bug ports. The multi-bit port '%s' was used\n\tin design '%s'. E HLS-62 The wait statement at line %d is not supported when\n\telaborating for scheduling. E HLS-63 The port '%s' at line %d in design '%s' is an inout port.\n\tInout ports are not supported when elaborating for scheduling. E HLS-64 The edge specification used on line %d is not supported\n\twhen elaborating for scheduling. E HLS-65 The variables that are mapped onto memory '%s' contain\n\tindices that overlap. Currently, variable indices are not allowed\n\tto overlap. E HLS-66 Indexes into array types must be done using an integer\n\tindex. The access to variable '%s' (resource '%s')\n\tat line %d is not an integer. E HLS-67 Specified clock period is insufficient. \ \t\n Available clock period(%.1f) = specified clock period(%.1f) - margin(%.1f). E HLS-68 Scheduled designs must have exactly one clock signal.\n\t%d were found. E HLS-69 Failed to Find a Legal Schedule E HLS-70 The process at line %d is inside of a generate statement.\n\tThis is not allowed when elaborating for scheduling. E HLS-71 The design has already been scheduled. E HLS-72 The design has no schedule report information. E HLS-78 The requested FSM table file cannot be opened. E HLS-79 Internal error: no next state. E HLS-80 Cannot open schedule report file E HLS-81 Current design is not for HLS E HLS-82 The reg '%s' is driven in block '%s'\n\tand in block '%s'. Currently, when elaborating for\n\tscheduling, a reg may only be driven in a single block. E HLS-83 The signal '%s' is driven in process '%s'\n\tand in process '%s'. Currently, when elaborating for\n\tscheduling, a signal may only be driven in a single process. W HLS-84 No area information for operation %s. W HLS-85 Unknown annotation style. E HLS-86 Operator name '%s' not found in Synthetic Libraries E HLS-87 No schedulable process E HLS-88 Bad edge constraint E HLS-89 Bad hierarchy E HLS-90 No load enable register in the standard synthetic library. W HLS-91 Inconsistent pipelined loop (simulation may not match) E HLS-92 No reset signal polarity E HLS-93 No ending endpoint for timing constraint E HLS-94 No beginning endpoint for timing constraint E HLS-95 Multiple conflicting constraint endpoints E HLS-96 No target library W HLS-97 The delay specified on the write to signal '%s'\n\ton line %d is %d which is not an exact multiple\n\tof the cycle time %d.\n\t%d cycles will be used for the delay. E HLS-98 The delay on the write to signal '%s' at line %d\n\tcauses the assignment to be pushed outside\n\tof the enclosing loop. In order for synthesis to match simulation,\n\tthis requires loop pipelining. However, the enclosing loop\n\tcontains exits, and loop pipelining is not currently allowed\n\tin loops with exits. E HLS-99 The delay on the write to signal '%s' at line %d\n\tcauses the assignment to be pushed outside\n\tof the enclosing block In order for synthesis to match simulation,\n\tthis requires loop pipelining. However, the enclosing block\n\tis not a loop so no loop pipelining can occur. I HLS-100 The delay on the write to signal '%s' at line %d\n\tcauses the assignment to be pushed outside of the\n\tenclosing block In order for synthesis to match simulation,\n\tthis requires loop pipelining. The loop will be pipelined with\n\tan initiation interval of %d and a latency of %d. W HLS-101 The %s is delayed by %d cycles. However, delayed\n\tassignments are only supported for fixed-I/O mode.\n\tThe delay will be ignored. E HLS-102 Object to be extruded is not a cell E HLS-103 Must have a Design Compiler Expert license to compile a design\n\tfor behavioral synthesis. I HLS-104 Set loop '%s' to have initiation interval of %d cycles and latency of %d cycles. E HLS-105 Loop '%s' cannot be set to latency of %d cycles because\n\tits member node %s is fixed at %d cycles after the loop begins. E HLS-106 Loop '%s' cannot be loop-pipelined because it contains exits E HLS-107 Loop '%s' cannot be set to initiation interval of %d cycles and latency of %d cycles because %d is not an even multiple of %d E HLS-108 Loop '%s' cannot be loop pipelined because it contains nested loop '%s' W HLS-109 Delayed assignments require the transport keyword\n\tin order for synthesis to match simulation.\n\tThe transport keyword is missing on line %d\n\tin file %s. W HLS-110 The loop '%s' was specified multiple times as\n\tdont_unroll. W HLS-111 A dont_unroll attribute was specified for a loop\n\tnamed '%s', but the loop could not be found. E HLS-112 A reset has already been inferred from the HDL by elaborate E HLS-113 Reset signal polarity clash E HLS-114 Inconsistent reset signal polarity E HLS-115 Either true or false E HLS-116 Invalid i/o mode flag I HLS-117 Design has already been timed. W HLS-118 for loop on line %d uses the iterator '%s'\n\ \tthat is larger than necessary to cover the range of the loop.\n\ \t'%s' is defined on line %d with a bit-width of %d. The range of\n\ \tthe loop is %d to %d which only requires the iterator to have a\n\ \tbit-width of %d. This will create inefficient logic if the for\n\ \tloop is not unrolled when elaborating for Behavioral Compiler. W HLS-119 The iterator '%s' is used in the for loops\n\ \ton lines %s that are not being unrolled.\n\ \tThe bit-widths required by the loops (%s)\n\ \tare different, and it might be more efficient to declare\n\ \tseparate iteration variables for each for loop. E HLS-120 The for loop on line %d uses the iterator '%s',\n\ \t which is too small to cover the range of the loop.\n\ \t'%s' is defined on line %d with a bit width of %d.\n\ \tThe range of the loop is %d to %d, which requires the\n\ \titerator to have a bit width of at least %d. E HLS-121 Could not write data file W HLS-122 License cannot be recovered E HLS-123 The memory '%s' is being passed in as an argument to\n\ \troutine '%s' at line %d. This is not allowed when elaborating\n\ \tfor scheduling. W HLS-124 The operator '%s' and the module '%s'\n\ \tare connected by more than one sequential binding,\n\ \tone of which is the binding '%s'. W HLS-125 The check_bindings command cannot verify the\n\ \tsequential binding '%s' of module '%s'\n W HLS-126 Cannot merge output registers of multi-cycle operations. W HLS-127 Edge %s may be driven by operations of different cycle delays W HLS-128 Loop %s has no exit\n\ \tOperations and/or transfers following it are dead code\n\ \tand will be pruned. W HLS-129 Post-scheduling uniquify failed\n E HLS-130 The process%s at line %d does not contain any wait\n\ \tstatements. Behavioral Compiler requires that each process being\n\ \telaborated for scheduling have at least one wait statement. This\n\ \tis necessary to determine the clock and clock edge to use for\n\ \tthe process. E HLS-131 The always block%s at line %d does not contain\n\ \tany posedge or negedge statements. Behavioral Compiler requires\n\ \tthat each always block being elaborated for scheduling have\n\ \tat least one edge statement. This is necessary to determine\n\ \tthe clock and clock edge to use for the block. E HLS-132 The process%s at line %d contains waits that check\n\ \tboth positive edges and negative edges of clocks. The wait at\n\ \tline %d checks the positive edge of the clock, and the wait\n\ \tat line %d checks the negative edge. Checking both edges is not\n\ \tsupported. E HLS-133 The always block%s at line %d contains\n\ \tboth posedge and negedge declarations. There is a posedge\n\ \tdeclaration at line %d and a negedge declaration at line %d.\n\ \tIt is illegal to check both edges of a clock within a single\n\ \talways block. E HLS-134 Design has not been timed for Behavioral Compiler E HLS-135 Clock period is too small for operation '%s'\n which requires a minimum clock period of '%f'. I HLS-136 The clock transitions being checked at lines\n\ \t%d and %d are different. No synchronous reset will be inferred\n\ \tfor the %s at line %d. I HLS-137 The clock transition at line %d is not followed\n\ \tby an if statement. No synchronous reset will be inferred\n\ \tfor the %s at line %d. I HLS-138 The clock transition at line %d is\n\ \tfollowed by an if statement, but the contents of the if block\n\ \tis not a single exit statement. In order to infer a synchronous\n\ \treset, the if block can only contain a single statement that\n\ \texits from the block. No synchronous reset will be inferred for\n\ \tthe %s at line %d. I HLS-139 The clock transition at line %d is followed by\n\ \tan if statement with a single exit statement, but the exit statement\n\ \tdoes not reset the entire block (process in VHDL, always block in\n\ \tverilog). No synchronous reset will be inferred for the\n\ \t%s at line %d. I HLS-140 The clock transitions at lines %d and %d are\n\ \tboth followed by a conditional that exits the main block. However,\n\ \tthe conditions for the two exits are different. No synchronous reset\n\ \twill be inferred for the %s at line %d. E HLS-141 The chain_operations and dont_chain_operations commands require two or more operations as arguments. I HLS-142 The clock transition at line %d is\n\ \tfollowed by an if statement, but the if statement has multiple\n\ \tbranches. In order to infer a synchronous reset, the if statement\n\ \tcan only contain a single branch with a statement that\n\ \texits from the block. No synchronous reset will be inferred for\n\ \tthe %s at line %d. E HLS-143 The variable '%s' was attributed as being a %s\n\ \tin resource %s on line %d. However, the variable is not defined\n\ \tin the process at line %d. If it is not a shared memory the variable\n\ \tshould be defined, and if it is a shared memory it should set\n\ \t"bc_allow_shared_memories = true". E HLS-144 The variable '%s' was attributed as being a %s\n\ \tin resource %s on line %d. However, the variable is not defined\n\ \tin the scope of the always block at line %d. E HLS-145 Multiple operations have been defined as an endpoint for a timing offset E HLS-146 The for loop at line %d contains the loop\n\ \tat line %d and the for loop is being unrolled. For loops are not\n\ \tallowed to contain other loops if they are being unrolled. E HLS-147 The command '%s' is only valid on designs that have\n\ \tbeen elaborated for scheduling, but have not been scheduled yet.\n\ \tThe design '%s' is not valid. E HLS-148 The command '%s' is not valid on designs that have\n\ \tbeen elaborated for scheduling and have not been scheduled yet.\n\ \tThe design '%s' is not valid. E HLS-149 Found scheduling template containing resource contention. E HLS-150 Loop '%s' cannot be loop-pipelined because\n\ \tthe branches of the conditional at line %s are unbalanced. E HLS-151 You cannot chain fewer than two operations I HLS-152 Scheduling '%s' ... I HLS-153 Allocating hardware for '%s' ... E HLS-154 Variable '%s' is not initialized for operation '%s' W HLS-155 Variable '%s' is not initialized I HLS-156 Operation %s is activated by gate %s W HLS-157 Ignoring multi-cycle delay for operation '%s' W HLS-158 Logic group '%s' has propagation delay of '%f',\n\ which is longer than the clock period of '%f' E HLS-159 Failed to schedule pipelined loop '%s' \n\ under initiation interval of %d and loop delay of %d E HLS-160 Detected Inconsistent Sequential Bindings.\n\ In module '%s', for operator '%s',\n\ Binding '%s' has %d states, but binding '%s' has %d states E HLS-161 Detected Inconsistent Sequential Bindings.\n\ In module '%s', for operator '%s',\n\ State '%d' of binding '%s' uses %d resources,\n\ but state '%d' of binding '%s' uses %d resources E HLS-162 Detected Inconsistent Sequential Bindings.\n\ In module '%s', for operator '%s',\n\ State '%d' of binding '%s' uses resource '%s',\n\ but state '%d' of binding '%s' does not use that resource E HLS-163 Inconsistent FSM registration flags. W HLS-164 one of the allowed flags must be used. E HLS-165 The %s '%s' is accessed globally in subprogram '%s'\n\ \tat line %d in file %s.\n\ \tThis is not supported when elaborating for scheduling. W HLS-166 The subprogram '%s' contains a %s statement\n\ \tat line %d in file %s.\n\ \tNo synchronous reset will be inferred. E HLS-167 The subprogram '%s' at line %d\n\ \tin file '%s'\n\ \tcontains loops. This is not supported when elaborating\n\ \tfor scheduling. E HLS-168 Cannot find legal binding for %s of operator type %s E HLS-169 It is illegal to use a 'wire' variable inside of an\n\ \talways block. The wire variable '%s' is used as an\n\ \titerator in a for loop at line %d\n\ \tin file %s. E HLS-170 %s constraint involving '%s' and '%s' is illegal\n\ because it crosses levels in the design hierarchy. E HLS-171 Failed to schedule loop named '%s'\n E HLS-172 You cannot specify common resource for fewer than two operations E HLS-173 You must specify a unique process W HLS-174 Conditional action on reset transition. W HLS-175 Read operation %s for signal %s is redundant because\n\ \tthe value is not used. E HLS-176 Write operation %s for signal %s is redundant because\n\ \tit is in dead code or the value has not been initialized. W HLS-177 Operation %s outputs are not used. E HLS-178 Cannot schedule operations %s and %s on a common resource. E HLS-179 The always block at line %d contains references to\n\ \tthe variable '%s'. This variable is defined as a\n\ \tBehavioral Compiler memory in the always block at line %d.\n\ \tSee Behavioral Compiler User Guide to find out how to share\n\ \tmemories between blocks. E HLS-180 The for loop on line %d uses the iterator '%s'\n\ \tOn line %d, the iterator '%s' is redefined.\n\ \tThis is currently not supported when elaborating\n\ \tfor scheduling. E HLS-181 Cannot pipeline loop '%s' with initiation interval %d. A path has a timing path whose length is too long. E HLS-182 Loop '%s' cannot be loop-pipelined with initiation interval %d\n\ \tbecause '%s' will occur after '%s' of the next iteration\n\ \tThere is a minimum timing constraint of %d cycles from\n\ \t%s to %s. Try changing initiation interval to %d. E HLS-183 Loop '%s' cannot be loop-pipelined with initiation interval %d\n\ \tbecause memory read/write on %s will be permuted. '%s' may occur at\n\ \tthe same time or after '%s' of the next iteration since there\n\ \tis a minimum timing constraint of %d cycles from\n\ \t%s to %s. Try changing initiation interval to %d.\n E HLS-184 Loop '%s' cannot be loop-pipelined with initiation interval %d\n\ \tbecause operation '%s' has a delay of %d cycles.\n\ \tTry changing initiation interval to %d.\n E HLS-185 Loop '%s' cannot be loop-pipelined with initiation interval %d\n\ \tbecause operation '%s' uses sequential binding '%s' where\n\ \tstate %d and %d\n both use internal resource '%s'.\n\ \tTry increasing initiation interval.\n E HLS-186 Cannot pipeline loop '%s' with initiation interval %d.\ A path has a minimum length that is too long. E HLS-187 Cannot pipeline loop '%s' with initiation interval %d. A path with fixed nodes has a minimum length that is too long. E HLS-188 Unable to find scheduling data in FSM-style format. I HLS-189 Register '%s' will be inferred as multibit module. I HLS-191 Binding '%s' to '%s' for timing. I HLS-192 Selected '%s' to implement '%s'. I HLS-193 Using wordlevel timing to calculate chaining of '%s'. E HLS-195 Loop %s cannot be loop-pipelined with initiation interval %d\n\ because the memory operation '%s' must be no later than %d\n\ cycles after the operation '%s'. This implies a minimum delay of %d\n\ cycles from %s to %s. However, this violates the timing constraint of\n\ %d cycles from %s to %s. E HLS-196 Loop %s cannot be loop-pipelined with initiation interval %d\n\ because the memory operation '%s' must be no later than %d cycles after the operation '%s'.\n\ This implies a minimum delay of %d cycles from %s to %s\n\ However, this is unsatisfiable because %s\n\ is fixed at cycle %d, and %s is fixed at cycle %d. E HLS-197 Loop %s cannot be loop-pipelined with initiation interval %d\n\ because the signal read/write operation '%s' must be no later than %d\n\ cycles after '%s'. This implies a minimum delay of %d\n\ cycles from %s to %s. However, this violates the timing constraint of\n\ %d cycles from %s to %s. E HLS-198 Loop %s cannot be loop-pipelined with initiation interval %d\n\ because the signal read/write operation '%s' must be no later than %d cycles \n\ after '%s'. This implies a minimum delay of %d \n\ cycles from %s to %s. However, this is unsatisfiable because %s\n\ is fixed at cycle %d, and %s is fixed at cycle %d. E HLS-199 Speculative execution must be either true or false E HLS-200 State chaining must be either true or false E HLS-201 BC FSM coding style is not in the valid set E HLS-202 FSM compiler and state transition chaining are incompatible E HLS-203 Unable to create attributes for BC E HLS-204 No reference for memory cell E HLS-205 Cannot use the memory master as a cell E HLS-206 Not a memory cell E HLS-207 Fixed schedule (%s at cstep %d) produces a state transition cycle\n at loop begin named %s\n E HLS-208 The named stall pin does not exist. W HLS-209 There exist timing constraint between this two operations. New timging constraint will be applied. I HLS-210 To enable this feature, you may also use a Behavioral Compiler\n\ \tlicense (BC-VHDL, BC-HDL). E HLS-211 Inappropriate reporting data for condition reporting E HLS-212 Compilation of user defined Design Ware parts failed. E HLS-213 Unconditional loop exit at line %s is not allowed. I HLS-214 Determine default margin. I HLS-215 Delete variable '%s' in process '%s'. I HLS-216 Set cycle margin to %.2f . E HLS-217 Need a Behavioral Compiler license to enable this feature. E HLS-218 All Behavioral Compiler licenses are already in use. W HLS-219 The command '%s' will be obsoleted in \n\tthe next release. \n\tPlease use the command '%s' instead. E HLS-220 The command 'dont_chain_operations' has been obsoleted.\n\tPlease use the command 'set_min_cycles' instead. E HLS-221 bc_allocation_effort must be one of 'default', 'zero', 'low', 'medium', 'high'. E HLS-222 bc_bit_level_muxing must be either 'true' or 'false'. E HLS-223 clock signal '%s' drives multi-cycle operation '%s'. E HLS-224 Error: connection '%s' on function '%s' is\n\ \ta signal. This is not currently supported when\n\ \telaborating for scheduling. E HLS-225 No address port of shared memory is specified in process '%s';\n\ \tAt least one port of the shared memory is specified. E HLS-226 Syntax error in address port specification '%s' of shared memory in process '%s'. E HLS-227 The specified address port '%s' of shared memory '%s' in process '%s' is not found. E HLS-228 Unable to create attributes for BC E HLS-229 Loop '%s' cannot be pipelined with initiation interval of 1\n\tbecause of the registered controller outputs. E HLS-230 Unrecoverd error has occured. This error might be cured via using a different type of fsm compiler. Try set\ "bc_use_fsm_compiler = false" in dc_shell and rerun. E HLS-231 The subprogram '%s' contains a %s statement\n\ \twhich fails to preserve the function. I HLS-232 Checking '%s' ... E HLS-233 The design contains parallel paths where one path is broken\n\tby clock boundaries, and another path is not.\n\tThis is not allowed in cycle-fixed mode.\n\tThe paths start from the if/case statement on\n\tline%s in file %s.\n\tA wait statement is located on line %d in file %s. W HLS-234 '%s' can not chain with '%s', chain_operations will be ignored. E HLS-235 The output of operation '%s', which has the\n\ \tattribute "carry_port_name", is connected to another operation.\n\ \tThis violates the rule that all outputs of the operation must be\n\ \tconnected to an output port on the design. E HLS-236 The output of operation '%s', which has the attribute\n\ \t"carry_port_name", has multiple fan-out. This violates the rule that\n\ \tall outputs of the operation must be connected to the same port\n\ \ton the design. E HLS-237 The operation '%s' has a "carry_port_name" attribute\n\ \treferencing port '%s'. This port is not driven by logic zero which\n\ \tis required in order to use the "carry_port_name" attribute. E HLS-238 Could not find operations CSA_UNS_OP and CSA_TC_OP.\n\ \tThis is probably because the synthetic library dw01.sldb is missing from\n\ \tthe synthetic_library variable specification. E HLS-239 Could not find operations MULT2_UNS_OP and MULT2_TC_OP.\n\ \tThis is probably because the synthetic library dw02.sldb is missing from\n\ \tthe synthetic_library variable specification. E HLS-240 Cell '%s' is part of multiple resource constraints. E HLS-241 Forcing the operations '%s' to share resources created a false combinational loop. E HLS-242 Forcing the operations '%s' and '%s' to share resources would result in a false path that is longer than the cycle time. W HLS-243 Forcing the operations '%s' and '%s' to share resources will result in a false path that is longer than the cycle time. E HLS-244 The option 'force_sharing' can only be used in combination with 'max_count'. E HLS-245 The 'allow_false_path' option can only be used in\ \tcombination with the 'force_sharing' option. E HLS-246 'min_count' must be less or equal than 'max_count'. E HLS-247 Can not apply set_common_resource to memory access '%s'. E HLS-248 Variable power_gated_clock_logic has incorrect value. E HLS-249 Variable power_test_enable has incorrect value. E HLS-250 Variable power_test_obs_logic has incorrect value. E HLS-251 Variable power_test_obs_logic_depth has incorrect value. E HLS-252 Variable power_reg_size_threshold has incorrect value. E HLS-253 Reg '%s' was assigned in a blocking assignment in\n\ \tother process but was read using the continue assignment at line '%d'. I HLS-254 Operations '%s' and '%s' were not merged\n\ \tinto CSA operations because of upper-bit truncation between them. I HLS-255 Operations '%s' and '%s' were not merged\n\ \tinto CSA operations because of upper-bit or lower-bit truncation\n\ \tbetween them. I HLS-256 Operation '%s' has multiple fan-out. It was duplicated\n\ \tcreating upto %d extra operation(s) to allow the CSA transformation to be\n\ \tperformed.%s I HLS-257 Operation '%s' has multiple fan-out and\n\ \twas not duplicated. See the man page for transform_csa to find out how\n\ \tto duplicate the operation to reduce delay at the expense of extra\n\ \tarea.%s E HLS-258 Unable to create attributes for BC W HLS-259 Command "transform_csa" cannot be applied to the scheduled\n\ \tdesign '%s'. W HLS-260 The timing of design '%s' was invalidated by "transform_csa". W HLS-261 Operation '%s' has both of the attributes "transform_csa" and\n\ \t"dont_transform_csa" with "true" values. The attribute "dont_tranaform_csa" is not honored. W HLS-262 Operation '%s' has both of the attributes "duplicate_csa" and\n\ \t"dont_duplicate_csa" with "true" values. The attribute "dont_tranaform_csa" is not honored. E HLS-263 bc_schedule_branches_asap must be either 'true' or 'false'. E HLS-264 %s must be either 'true' or 'false'. W HLS-265 There exist a path from '%s' to '%s' having no timing information. I HLS-266 Memory instance '%s' was declared as a shared memory and\n\ \twas used by processes %s. I HLS-267 Memory instance '%s' was declared as a shared memory, but\n\ \twas used by one process '%s'. W HLS-268 Ports of memory '%s' are not fully utilized.\n\ \tMapping of bindings %s requires\n\ \t%d %s resources, but only %d resources are available. E HLS-269 Detected an inconsisteny among %s bindings in memory module '%s':\n\ \tFor Bindings '%s' and '%s' are pipelined, but their\n\ \tinitiation intervals are different. E HLS-270 The node '%s' is part of conflicting timing constraints. E HLS-271 Unable to create attributes for BC W HLS-272 Detected an inconsistency of bindings in memory '%s'.\n\ \tBinding '%s' is nonpipelined and binding '%s'\n\ \tis pipelined. Using this memory can cause a suboptimal schedule. E HLS-273 Loop has exits but loop continue %s does not have any condition. E HLS-274 The memory resource '%s' at line '%d' is not supported for multi-processes. E HLS-275 Memory module '%s' cannot be found in the synthetic libraries. E HLS-276 Command "bc_report_memories" cannot be applied to design\n\ \t'%s' which was not elaborated for behavioral synthesis. E HLS-277 Command "bc_report_memories" cannot be applied to the scheduled\n\ \tdesign '%s'. E HLS-278 Read memory access of '%s' in process '%s'\n\ \tcannot be performed because module '%s' does not have\n\ \teither a read only or read/write port. E HLS-279 Write memory access of '%s' in process '%s'\n\ \tcannot be performed because module '%s' does not have\n\ \teither a write only or read/write port. W HLS-280 User Constraint was given to ignore memory precendences\n\ \tbetween '%s' and '%s' in process '%s',\n\ \tin which their accesses conflict. W HLS-281 User Constraint was given to ignore memory loop precendences\n\ \tbetween '%s' and '%s' in process '%s',\n\ \tin which their accesses across iterations of loop conflict. W HLS-282 The node '%s references design '%s' \n\ \twhich does not drive output '%s'.\n\ \tPlease check the state binding in your .sl file. E HLS-283 Because options -dont_split, -round_bits #, and\n\ \t-truncate_bits # conflict with each other, choose only one.\n\ \tSee the man page for transform_csa to find out how to control operation\n\ \tspliting. E HLS-284 The variable bc_allocation_effort is no longer \n\ \tsupported. Please use the option -allocation_effort for the schedule command. I HLS-285 Operations '%s' and '%s' were not merged into CSA\n\ \toperations. See the man page for this command to find out how\n\ \tto use distributive rule to decrease delay at the expense of extra\n\ \tarea. I HLS-286 Operations '%s' and '%s' were not merged into\n\ \tCSA operations because '-dont_split' option was asserted. See\n\ \tthe man page for transform_csa to find out how the operations\n\ \tcan be merged by spliting operation. W HLS-287 Designware Foundation license is not avaiable during transform_csa. W HLS-288 Due to the transformation of operations with lower bit rounding,\n\ \tsimulation mismatch can occur. See man pages to find out how simulation\n\ \tmismatch can be avoided on transform_csa. I HLS-289 The direction of port '%s' will be input. W HLS-290 Could not find memory '%s' in synthetic libraries which is\n\ \tto be accessed by '%s' of instance '%s'.\n\ \tThis can cause a fatal error in schedule. I HLS-291 cell '%s' will be chained if possible.\n E HLS-292 You cannot specify a zero delay with the \n\ \tset_memory_output_delay command.\n I HLS-293 the design '%s' has been already timed. \n\ \tThe timing table will be automatically update. E HLS-294 Could not find memory name '%s' in synthetic library.\n E HLS-295 Negative delays are not allowed with the \n\ \tset_memory_output_delay command. E HLS-296 STABLE = TRUE on a memory output port was detected\n\ \tthis is inconsistant with positive internal delays W HLS-297 Due to the pipelining of loop '%s', the unbalanced\n\ \tbranches of the conditional at line %s will get scheduled\n\ \tin the same number of control steps. E HLS-298 bc_force_balanced_branches has an illegal value.\n\ \tPlease use one of never, always, wait_based. I HLS-299 Evaluation of an exit condition of loop '%s' needs\n\ \t%d extra clock cycles after the loop to preserve timing when exiting. E HLS-300 Current design is not defined. E HLS-301 synthetic_library variable is not defined. I HLS-302 Only '-synthetic_libraries' or '-bindings' are applied\n\ \tbecause current design is not defined. I HLS-303 Multi-stage multiplication '%s' is not applicable to transformation. I HLS-304 No addition/subtraction/multiplication tree was found. E HLS-305 Because options '-balance_only' and '-chain_only' are conflict,\n\ \tchoose only one of them. See the man page for transform_csa to\n\ \tfind out the applications. W HLS-306 '-duplicate' option cannot be appiled together with '%s'\n\ \toption. '-duplicate' was ignored. E HLS-307 '%s' is an invalid logic grouping size. Use one of 'zero',\n\ \t'small', 'medium', and 'large'. W HLS-308 Negative value '%d' of option '%s' is not allowed.\n\ \tThe option was ignored. W HLS-309 Memory module '%s' uses binding '%s' which has no\n\ \tstate information. This can cause a fatal error in schedule. I HLS-310 Operations '%s' extended input bit-width %s\n\ \tto generate MULT2 operation without output extension. It increases area,\n\ \tbut can reduce the delay. W HLS-311 memory_address_port attributes were found in processes %s.\n\ \tBut, bc_allow_shared_memories is not set. The memory is assumed to be\n\ \tnon-shared. E HLS-312 Could not find operations MULTP_UNS_OP and MULTP_TC_OP.\n\ \tThis is probably because the synthetic library dw02.sldb is missing from\n\ \tthe synthetic_library variable specification or the dw02.sldb does not contain\n\ \tthe modules.. E HLS-313 Multiple %s bindings were defined in address port '%s' of memory '%s'. E HLS-314 Reset signal came from synthetic operation or sequential operation. E HLS-315 Number of cycles '%d' constrained to graph '%s'\n\ \tby set_cycles command exceeds the minimum number of cycles %d required\n\ \tfor the graph. E HLS-316 Because preserve function '%s' contains %s %s\n\ \tthe function cannot be treated as a designware. See the man page to\n\ \tfind out the usage of preserve function attribute. E HLS-317 Negative delays are not allowed with the \n\ \tset_memory_input_delay command. E HLS-318 You cannot specify a zero delay with the \n\ \tset_memory_input_delay command.\n E HLS-319 Cannot find variable '%s' in design '%s'.\n\ set_exclusive_use will be ignored.\n E HLS-320 Precompiled design '%s' has not been created in the Behavioral Compiler flow. I HLS-321 Writing preserved function '%s' to file '%s'\n\ \tin library '%s' which is mapped to '%s'. W HLS-322 Reading precompiled version of preserved function '%s' from library '%s'. W HLS-323 Cannot find precompiled version of preserved function '%s'\n\ \tin library '%s'. The preserved function will get compiled. W HLS-324 test E HLS-325 Behavioral Compiler does currently not support data\n\ \tdependencies from the inside of a pipelined loop to\n\ \tthe outside of that loop, unless the producer of the\n\ \tdata is scheduled in the initiation interval. I HLS-326 register '%s' has a reset value '%s' E HLS-327 Negative external delays are not allowed with the \n\ \tset_memory_output/input_delay command. I HLS-328 An old delay '%f' has been found on cell '%s' I HLS-329 An old external delay '%f' has been found on cell '%s' E HLS-330 no memory found in synthetic libraries. W HLS-331 no clock has been yet defined on the current design E HLS-332 The total delay '%f' exceeds the clock period '%f' I HLS-333 Please use "bc_clears_all_registers" rather than "reset_clears_all_bc_registers" next time. I HLS-334 Nothing to report for given range in this process. W HLS-335 The dont_unroll loop %s is missing. W HLS-336 Direct reset is turned off because the command control_register -outputs is on. E HLS-337 The command '%s' is only valid on designs that have\n\ \tbeen timed for scheduling, but have not been scheduled yet.\n\ \tThe design '%s' is not valid. E HLS-338 The 'area' option for the schedule command has been renamed in 'extend_latency'. I HLS-339 the design '%s' has been already \n\ \ttimed. W HLS-340 Port '%s' drives node '%s'. E HLS-341 Design %s is already compiled for bc_time_design. E HLS-342 no cluster was found in %s W HLS-343 %s attribute is set true on design %s E HLS-344 Design %s is not a cluster of random logic I HLS-345 The delay on the write to signal '%s' at line %d\n\ \tcauses the assignment to be scheduled %d cycles after the\n\ \tbeginning of the enclosing loop. W HLS-346 The design has a comparison operation on line %d that compares values of type std_logic_vector. This is ambiguous.\ W HLS-347 All dont_care nets will become logic zero nets. E HLS-348 The variable feeding input %s of operation %s is not initialized. E HLS-349 Design %s contains a subdesign %s which does not drive a used output %s W HLS-350 Operation '%s' has been turned into a multicycle operation. I HLS-351 Using precompiled version of preserved\n\ \tfunction '%s' from library '%s'. E HLS-352 The variable %s is no longer supported.\n\ Please use %s instead. E HLS-353 There must be a main (infinite) loop inside \ the reset loop, if you are using the direct reset connection. E HLS-354 You cannot use a rolled loop before the first clock \ statement inside the reset loop block, if you are also using the \ direct reset connection. Add a clock statement before the rolled loop \ inside the reset loop block, or use set_behavioral_reset -fsm. W HLS-355 No signal assignments appear before the first \ clock statement in the reset loop; therefore, the reset signal cannot\ be directly connected to any signals. E HLS-356 You cannot use a reset loop that contains \ a conditional (if) statement before the first clock statement,\ if you are also using the direct reset connection.\ Add a clock statement before the conditional statement inside the reset loop block,\ or use set_behavioral_reset -fsm. I HLS-357 The reset signal will be directly \ connected to the preset or clear pin of registers. I HLS-358 The reset signal will be generated from the FSM. I HLS-359 The reset of the scheduled design has been set to %s. W HLS-360 You have executed set_behavioral_reset without\ arguments; setting all reset options to their default values. I HLS-361 Checking for reset loop coding style will be performed on the reset loop. W HLS-362 Multiple rolled loops appear in the reset loop. E HLS-363 The reset port was not specified either with\ set_behavioral_reset -port or in the HDL description.\ Cannot define reset characteristic. W HLS-365 Multiple clock statements appear in the reset loop. E HLS-366 Input port '%s' is updated inside function '%s'. W HLS-367 The reset of the scheduled design has been changed to %s, overriding the previously specified %s reset. E HLS-368 You cannot specify %s without also specifying %s. E HLS-369 This constraint is illegal because it crosses the subprogram hierarchy. E HLS-370 Failed to rebind multiple sequential bindings. E HLS-371 \ Superstate mode violation detected at loop-continue\n\ of %s E HLS-372 \ Superstate mode violation detected at loop-entry\n\ of %s E HLS-400 Variable '%s' used in preserve_schedule_subprogram '%s'\n \ \twas not defined locally. E HLS-401 not create two preserve (sequential) function with same nane'%s' E HLS-402 illegal memory usage '%s' in the preserve schedule subprogram '%s'. I HLS-403 Operations '%s' and '%s' were not merged\n\ \tinto CSA operations because of the mismatch of pins or nets connected\n\ \tbetween them. E HLS-404 Ignoring execution precedence from '%s' to '%s'.\n\ \tRemoval of Read <-> Write precedences can lead to illegal allocation\n\ \tof memory bindings (ports). Consult your local Behavior Compiler expert\n\ \tfor further information. E HLS-405 It is not recommended to uniquify Behavioral Compiler designs before scheduling. Of course, uniquify can be used for post-scheduled designs. E HLS-406 Not an array cell. E HLS-407 No reference for array cell. E HLS-408 Cannot use the array master as a cell W HLS-409 '-use_bit_adder' option cannot be appiled together with '%s'\n\ \toption. '-use_bit_adder' was ignored. W HLS-410 Preserved function '%s' has use_netlist pragma.\n\ \tThe netlist will be used rather than the cached version in library '%s'. E HLS-411 Variable '%s' is used in preserve_function '%s'\n \ \tbut is not defined locally. W HLS-440 No AND or OR gate in the standard synthetic library. E HLS-483 Loop '%s' cannot be loop pipelined with initiation interval %d\n\ \tbecause array read/write on %s will be permuted. '%s' can occur at\n\ \tthe same time or after '%s' of the next iteration since there\n\ \tis a minimum timing constraint of %d cycles from\n\ \t%s to %s. Try changing initiation interval to %d. E HLS-495 Loop %s cannot be loop pipelined with initiation interval %d\n\ \tbecause the array operation '%s' must be no later than %d\n\ \tcycles after the operation '%s'. This implies a minimum delay of %d\n\ \tcycles from %s to %s. However, this violates the timing constraint of\n\ \t%d cycles from %s to %s. E HLS-496 Loop %s cannot be loop pipelined with initiation interval %d\n\ \tbecause the array operation '%s' must be no later than %d cycles after the operation '%s'.\n\ \tThis implies a minimum delay of %d cycles from %s to %s\n\ \tHowever, this is unsatisfiable because %s\n\ \tis fixed at cycle %d, and %s is fixed at cycle %d. E HLS-497 %s constraint involving non-loop preserve_schedule_subprogram\n\ \t'%s' and a cell which is not in the subprogram is not supported. W HLS-498 Resource '%s' of memory '%s' specified in .sl file\n\ \tnever be maximally utilized. At most %d of the resource can be used\n\ \tin parallel by the port bindings. E HLS-499 All %s licenses are already in use.\n\ \tThe %s command needs such a license. E HLS-500 You need a license for %s \n\ \tto enable the %s command. E HLS-501 Clock was not defined in binding '%s' of memory '%s'. E HLS-502 Address port name was not defined in binding '%s' of memory '%s'. E HLS-503 Multiple clocks were defined in binding '%s' of memory '%s'. E HLS-504 Operation(s) specified in timing constraints command\ are signal probe(s).\ W HLS-505 A timing constraint cannot be set on '%s',\ which is a signal probe. W HLS-506 A timing constraint cannot be set on '%s', which is a signal probe.\ E HLS-507 All operations specified in chain/dont_chain command\ are signal probes.\ W HLS-508 A timing constraint cannot be set on '%s', which is a signal probe.\ E HLS-509 All operations specified in unschedule/preschedule \ command are signal probes.\ E HLS-510 Error in specifying port '%s' of the preserved function at line '%d'. '%s' \ E HLS-511 You cannot specify both "preserved_functions"\ and "-exclude preserved_functions" at the same time. E HLS-512 Invalid argument %s specified for command option \n\ \t -compile_effort. E HLS-513 You have specified two or more options that cannot be used together. W HLS-514 No preserved functions were found in `%s.' W HLS-515 The command `%s' with the '-no_compile' option \ has no effect without also specifying the '-write' option. W HLS-516 Skipping `%s', because a mapped netlist for\n\ \tthis preserved function was detected.\ I HLS-517 Calling `include %s' on preserved function \n\ \t `%s.' E HLS-518 The filename option may not be applied to multiple preserved functions. I HLS-519 Designs will be written to design library `%s.' E HLS-520 You cannot use the -force_recompile and -no_compile\ options together. E HLS-521 You cannot use the '-include_script' option,\ because the preserved function `%s' contains an embedded script. W HLS-522 Existing design for preserved function \ %s will be overwritten.\ I HLS-523 Compiling preserved function `%s' with \n\ \t %s effort. E HLS-524 You cannot use the -netlist_file_name and -return_port\ options if you specify more than one preserved function. E HLS-525 The preserved function `%s' has the same name\ as a synthetic operator in the synthetic library. E HLS-526 After scheduling, you cannot invoke `compile_preserved_functions' \ without using the `-no_compile' option. E HLS-527 The `read_preserved_function_netlist' command \n\ \t cannot be invoked for preserved function `%s' because the \n\ \t `use_netlist' pragma was used in the latter. E HLS-528 Preserved function `%s' specified in the \n\ \t list of preserved functions to be processed or excluded, does not \n\ \t exist in the current top-level design `%s.' E HLS-529 Unable to read netlist file `%s' in the default \n\ \t design library for preserved function `%s.' E HLS-530 Unable to find design `%s' in netlist file '%s'\n\ \tin design_library '%s' for preserved function `%s.' E HLS-531 Unable to read the file `%s' for preserved function `%s'\n\ \tusing design_library `%s' which is mapped to `%s'. I HLS-532 Using the design in netlist `%s' \n\ \t in library `%s' for preserved function `%s.' E HLS-533 Cannot link the external netlist `%s.' E HLS-534 No %s library is set for the current top-level \n\ \t design `%s.' W HLS-535 No link or target library is set for the \n\ \t netlist `%s.' E HLS-536 The library `%s' used by the external netlist \n\ \t `%s' is not used by the current top-level design `%s.' E HLS-537 The external netlist `%s' is %s. \n\ \t It contains a %s `%s.' I HLS-538 Writing preserved function `%s' to file `%s.' I HLS-539 Using the design in netlist `%s' \n\ \t in the default design library for preserved function `%s.' W HLS-540 Cannot specify a return port for preserved \ function `%s', because it has more than one output port. Ignoring\ the specified return port `%s'. I HLS-541 Using port `%s' from netlist `%s' as return \n\ \t port for preserved function `%s.' E HLS-542 Preserved function `%s' could not be compiled \n\ \t using the script `%s.' E HLS-543 The `read_preserved_function_netlist' command \n\ \t cannot be invoked after scheduling. W HLS-544 The `use_netlist' pragma is being phased out,\ and will not be supported after the v2000.05 release. Please use \ `read_preserved_function_netlist' instead. W HLS-545 The variable `%s' \n\ \t is no longer supported. E HLS-546 The options `-cache_preserved_functions' and \n\ \t `-except' are no longer supported in `bc_time_design.' E HLS-547 The options `-use_cached_preserved_functions' and \n\ \t `-recompile' are no longer supported in `bc_time_design.' W HLS-548 The design has a comparison operation that compares values of type std_logic_vector. This is ambiguous. For more specific line information, please re-analyze with "bc_enable_analysis_info = true".\ E HLS-550 Can't find %s port '%s' for design '%s'. E HLS-551 Port '%s' of design '%s' has unsupported type inout. E HLS-552 Port '%s' of design '%s' has unknown type. E HLS-553 You may not specify %s without specifying %s. E HLS-554 %s has to be %s. E HLS-555 Inconsistent stage count for %s'. E HLS-556 Found loop containing cell '%s'. E HLS-557 Inconsistent number of pipeline stages in netlist %s. E HLS-558 Found control register '%s' in netlist '%s'. E HLS-559 The %s '%s' doesn't match name of the\n\ \t%s '%s' defined for netlist '%s'. E HLS-560 Cannot find clock port %s for design %s. E HLS-561 Clock port %s for design %s is not an input port.\ E HLS-562 Cannot find reset port %s for design %s.\ E HLS-563 Reset port %s for design %s is not an input port.\ E HLS-564 You may specify only one of %s.\ W HLS-565 Assuming clock type is positive edge.\ E HLS-566 The pipelining properties of netlist %s have already\n\ \tbeen determined. You may not specify any pipelining options.\ E HLS-567 You specified pipelining options even though netlist\n\ \t%s does not contain any sequential elements.\ W HLS-568 Skipping netlist %s, it already contains sequential elements.\ W HLS-569 No clock period has been specified, pipelining %s\n\ \tfor minimum clock period.\ I HLS-570 Netlist %s is pipelined component with %d stages.\ E HLS-571 No clock port has been specified for sequential netlist %s.\ W HLS-572 The reset synchronicity of sequential component %s is different \ from the one of the design. W HLS-573 The reset polarity of sequential component %s is different \ from the one of the design. W HLS-574 The clock polarity of sequential component %s is different \ from the one of the design. E HLS-575 When selecting any pipelining related option, you\n\ \tmay specify neither 'include_script' nor 'no_compile'. E HLS-576 The filename may not be hierarchical. E HLS-577 You may not specify an input_delay or output_delay \ \n when selecting the include_script option. E IMPT-1 The variable '%s' isn't defined. E IMPT-2 The variable '%s' is of an unsupported external import option type. E IMPT-3 Unknown import format '%s'. E IMPT-4 Cannot execute '%s'. W IMPT-5 The variable 'edifin_lib_%s_symbol' isn't defined. E IMPT-12 Expected a list. Found '%s'. E IMPT-13 Each list must contain three elements: sheet name, orientation and symbol name. E IMPT-14 Sheet orientation must be 'landscape' or 'portrait'. '%s' is invalid. F INT-1 Unknown interrupt signal '%d' encountered. I INT-2 Interrupting current command. I INT-3 One more interrupt will exit process. I INT-4 Process terminated by interrupt. I INT-5 Preparing to interrupt optimization... I INT-6 Aborting optimization... I INT-7 Ignoring interrupt signal since the design is \ being mapped. One more interrupt will abort optimization without\ transferring the design... I INT-8 Aborting optimization without transferring the design... E LBDB-1 The '%s' function requires %d arguments. E LBDB-2 The value of argument %d of the '%s' function\n\ \tis of the wrong type. A value of '%s' type is required. E LBDB-3 The '%s' value is invalid for the '%s' attribute.\n\ \tIts valid values are %s. E LBDB-4 The %s '%s' cannot be specified during\n\ \tthe update_lib command. E LBDB-5 The library already has a '%s' attribute. It cannot be\n\ \toverwritten during the update_lib command. E LBDB-6 The library already has a '%s' group; it cannot be\n\ \toverwritten during the update_lib command because it is permanent. I LBDB-8 The %s '%s' group has been successfully %s\n\ \tin the library. W LBDB-11 The same '%s' attribute is defined twice and is ignored the second time. W LBDB-12 The '%s' attribute is the wrong type for the '%s' object. W LBDB-13 The '%s' enum has been defined twice and is being ignored. E LBDB-14 The library already has a '%s' group; the library\n\ \tcannot be overwritten unless the -overwrite option is specified. W LBDB-16 Found a duplicate %s attribute. Using the latest value. E LBDB-17 The library already has a type named '%s'. Type \n\ \tgroups can never be overwritten. W LBDB-18 In the '%s' library, the environment attribute \n\ \t%s's value is out of range. W LBDB-19 Can't find a pin named '%s' in the '%s' cell. W LBDB-20 Cannot process 'pin_opposite' for the '%s' cell. E LBDB-23 There is a missing timing arc between pins '%s' and\n\ \t'%s' in the '%s' cell. W LBDB-24 The '%s' symbol is used but is not defined. E LBDB-27 An invalid attribute is found. E LBDB-28 The '%s' attribute is supplied with %d arguments.\n\ \tOnly %d arguments are expected. W LBDB-29 The '%s' attribute is already defined for %s groups.\n\ \tIt cannot be redefined. W LBDB-30 There is a sequential timing arc with the\n\ \t%s non-clock pin for a related_pin attribute. I LBDB-31 The %s group has been successfully %s\n\ \tin the library. W LBDB-32 The '%s' group has been defined multiple times in\n\ \tthe '%s' library. Using the last definition encountered. E LBDB-34 There is a syntax error in the related_bus_pins attribute's value. W LBDB-35 Missing a timing arc of timing_type 'three_state_disable'\n\ \tbetween '%s' and '%s' pins in the '%s' cell. E LBDB-36 The '%s' specifies two variable names. W LBDB-37 The '%s' layer is defined multiple times:\n\ \tDeleting the old definition. E LBDB-39 The '%s' symbol is defined multiple times. E LBDB-40 In the '%s' symbol, the '%s' and '%s' pins both\n\ \thave the '%s' direction and the same Y location. E LBDB-41 In the '%s' symbol, the '%s' and '%s' pins both\n\ \thave the '%s' direction and the same X location. E LBDB-42 In the '%s' symbol, the '%s' pin '%s' and\n\ \tthe '%s' pin '%s' are uncorrectly positioned. E LBDB-43 The '%s' pin is defined multiple times in the '%s' symbol. E LBDB-46 Found an invalid rotation. E LBDB-47 The '%s' cell's pin '%s' has a timing arc that has\n\ \t%d matched timing arcs on the scaled_cell(%s,%s). E LBDB-48 The '%s' pin has a %s group whose related_pin\n\ \tis the port itself. E LBDB-50 In the '%s' cell, the '%s' input pin has a 'function' attribute. E LBDB-53 The '%s' attribute, which expects values of %s type,\n\ \tis being supplied a value of %s type. E LBDB-54 The define attribute has an invalid '%s' type.\n\ \tThe valid types are 'string', 'integer', 'float', and 'boolean'. E LBDB-55 The '%s' technology license is not installed. E LBDB-57 The 'generic' technology can only be read by Synopsys. W LBDB-58 The '%s' pin is a multicell_pad_pin, but\n\ \tit has no connection_class information. E LBDB-59 The '%s' found in the %s\n\ \tattribute is invalid. W LBDB-60 The wire_load or wire_load_table '%s' group has no\n\ \t'%s'. Using the default value of (%d, %3.1f). W LBDB-61 Template '%s' is defined in old library syntax. E LBDB-62 The '%s' symbol is a duplicate '%s' template. E LBDB-66 The '%s' attribute cannot be supplied a \n\ \tnonpositive value (%f). E LBDB-69 Missing a %s name. E LBDB-70 The '%s' group name is defined multiple times for the '%s' parent. E LBDB-72 Undefined module_pin '%s' referenced in pin_association\n\ \t'%s' in %s '%s'. E LBDB-73 The '%s' cell has more than one sequential \n\ \tfunction (seq, latch, or ff) declaration. E LBDB-74 The %s value, '%s', is either not \n\ \tdefined or it is defined after this line. W LBDB-75 There is an extra timing arc between '%s' and \n\ \t'%s' pins in the '%s' cell. E LBDB-76 The '%s' %s cannot be specified here. E LBDB-79 The 'ripped_pin' name is not defined. E LBDB-80 The '%s' port name is either undefined or \n\ \tits group definition is invalid. E LBDB-81 The base type in the type group is invalid. E LBDB-82 The data type in the type group is invalid. W LBDB-83 The width value in the type group is invalid.\n\ \tIt is corrected. W LBDB-86 The downto value in the type group is invalid.\n\ \tIt is corrected. E LBDB-87 The type group is missing its 'data_type' field. E LBDB-88 The type group is missing its 'base_type' field. E LBDB-89 The '%s' library attribute must be defined\n\ \tto specify a %s value. E LBDB-90 The type group is defined multiple times. W LBDB-91 The bus naming style format is invalid.\n\ \tUsing the default format. E LBDB-92 The bus subscript is out of bounds. E LBDB-93 The bus type is invalid. W LBDB-94 The ':' character is used in this bus naming style;\n\ \tthis makes it impossible to specify ranges of buses using ':'. E LBDB-95 Buses have incompatible widths. E LBDB-96 The bus type name is missing. E LBDB-97 The bus type of a subelement is missing. E LBDB-98 The type group name is not defined. E LBDB-99 The pin direction is inconsistent with the bus or\n\ \tthe bundle parent direction. E LBDB-101 The piece number in piecewise linear mode is negative. W LBDB-102 The '%s' piece is multiply\n\ \tdefined. Using the first one encountered. W LBDB-103 The piece number is greater than the number\n\ \tdefined with piece_define. W LBDB-104 The piecewise linear model is multiply defined.\n\ \tUsing the first one encountered. W LBDB-105 The timing arc has a negative %s\n\ \tspecified. Using the default value. W LBDB-107 The %s '%s' is defined multiple times\n\ \tin the library. Using the last one encountered. W LBDB-110 In the piecewise linear model, the first piece must\n\ \thave 0 length. W LBDB-111 In the piecewise linear model, a piece length\n\ \tsmaller than that of the previous piece has been found. E LBDB-112 The timing arc has only one segment of\n\ \t'%s'. It must have at least two if \n\ \tpiece_define has more than one piece. E LBDB-117 A list does not belong here. E LBDB-119 The '%s' pin on the %s could not be found on\n\ \tthe %s. There must be a one-to-one match. W LBDB-120 Layers are ignored inside symbols. E LBDB-126 The '%s' construct is not valid\n\ \tin '%s' libraries. E LBDB-132 In the '%s' cell, the %s '%s' pin cannot have\n\ \ta '%s' attribute. W LBDB-136 The '%s' attribute on the '%s' pin in\n\ \tthe '%s' cell is not valid on %s pins.\n\ \tThe attribute is ignored. W LBDB-138 The timing arc is missing the piecewise data value\n\ \tfor '%s'. The value is interpolated if possible.\n\ \tOtherwise, the default value is used if it exists. E LBDB-139 Invalid delay model for the given technology. W LBDB-140 The '%s' cell contains circular timing arcs.\n\ \tThe '%s' pin is in one of the cycles. W LBDB-141 The timing arc is missing the piecewise data value for\n\ \t'%s'. The default value is used if it exists. E LBDB-142 '%s' is an invalid value for the '%s'\n\ \tenumerated type attribute. E LBDB-143 An invalid string is provided. The invalid string is\n\ \teither a blank string or a string that begins with a digit\n\ \tthat is unquoted. E LBDB-144 The '%s' pin name does not match the '%s' bus name. W LBDB-145 The 'direction' attribute is missing in the %s '%s'. E LBDB-146 The value for the update attribute must be "true" or "false". E LBDB-147 A value must be specified for the annotate or\n\ \tthe annotate_symbol group. E LBDB-148 The '%s' pin is not found in the annotate_symbol group. E LBDB-149 The X value is invalid in the annotate or\n\ \tthe annotate_symbol group. E LBDB-150 The format specification cannot have more than %d %%s specifications. E LBDB-151 The format specification has %d %%s specification(s),\n\ \tbut only %d value(s) is/are specified. E LBDB-152 The '%s' object type is invalid in the annotate\n\ \tor the annotate_symbol group. E LBDB-153 A syntax error is found before the library or phys_library group.\n\ \tThe compilation is terminated. W LBDB-155 The %s_cell for the '%s' cell with '%s'\n\ \toperating_conditions is defined multiple times in the library.\n\ \tUsing the last one encountered. E LBDB-156 The LSI rounding digit and cutoff attributes\n\ \thave incompatible values. E LBDB-157 The '%s' cell name defined in the scaled_cell is not found. E LBDB-158 The '%s' operating conditions is not found. E LBDB-159 Incomplete EDIF properties are specified in the '%s' symbol.\n\ \tSpecify 'edif_cell_name', 'edif_view_name', and 'edif_name_property'. E LBDB-160 It is not acceptable to set the technology to\n\ \t'%s' after it has been set to '%s'. The two\n\ \ttechnologies are incompatible. E LBDB-161 The '%s' bus needs to have its bus_type specified first.\n\ \tThe %s '%s' was found before the bus_type. E LBDB-162 An invalid area range is found in the wire_load_from_area attribute. W LBDB-163 The '%s' attribute value is\n\ \t %s (%3.1f). Using %3.1f instead. E LBDB-164 The 'wire_load_from_area' range overlaps\n\ \tthe range in line %d. W LBDB-165 A range gap is found in the 'wire_load_selection'.\n \ \tThe 'min_area' is extended from %f to %f. W LBDB-166 A range does not start with 0.0 in the 'wire_load_selection'.\n\ \tThe 'min_area' is extended from %f to 0.0. E LBDB-167 The '%s' scaling factors group is not found. E LBDB-168 The %s timing constraint has only one value.\n \ \tOnly one 'intrinsic_rise' or 'intrinsic_fall' can be specified. E LBDB-169 An invalid 'three_state_disable' timing type appears\n\ \ton the timing arc. Its parent output pin has no 'three_state' attribute. W LBDB-170 The '%s' attribute's value is\n\ \t%s (%3.1f). Removing it. E LBDB-171 The '%s' wire load model is not defined, or \n\ \tit is defined after this line. W LBDB-172 The '%s' attribute is not specified. Using %4.2f. E LBDB-173 The '%s' group requires one or more names. E LBDB-174 The '%s' group requires %d names. W LBDB-175 The bus_naming_style contains characters that\n\ \tare also used as delimiters in function, three_state, and related_pin\n\ \tattributes. Be sure to put spaces around the characters in the [%s] set\n\ \twhen supplying values for attributes of the types mentioned.\n\ \tAlso, surround subscripted pin names with double quotes in pin groups. E LBDB-176 Invalid bus syntax is detected in '%s'. W LBDB-177 The attribute '%s' is not specified Using '%s'. E LBDB-179 The '%s' group requires the '%s' attribute.\n\ \tEither the attribute is missing or the attribute has an invalid value. E LBDB-180 The '%s' attribute requires both\n\ \t'clear' and 'preset' attributes. E LBDB-181 The '%s' group, with both 'clear' and 'preset' attributes,\n\ \trequires 'clear_preset_var1' and/or 'clear_preset_var2' attributes. E LBDB-182 Invalid %s name '%s' is detected. This name must be\n\ \tunique among all pin names, bus names, bundle names, and rail connection names. E LBDB-186 Invalid '%s' pin name is detected in the '%s' bundle. E LBDB-187 The '%s' bundle needs to have its 'members' specified first.\n\ \tThe '%s' %s is found before a 'members'. E LBDB-188 The 'members' attribute is defined multiple times. W LBDB-189 Level shifters are required for this library.\n\ \tA level shifter is a buffer or inverter with differing\n\ \tconnection_class values specified between input and output\n\ \tpins. Design Compiler cannot produce valid designs using this\n\ \tlibrary if a level shifter component is not provided. W LBDB-190 %s level shifter with input connection class '%s' \n\ and output connection class '%s' is needed. E LBDB-191 The inout '%s' pin, bus, or bundle has\n\ \tno 'three_state' function. E LBDB-200 The cell has both the 'pad_cell' and the 'auxiliary_pad_cell' attributes. E LBDB-201 A nonpad '%s' cell has a '%s' attribute. E LBDB-202 A nonpad '%s' cell has a '%s' pin\n\ \twith a '%s' attribute. E LBDB-203 The nonpad '%s' pin has a '%s' attribute. E LBDB-204 The '%s' %s pin cannot have a '%s' attribute. E LBDB-205 The '%s' pad pin is missing a '%s' attribute. E LBDB-206 The '%s' pad cell has no pad pins. W LBDB-207 The '%s' pad cell has more than one pad pin. \n\ \tUsing the first pin specified. E LBDB-208 The %s '%s' pad cell cannot be a 'clock' pad. E LBDB-209 A '%s' attribute cannot be specified on a\n\ \tpin unless a pull_up or pull_down driver_type is specified. E LBDB-210 The pulling_current value cannot be 0.0. E LBDB-211 The '%s' driver_type cannot be specified on a\n\ \tpin that already has a %s driver_type specified. E LBDB-212 The 'open_%s' driver_type cannot be specified on\n\ \tan input pin. E LBDB-213 The '%s' area attribute cannot be specified\n\ \ton a pin of a cell that is not a pad cell. E LBDB-214 The '%s' area attribute of '%s' type\n\ \tcannot be specified on a pin of a cell that is not a pad cell\n\ \tor an auxiliary pad cell. E LBDB-215 The '%s' attribute cannot be specified\n\ \ton the '%s' input pin. E LBDB-216 The '%s' scaled_cell's '%s' pin has a different\n\ \tnumber of timing arcs than the corresponding pin on the '%s' cell. E LBDB-217 The '%s' cell's '%s' pin has a timing arc without\n\ \ta counterpart on the scaled_cell(%s,%s). W LBDB-218 The 'direction' of the '%s' scaled_cell pin \n\ \tdoes not match that of the same pin name on the '%s' cell.\n\ \tResetting the scaled_cell pin's direction to match both directions. E LBDB-219 The (%s,%s) scaled_cell has duplicate\n\ \ttiming arcs for the '%s' pin. It is unclear\n\ \twhich arc corresponds to the arcs in the '%s' cell. E LBDB-220 The '%s' %s_voltage group has no '%s' attribute\n\ \tspecified. This attribute is essential in defining valid voltages. W LBDB-221 The '%s' %s_voltage group has a %s value,\n\ \twhich is %s %s. E LBDB-222 The fpga_family attribute is required when\n\ \tthe fpga_cell_type attribute is specified. E LBDB-223 The fpga_cell_type attribute is required when\n\ \tthe fpga_family attribute is specified. E LBDB-224 The fpga_timing_type is required on all arcs \n\ \twhen fpga_cell_type and fpga_family are specified. E LBDB-225 The fpga_timing_type is invalid when the fpga_cell_type\n\ \tand the fpga_family attributes are not defined on a cell. E LBDB-226 The FPGA CLB cell type from the x2000 family requires\n\ \tA, B, C, D, K, X, and Y pins. E LBDB-227 The FPGA IOB cell type from the x2000 family requires\n\ \tO, T, K, I, and PAD pins. E LBDB-228 The FPGA CLB cell type from the x3000 family requires \n\ \tA, B, C, D, E, K, EC, DI, RD, X, Y, and GSR pins. E LBDB-229 The FPGA IOB cell type from the x3000 family requires \n\ \tO, T, IK, OK, I, Q, PAD, and GSR pins. E LBDB-230 The FPGA CLB cell type from the x4000 family requires\n\ \tF1-F4, G1-G4, C1-C4, K, X, Y, XQ, YQ, GSR, CIN, and COUT pins. E LBDB-231 The FPGA IOB cell type from the x4000 family requires\n\ \tO, T, IK, OK, I1, I2, PAD, and GSR pins. E LBDB-235 This %s voltage or power supply group is not defined. E LBDB-236 An %s pin cannot specify an %s_voltage attribute. W LBDB-238 No '%s' attribute has been specified for the\n\ \tlibrary. This attribute is needed in %s libraries. E LBDB-239 The '%s' driver_type cannot coexist\n\ \twith the '%s' attribute on the '%s' pin. E LBDB-240 The '%s' cell area attribute has already been defined. W LBDB-241 Multiple cell area definitions (%s, %s) map\n\ \tonto the same '%s' area. Using the last one encountered. W LBDB-242 This '%s' timing arc has the same timing_type and\n\ \trelated_pin attributes as the timing arc on the line %d. W LBDB-243 The '%s' combinational cell has a '%s' pin with\n\ \ta sequential timing arc containing the '%s' timing_type. W LBDB-246 The default_wire_load_selection is not defined.\n\ \tBy default, the '%s' wire_load_selection group is used. E LBDB-247 The default_wire_load_selection is not defined.\n\ \tThe default_wire_load_selection attribute is required when more than one\n\ \twire_load_selection group is specified. W LBDB-250 The '%s' pin already has a 'pulling_resistance' value.\n\ \tThe 'pulling_current' causes the 'pulling_resistance' value to be overwritten. W LBDB-251 The '%s' pin has a 'hysteresis' attribute but\n\ \tno 'input_voltage' attribute. Both attributes are needed. E LBDB-252 The '%s' %s group already exists and\n\ \tcannot be overwritten. E LBDB-253 The '%s' pin does not have all the %s slew rate attributes\n\ \tdefined. The '%s' attribute is missing.\n\ \tAll %s slew-rate attributes must be specified together as a group. E LBDB-254 The '%s' edge rate related attribute \n\ \tcannot be specified on the '%s' output pin. E LBDB-255 The 'vhdl_name' attribute of '%s' is invalid VHDL or\n\ \tconflicts with another 'vhdl_name' attribute. W LBDB-256 The 'vhdl_name' attribute of '%s' is invalid VHDL or\n\ \tconflicts with another 'vhdl_name' attribute. Renamed to '%s'. W LBDB-257 The '%s' wire_load_selection group has been specified\n\ \twhile the default_wire_load_mode is %s 'top'. This causes \n\ \tthe 'wire_load_selection' group to work only for the top-level design. E LBDB-258 The '%s' driver_type cannot be specified\n\ \ton a inout pin without a three_state attribute. E LBDB-259 The '%s' refers to a nonexistent '%s'. E LBDB-260 The '%s' in '%s' and '%s' \n\ \tin '%s' of the '%s' lu_table_template represent \n\ \tthe same unallowable meaning. E LBDB-261 The '%s' has already been specified for '%s'. E LBDB-262 The '%s' attribute has an invalid sequence of\n\ \tdata '%f , %f'. The values must be in\n\ \tmonotonically increasing order. E LBDB-263 The '%s' attribute has a value '%f',\n\ \twhich is less than '%f', the minimum required value\n\ \tof this attribute. E LBDB-264 The '%s' is invalid in this look-up table. E LBDB-265 You cannot mix a cell delay table with\n\ \ta propagation delay table in the same timing group. E LBDB-266 The '%s' attribute is needed in the specification. \n\ \tNo default can be applied to this attribute. E LBDB-267 The '%s' is missing for this timing arc. E LBDB-268 The '%s' cannot be specified in a timing arc with\n\ \tthe '%s' timing_type. E LBDB-269 You have both '%s' and '%s'\n\ \tspecified in this timing group. E LBDB-270 The '%s' have a count of %d, which does not match\n\ \tthe size %d specified. E LBDB-271 The '%s' has zero elements. W LBDB-272 The '%s' attribute has a '%f' value,\n\ \twhich is less than '%f' the minimum recommended value of this attribute. E LBDB-273 The fanout_length complex attribute allows only 2\n\ \tor 5 arguments, and you specified %d arguments. W LBDB-274 The '%s' attribute has a '%f' value,\n\ \twhich is less than '%f' the minimum required value of this attribute.\n\ \tThe value is changed to the minimum value. W LBDB-275 The '%s' attribute has size 1, which is not \n\ \tused for any purpose with its associated variable. E LBDB-276 The '%s' refers to an invalid '%s'. E LBDB-278 The 'timing' group with '%s' timing_type \n\ \tneeds at least one look-up table. E LBDB-279 The 'timing' group with '%s' timing_type \n\ \tneeds one look-up table. E LBDB-280 The '%s' look-up table cannot use\n\ \t'%s' as its template. The look-up table is not\n\ \tcompatible with the template. E LBDB-281 The '%s' template has variables which\n\ \tshould not be used together. E LBDB-282 The '%s' attribute has a '%f' value\n\ \tthat is larger than the maximum allowed value of '%f'. E LBDB-283 The '%s' layer name is invalid. Valid names are '%s'. E LBDB-284 Missing 'routing_layers' attribute for this library\n\ \twhich is needed for specifying 'routing_track'. E LBDB-285 In this 'routing_track' group, 'tracks' is 0 and\n\ \t'total_track_area' is %f, which is inconsistent. E LBDB-286 No 'routing_track' information in the '%s' library. W LBDB-287 No routability information in the '%s' %s. E LBDB-288 The '%f' 'total_track_area' value is larger than\n\ \tthe '%f' cell area value. E LBDB-289 '%s' has been used more than one time in the\n\ \tspecification. E LBDB-290 '%s' should have at least one entry in it. W LBDB-291 No routability information for the '%s' layer.\n\ \tIt is assumed to be completely obstructed. E LBDB-292 The '%s' should be the %d%s attribute in the library. E LBDB-293 In this 'routing_track' group, the 'tracks' value\n\ \tis %d and the 'total_track_area' value is '0.0'. This is\n\ \tinconsistent. W LBDB-294 The UP or DOWN X pin coordinate does not lay on a grid. W LBDB-295 The LEFT or RIGHT Y pin coordinate does not lay on a grid. W LBDB-296 The '%s' pin of the '%s' auxiliary pad cell\n\ \tshould not have a function attribute. E LBDB-297 The '%s' pin is reserved and should not be used as a pin name. E LBDB-298 The '%s' attribute has a value %d, which is\n\ \tless than the minimum required value of this attribute %d. E LBDB-300 The '%s' related_outputs for the internal_power group has\n \ \tbeen specified. A duplicate is not allowed. I LBDB-301 No internal_power information for the '%s' cell. E LBDB-302 The '%s' specified in the '%s' is an\n\ \t%s pin. E LBDB-303 You cannot specify more than one input pin or one bit\n\ \tof a bus or bundle input pin in the 'related_input'. E LBDB-304 You can specify '%s'\n\ \tbut not both, because they are mutually exclusive. E LBDB-305 In the context, the '%s' valid value of the\n\ \t'%s' template is '%s'.\n\ \tYou specified '%s'. W LBDB-306 The '%s' preferred input voltage does not exist in this library. W LBDB-307 The '%s' preferred output voltage does not exist in this library. W LBDB-308 Incomplete set of pads to support the '%s'\n\ \tpreferred output pad slew rate control. W LBDB-309 In the '%s' gate, cannot degenerate the \n\ \t'%s' output due to excessive function size. I LBDB-310 Degenerating %d-input gates from '%s' component\n\ \tof the '%s' output. I LBDB-311 Degenerated %d %d-input gates from the '%s' component.\n\ \tA total of %d components have been degenerated from the '%s' output. W LBDB-312 Unable to do fpga complex degeneration on the '%s' gate because it %s. E LBDB-315 The '%s' attribute is incorrectly specified in the\ context. E LBDB-316 Arithmetic overflow or exception is encountered\n\ \ton the '%s' attribute with the '%s' value. E LBDB-317 It is invalid to specify the '%s' attribute\n\ \ton a pin within the bus or bundle group. E LBDB-350 The '%s' cell has the interface_timing attribute,\n\ \tbut is not a black box. W LBDB-353 A nonsequential timing arc is specified with\n\ \trespect to the '%s' clock pin. W LBDB-354 A sequential timing arc is specified with respect\n\ \tto the '%s' nonclock pin. W LBDB-355 A skew constraint is specified for the nonclock '%s' pin. W LBDB-356 Multiple %s constraints are specified between\n\ \tthe '%s' pin and the '%s' clock pin. W LBDB-357 The '%s' cell has the interface_timing attribute,\n\ \tbut has no clock pin. E LBDB-358 It is not legal to specify the attribute '%s' in\n\ \tthe '%s' group in this context. E LBDB-370 The library contains a '%s' group,\n\ \tbut has no contain '%s' group. E LBDB-371 The '%s' lut group is missing the mandatory '%s' attribute. E LBDB-372 The '%s' lut group attribute has an invalid '%s' value. E LBDB-373 The '%s' cell has more than one lut group defined. E LBDB-374 The '%s' input port is not in the '%s' lut. E LBDB-375 The '%s' port is incorrectly listed as an input in the\n\ \t'%s' lut. E LBDB-376 The '%s' port is invalid in a cell containing a lut group. E LBDB-377 The '%s' lut group is invalid in a multiple output cell. E LBDB-378 The '%s' lut group is invalid in a cell with no outputs. E LBDB-379 The '%s' output port on the '%s' cell has no\n\ \tfunction attribute, or the function attribute is invalid with\n\ \tthe lut group on this cell. E LBDB-380 The '%s' name is invalid for a lut group in the '%s'\n\ \tcell because a port on the design has the same name. E LBDB-381 The '%s' lut cell has %d input port(s). A lut\n\ \tcell must have at least 2 but no more than 6 input ports. E LBDB-382 The '%s' cell is an invalid lut cell. Only\n \ \tsimple combinational cells are valid. E LBDB-383 The '%s' attribute is invalid on\n\ \tthe '%s' lut cell. E LBDB-384 The lut marker cell attribute\n\ \t'%s' is invalid on the '%s' cell. E LBDB-385 The lut marker '%s' cell is functionally invalid.\n\ \tLut marker cells must be single output buffers. W LBDB-386 The lut marker '%s' cell has a nonzero\n\ \t'%s' attribute. Marker cells must have\n\ \tzero area and zero delay. W LBDB-387 The '%s' library has more than one lut output marker cell. E LBDB-388 The '%s' attribute cannot be specified in a\n\ \ttiming arc that is not a timing constraint. E LBDB-389 This timing arc has either '%s' or '%s'\n\ \tattribute but not both. W LBDB-390 The when and/or sdf_cond attributes in this\n\ \ttiming arc are ignored. W LBDB-391 The '%s' attribute on pin '%s' is not valid.\n\ \tThe attribute is ignored. E LBDB-392 The ECL Technology is obsolete with v3.4b. Compilation terminated abnormally. E LBDB-393 Too many values entered for the driver_type attribute. E LBDB-394 The driver type %s is incompatible with the %s pin %s. W LBDB-395 The timing arc with timing_type '%s'\n\ can only be specified on a pin with 'input' or 'inout' direction. W LBDB-396 The 'related_output_pin' attribute is only needed\n\ when the delay table refers to a template which uses the\n\ output loading of the related_output_pin in one of its dimension. E LBDB-397 There can only be one pin in the 'related_output_pin'\n\ attribute and the pin should be single bit. E LBDB-398 The pin '%s' specified in the 'related_output_pin'\n\ attribute is not an output or inout pin. E LBDB-399 The timing_type '%s' is not supported\n\ with the 'related_output_pin' attribute. W LBDB-400 The '%s' operating condition has been defined \n\ \tmultiple times in the '%s' library. \n\ \tDesign Compiler will use the first definition only. E LBDB-401 The '%s' is missing for this timing check. E LBDB-402 The '%s' is missing for this internal_power group. E LBDB-403 The '%s' and '%s' attributes are both defined for this\n\ \tinternal_power group. E LBDB-404 The '%s' lookup table in the input-associated\n\ \tinternal_power group cannot use '%s' as its template. E LBDB-405 The 1-dimensional '%s' lookup table in the\n\ \tinout-associated internal_power group cannot use '%s' as its template. E LBDB-406 The 1-dimensional '%s' lookup table in the\n\ \t%s-associated internal_power group cannot use '%s' as its template. E LBDB-407 The 2-dimensional '%s' lookup table in the\n\ \t%s-associated internal_power group cannot use '%s' as its template. E LBDB-408 The 3-dimensional '%s' lookup table in the\n\ \t%s-associated internal_power group cannot use '%s' as its template. E LBDB-409 The %d-dimensional template used in '%s' lookup table\n\ \tis incompatible with the template used in '%s' lookup table. E LBDB-410 The '%s' attribute is missing from the internal_power\n\ \tgroup. E LBDB-411 The internal_power group associated with pin '%s'\n\ \tcannot coexist with the cell-associated internal_power group in line %d. E LBDB-412 There is a missing internal_power relation between\n\ \tpins '%s' and '%s' in the '%s' cell. E LBDB-413 There is an extra internal_power group between '%s' and\n\ \t'%s' pins in the '%s' cell. E LBDB-414 In this internal_power group, the '%s' output pin in\n\ \tthe '%s' attribute is not functionally equivalent or opposite to the '%s' pin. E LBDB-415 The '%s' attribute cannot be specified in this\n\ \tinternal_power group. E LBDB-416 The '%s' cell is missing cell_leakage_power attribute. E LBDB-417 Pin '%s' has a timing arc that appears on only one of\n\ \tthe scaled cell (%s,%s) and the cell '%s'. W LBDB-418 The cell_degradation constraint is missing\n\ \tin this timing group in cell '%s'. W LBDB-419 Found the obsolete and unsupported 'state' group in the'%s' cell;\n\ \tplease use 'ff' group or 'latch' group or 'statetable' instead. E LBDB-420 The index number '%d' must be less than\n\ \tthe address width '%d'. E LBDB-421 The column or row address width '%d' must be less than\n\ \tor equal to the address width '%d'. E LBDB-423 Address pins are not all used by column_address and row_address attributes. W LBDB-424 The number of address pins that overlap between column and row is '%d'. W LBDB-425 Removing duplicate indices in the attribute. E LBDB-426 The '%s' is missing for this inout pin. E LBDB-427 All power supplies defined in the power_supply group\n\ \tmust exist in this operating_conditions group. E LBDB-428 All the pins in the '%s' cell with multiple power supplies\n\ \tmust have signal level attributes. W LBDB-429 The timing arc from '%s' to '%s' is dormant. E LBDB-430 The '%s' rail_connection in a cell with multiple power\n\ \tsupplies is missing an internal_power table. E LBDB-431 The value for attribute '%s' is empty. E LBDB-432 The non-Zero %d scalar value is not allowed in internal_power\n\ \tgroup within a cell group. E LBDB-433 The '%s' integrated gated clock cell has a '%s' pin with\n\ \ta combinational timing arc containing the '%s' timing_type. E LBDB-434 The '%s' integrated gated clock cell has a '%s' pin with\n\ \ta sequential timing arc containing the '%s' timing_type. E LBDB-435 The '%s' integrated gated clock cell has a '%s' pin without\n\ \tspecified timing arcs. E LBDB-436 Illegal timing_model_type value '%s'. W LBDB-437 The generated_clock(%s) group is defined \n\ \tmultiple times. E LBDB-438 The master pin is not specified in the generated_clock\n\ \tgroup. E LBDB-439 The clock pin is not specified in the generated_clock\n\ \tgroup. E LBDB-440 The generated_clock divisor is less than 1. E LBDB-441 The generated_clock multiplier is less than 1. E LBDB-442 The generated_clock edge is less than 0. W LBDB-443 The mode_definition(%s) group is defined\n\ \tmultiple times. E LBDB-444 The mode definition '%s' has no values defined. W LBDB-445 The mode_value(%s) group is defined\n\ \tmultiple times. E LBDB-446 The sdf_cond attribute is not specified for the\n\ \tmode condition. W LBDB-447 The mode instance is defined multiple times\n\ \tfor the same timing arc. E LBDB-448 The Boolean condition overlaps with the condition\n\ \tspecified at line %d. E LBDB-449 The mode instance mode(%s, %s) is invalid. E LBDB-450 Mismatched quotes in the sdf_cond string. E LBDB-451 Undefined variable '%s'. E LBDB-452 Fewer than two ports are specified in the\n\ \tshort list. E LBDB-453 The parameter '%s' in the short list is not a\n\ \tport or bus name. E LBDB-454 Unequal bus widths in the short list.\ \tspecified timing arcs. E LBDB-455 Multiple drive arcs are defined on port %s. E LBDB-456 The drive arc is not combinational. E LBDB-457 Related pin is found on the drive arc. E LBDB-458 Cell rise or fall table is missing on the\n\ \tdrive arc. E LBDB-459 The drive arc has tables that are not 1-D function\n\ \tof total_output_capacitance. E LBDB-460 Multiple tlatch groups are defined on\n\ \tpin '%s'. E LBDB-461 The edge type is not specified for the tlatch. E LBDB-462 Pin '%s' referred to in tlatch does not exist. W LBDB-463 The related pin '%s' for the non-sequential\n\ \tsetup/hold timing check is labeled a clock. E LBDB-464 The '%s' cell is a non-pad cell with x_function,\n\ \twhich is not supported by Library Compiler. E LBDB-465 The '%s' attribute is missing\n\ \tfrom the electromigration group. E LBDB-466 The '%s' attribute cannot be\n\ \tspecified in this electromigration group. E LBDB-467 The '%s' lookup table in the input-associated\n\ \telectromigration group cannot use '%s' as its template. E LBDB-468 The one-dimensional '%s' lookup table in the\n\ \tinout-associated electromigration group cannot use '%s' as its template. E LBDB-469 The one-dimensional '%s' lookup table in the\n\ \t%s-associated electromigration group cannot use '%s' as its template. E LBDB-470 The two-dimensional '%s' lookup table in the\n\ \t%s-associated electromigration group cannot use '%s' as its template. E LBDB-471 The '%s' port has %d electromigration tables.\n\ \tOnly one table is allowed. Path-dependent electromigration is not supported. W LBDB-472 The timing type of the timing arc from '%s' to\n\ \t'%s' is changed from '%s' to\n\ \t'%s'. E LBDB-473 The timing label '%s' is already used for \n \ \tanother timing arc in the same cell. E LBDB-474 The timing group has incorrect number of labels. E LBDB-475 The port '%s' is missing the attribute '%s'. W LBDB-476 The port '%s' does not have the attribute '%s' \ specified. The value %f will be assigned to the attribute. E LBDB-477 The table %s has invalid intermediate_values \n\ \tentry. \ \ E LBDB-478 The intermediate_values cannot be used with \n\ \tcurrent setting of output delay threshold voltages. E LBDB-479 when '%s' is specified '%s' has to be \n \ \t given as well. E LBDB-480 Missing a timing arc of timing_type 'three_state_disable'\ between the '%s' and '%s' pins in the '%s' cell. E LBDB-1001 Found one or more cells defined before resource group. E LBDB-1002 The resource name is not supported. E LBDB-1003 The resource group does not contain any layer definition. E LBDB-1004 The resource group does not contain any site definition. W LBDB-1005 Found a duplicate %s attribute. Using the first value. E LBDB-1006 Cannot accept the '%s' pin as the logically equivalent pin. E LBDB-1007 The %s name '%s' is an undefined layer name. E LBDB-1008 The %s function has inconsistent number of arguments. E LBDB-1009 Non-positive number found in the size function. E LBDB-1010 The site '%s' is not defined in the resource group. E LBDB-1011 Cannot accept the '%s' macro as the electrically equivalent cell. E LBDB-1012 The layer name, '%s', in the '%s' group is not unique. E LBDB-1013 The %s function has inconsistent number of arguments. E LBDB-1014 The via group does not have a 'contact' group. E LBDB-1015 One or more rectangles are required in this group. I LBO-1 Location based optimization enabled. I LBO-2 Location based optimization enabled with obstruction capability. W LBO-3 The pin '%s' has a location '%d %d' which is on \ an obstruction; fanout optimization will not be performed on the net. W LBO-4 Cannot estimate load/delay I LBO-5 reoptimize_design command is recommended for layout sensitive optimization W LBO-11 Cannot mark %s as an obstruction since bounding rectangle is not defined. W LBO-12 %s is already marked as an obstruction. W LBO-13 Cannot mark hierarchical cell %s as an obstruction. E LBO-15 No physical design information read before set_port_location\ in the incremental mode; unable to set the port location. I LBO-16 Resetting location for the port %s. I LBO-17 Setting location for port %s: X = %s %s Y = %s %s E LBO-18 Unable to find port %s in the current design. E LBO-19 Port %s does not have location information which can be changed. E LBO-20 set_port_location cannot annotate more than one port at a time. E LBO-21 Coordinates set must consist of two floating point values. E LBO-22 Pin location cannot be set without cluster information. E LBO-23 The library cell %s could not be found in the target library. E LBO-24 Pin %s of library cell %s could not be found. W LBO-25 Library cell %s does not have any dimensions. The pins of cell %s will be assigned the location of the cell. E LBR-1 Can't find the %s '%s'\n\ \tin the library '%s'. E LBR-2 The library '%s' is mapped to the directory\n\ \t'%s' which is not %s. W LBR-3 The %s '%s' is out of date with respect to its\n\ \tsource file '%s'. E LBR-4 The %s '%s' is out of date and I can't find the\n\ \tsource file '%s'. E LBR-5 The %s '%s' is out of date.\n\ \tPlease re-analyze it and try again. E LBR-6 The library '%s' is not mapped to a directory. E LBR-7 Could not write the file '%s'. W LBR-8 Library logical name '%s' is not mapped to a host directory. W LBR-9 The .mra file '%s' contains invalid data.\n\ \tThe invalid data is being ignored. W LBR-10 The environment variable '%s' has no value. W LBR-11 Design library name '%s' is reserved,\n\ \tand can not be defined by the user. W LBR-12 Logical library name '%s' is reserved,\n\ \tand can not be mapped by the user. W LBR-13 Logical library name '%s' can not be mapped to '%s',\n\ \twhich is reserved. E LBR-14 '%s' in library '%s' is a %s. A %s was expected. I LBR-15 Re-analyzing the out of date %s '%s'. E LBR-16 You cannot overwrite a library file. W LBR-17 The package '%s' is not able to be saved.\n\ \tIt will be used for this read, but will not\n\ \tbe able to be used for subsequent reads. E LBR-18 The variable '%s' is not set ...\n\ \tYou must use the '-filename' argument. E LBR-19 The entity '%s' does not have any architectures\n\ \tanalyzed for it. E LBR-20 You can't specify an architecture when elaborating\n\ \ta configuration. W LBR-21 The design '%s' has no parameters.\n\ \tThe parameters '%s' have been ignored. E LBR-22 The library '%s' cannot be mapped to the same\n\ \tdirectory as '%s'. E LBR-23 Could not delete the file `%s'. E LBR-24 The file `%s'\n\tdoes not contain the design `%s'. E LBR-25 The file '%s' contains more than one entity. E LBR-26 Could not read in the file '%s'. I LBR-27 Overwriting the '%s' \ version of architecture '%s'\n\t with a '%s' version in the library '%s'. E LBR-28 The %s '%s' depends on the %s '%s'\n\ \twhich has been analyzed more recently.\n\ \tPlease re-analyze the source file for '%s' and try again. E LBR-29 Design library '%s' cannot be mapped to the same directory\n\tas design library '%s'. E LBR-30 Recursion detected in .syn files.\n\tDesign unit '%s' was referenced multiple times. E LBR-31 '%s' is being defined as a design library (using the '>'\ operator, but it was already defined as a logical library\ (using the ':' operator or the define_design_lib command).\ To modify the directory that '%s' is mapped to, please\ use ':' or the define_design_lib command. E LBR-32 Can't find file '%s'.\n\tUpdate failed. E LBR-33 File '%s' was not generated\n\tfrom '%s'. Update failed. E LBR-50 An order-based parameter:\n\ \t%s\n\ \twas specified after a name-based parameter. E LBR-51 Parameter "%s" multiply defined. E LBSYN-1 The parameter '%s' has been defined multiple times \n\ \tin module '%s'. E LBSYN-2 Pin association '%s' must specify exactly one of "oper_pin" or "value". E LBSYN-3 Binding '%s' must specify "bound_operator". E LBSYN-4 The module or component '%s' requires a design_library attribute. E LBSYN-5 Operator pin '%s' must either be "input" or "output". E LBSYN-6 Operator '%s' data_class must either be "unsigned" or "signed". E LBSYN-7 Module pin '%s' must have a 'bit_width' attribute. E LBSYN-8 The value "%s" in group %s(%s) is not legal. E LBSYN-9 The value attribute is missing in group %s(%s). E LBSYN-10 Parameter '%s' cannot have both a constant attribute\n\ and a formula attribute. E LBSYN-11 Parameter '%s' has a constant attribute\n\ without a type attribute. W LBSYN-12 In parameter '%s', the type attribute is ignored. E LBSYN-13 The string %s can not be evaluated,\n\ \ttherefore it can't be used for the bit_width value on pin %s. E LBSYN-15 The binding group %s in the module %s does not\n\ \tcontain any pin_association groups. W LBSYN-16 The parameter %s does not have the\n\ \thdl_parameter attribute set true, nor does it have a formula. W LBSYN-17 the parameter %s formula may not evaluate\n\ \tcorrectly during a compile operation because of: %s. E LBSYN-18 Substitute Licenses are for internal use only. E LBSYN-19 The "substitute_license" group requires an "original_license" attribute. E LBSYN-20 The "substitute_license" group requires a "substitute_license" attribute. W LBSYN-21 The "substitute_license" group contains no "valid_modules" attribute. E LBSYN-22 Original license must be DesignWare-Foundation. E LBSYN-23 Only one generator group can exist in a library. E LBSYN-24 The "generator" group requires the \n\ \t'%s' attribute. E LBSYN-25 The "generator" group requires a\ "generator_interface" attribute. E LBSYN-26 The "generator" group requires a\ "contact_upon_failure" attribute. E LBSYN-27 Only one "verilog" subgroup may exist in a \ "generator" group. E LBSYN-28 Only one "vhdl" subgroup can exist in a \ "generator" group. E LBSYN-29 The attribute "output_format" requires either a "vhdl"\ or a "verilog" subgroup. E LBSYN-30 Specify either a "vhdl" or "verilog" group, but\ not both. I LBSYN-31 Generator '%s' assumed to create DB output. E LBSYN-32 The formula for parameter '%s' requires a string \n\ expression. E LBSYN-33 Only one "sdf" subgroup may exist in a\n\ \t"generator" group. W LBSYN-34 The module group '%s' has no output pins defined.\n W LBSYN-35 The module group '%s' has no input pins defined.\n E LBSYN-36 The pin '%s' in module group '%s' has an improper\n\ \tdirection specified. W LBSYN-37 The pin associations for the module %s do not\n\ \tbind to any output pins. W LBSYN-38 The pin associations for the module %s do not\n\ \tbind to any input pins. W LBSYN-39 The sequential bindings allow states '%s' and '%s'\n\ \tto simultaneously use pin '%s' on module '%s'. E LBSYN-40 The '%s' group named '%s' is multiply defined. W LBSYN-41 The resource named '%s' is used but not defined\n\ \tin the synthetic module '%s'. W LBSYN-42 Operator '%s' has an excessive number (%d total)\n\ \tof bindings. E LBSYN-43 Unable to find the operator pin '%s' named by an\n\ \tunbound_oper_pin group in binding '%s' in\n\ \tmodule '%s'. E LBSYN-44 Multiple implementation groups named '%s'\n\ \tfound in synthetic module '%s'. E LBSYN-45 Input pin '%s' cannot have both the 'sreset' and the\n\ \t'areset' attribute in the synthetic module '%s'. E LBSYN-46 The binding '%s' in module '%s'\n\ \tcontains a constraint specifying a nonexistent pin '%s'\n\ \tof the operator '%s'. W LBSYN-47 The number of permutable inputs (%d) and the\n\ \tnumber of bindings (%d) do not agree for operator '%s'\n\ \tin the module '%s'. W LBSYN-49 The binding '%s' in module '%s' refers to an\n\ \toperator, '%s', which is not found in the synthetic library list. E LBSYN-57 Multiple clock pins exist on module '%s'. E LBSYN-58 Unbound operator pin value must evaluate to '1'\n\ \tfor operator pin '%s' in binding '%s' in\n\ \tmodule '%s'. W LBSYN-59 The width function is only supported in module group\n\ \tparameter formulas. W LBSYN-60 Module pin '%s' in state '%s'\n\ \tof binding '%s' for module '%s' is not bound to any\n\ \toperator pin and the module pin does not specify a\n\ \tstall value. E LBSYN-61 Module '%s' is of type '%s',\n\ \twhich is not a valid type. E LBSYN-62 Operator '%s' is of type '%s',\n\ \twhich is not a valid type. E LEFIN-1 There is no layer definition. E LEFIN-2 There is no site information. E LEFIN-3 There is no cell information. W LEFIN-4 There is no via information. E LIBAN-1 Invalid switch value for '%s'. E LIBAN-2 Undefined switch '%s'. E LIBAN-3 Command syntax error is detected in '%s'. E LIBAN-5 The '%s' DB file is not a technology library. E LIBAN-6 You do not have authorization to use the '%s' library. E LIBAN-7 The '%s' library cannot be used for simulation. E LIBAN-11 No technology library was specified. E LIBAN-12 The switch value for '%s' is required. E LIBAN-13 Cannot read the '%s' file. E LIBAN-14 The '%s' library is created with an older version of Synopsys software. E LIBAN-15 The '%s' switch cannot be defined twice. E LIBAN-16 Bad switch value '%s' for '-arch' is detected.\n\ \tThe valid switch values are: UDSM, FTSM, FTGS and VITAL. E LIBAN-17 The '%s' switch is obsolete. E LIBG-1 The Synopsys database is corrupted. The library is not created. E LIBG-2 An invalid '%s' function string in the '%s' cell. E LIBG-3 A bad '%s' pin name in the '%s' cell. E LIBG-4 In the '%s' cell, the '%s' noninput pin \n\ \tcannot be used in the function. E LIBG-5 Cannot find the '%s' pin in the '%s' cell. E LIBG-6 Missing a related_pin for the '%s' pin timing group\n\ \tin the '%s' cell. E LIBG-8 In the '%s' cell, the '%s' input drives more than one function. W LIBG-16 The '%s' Pin/bus on the '%s' cell has no 'function' attribute.\n\ \tThe cell becomes a black box. E LIBG-17 The 'function' of the '%s' pin/bus on the '%s' cell\n\ \tcan only be '%s' or '%s'. I LIBG-18 The '%s' equation on the '%s' cell is not recognized. E LIBG-20 The '%s' equation on the '%s' cell evaluates\n\ \tto a '%s' constant. E LIBG-21 The derived equality relationship between '%s' and \n\ \t'%s' pins conflicts with the user-specified 'pin_opposite' for the '%s' cell. E LIBG-22 The derived opposite relationship between '%s' and \n\ \t'%s' pins conflicts with the user-specified 'pin_equal' for the '%s' cell. I LIBG-24 Unable to honor the 'prefer_tied' attribute onthe '%s' pin\n\ \tof the '%s' cell. W LIBG-25 Duplicated test signals of '%s' type is found on\n\ \tthe '%s' library cell. E LIBG-26 The '%s' test cell pin on the '%s' cell\n\ \thas no 'function' attribute. The test cell is removed. W LIBG-27 The '%s' pin is eliminated from the '%s' pin \n\ \tfunction on the '%s' cell. The cell becomes a black box. W LIBG-28 The '%s' three state pin has no 'function' or\n\ \tthe function is too complex to be recognized;\n\ \tthe '%s' cell becomes a black box. W LIBG-29 The state group needs more statements to be\n\ \tmeaningful; cell becomes black-box. W LIBG-30 The '%s' equation on the '%s' cell evaluates\n\ \tto a constant '%s'. Since this implies the output will never become\n\ \t%s, this equation is ignored. W LIBG-31 The test cell on cell '%s' does not have any function. E LIBG-32 The '%s' parallel sequential cell must use\n\ \tbus/bundle for outputs. W LIBG-33 In the '%s' cell, the '%s' inout pin\n\ \tcannot have feedback in its function. The cell becomes a black box. E LIBG-34 The '%s' pin in the '%s' cell has the '%s' direction\n\ \tThe direction must be '%s'. W LIBG-35 The 'nextstate_type' attribute on the '%s' pin/bus in\n\ \tthe '%s' cell is inconsistent with its function. The attribute is ignored. W LIBG-36 In the '%s' cell, the '%s' input drives more than one\n\ \tfunction. The cell might not be optimally used. W LIBG-37 The '%s' pin/bus is unused in the '%s' cell.\n W LIBG-38 The '%s' enable pin with a three_state attribute in the\n\ \t '%s' cell should have non-unate timing arcs. W LIBG-39 The '%s' asynchronous input of the '%s' cell is inconsistent in active level. W LIBG-40 The '%s' clock/gate input of the '%s' cell is inconsistent in active edge/level. W LIBG-41 The 'when' attribute (%s) uses pins\n\ \tthat cannot be found in %s (%s). E LIBG-42 The '%s' related pin of the '%s' cell has clear/preset\n\ \ttiming arcs but is not asynchronous. E LIBG-43 The '%s' related pin of this timing arc is an output pin and\n\ \tthe timing_sense is not specified. E LIBG-44 The logic represented by the 'when' string (%s) in this\n\ \ttiming group is not mutually exclusive with the logic represented by\n\ \tthe 'when' string (%s) in the timing group on line %d. E LIBG-45 The 'timing_sense' attribute is missing. It is required\n\ \tfor '%s' timing arc. E LIBG-46 The '%s' pin of the '%s' cell is not a clock/enable pin and\n\ \tcannot be used in the 'related_pin' of timing arc with the \n\ \t'%s' timing_type. W LIBG-47 Cell(%s): The state table entries have been expanded.\n\ \tThe following %d %s of overlapping entries %s been found:\n\ %s\n\ \tFor each occurrence, the first "rule out" entry is used. W LIBG-48 Cell(%s): The following %d %s, which includes\n\ \tcurrent and delayed input values in the state table, %s unspecified: %s\n\ \tOutputs are made unknown. E LIBG-49 Cell(%s): '%s' token in "%s" field is not recognized. E LIBG-50 Cell(%s): Incorrect "%s" field size in table.\n\ \tSize found: %d, expecting: %d. E LIBG-51 Cell(%s): The '%s' port has too many port names in 'input_map'.\n\ \tNumber of ports specified is %d, the maximum number expected is %d. E LIBG-52 Cell(%s): The '%s' port requires either 'internal_node' or\n\ \t'state_function'. E LIBG-53 Cell(%s): The 'internal_node' in the '%s' port\n\ \tdoes not match any internal node name in the state table. W LIBG-54 Cell(%s): The '%s' internal pin does not drive any\n\ \toutput or is unneeded. The pin is ignored. E LIBG-55 Cell(%s): The 'input_map' in the '%s' port is not\n\ \tallowed with the 'state_function'. Deleting the table. E LIBG-56 Cell(%s): The '%s' node must be specified in\n\ \tthe 'input_map' of the '%s' port. Deleting the table. E LIBG-57 Cell(%s): Duplicate '%s' names in the 'input_map' of the '%s' port. E LIBG-58 Cell(%s): For the '%s' port, the '%s' node is mapped to\n\ \t'%s', which is not a port. E LIBG-59 Cell(%s): The 'input_map' of the '%s' port maps\n\ \tthe '%s' input port to the '%s' internal node. W LIBG-60 Cell(%s): translates into a combinational cell.\n\ \tThe State table information is not created. E LIBG-61 Cell(%s): Verification failure on the '%s' port. Deleting the table. W LIBG-62 Cell(%s): The '%s' input node is not required by any\n\ \tinternal node used. The input node is ignored. E LIBG-63 Cell(%s): The '%s' internal node is combinational. E LIBG-64 Cell(%s): The '%s' port cannot have both 'internal_node'\n\ \tand 'state_function' attributes. E LIBG-65 Cell(%s): The '%s' internal pin cannot have a 'three_state' attribute. W LIBG-67 Cell(%s): The '%s' port has both the internal_node\n\ \tand the input_map specified. However, there is a mismatch in the mapping.\n\ \tThe '%s' port is mapped by the input_map instead of the '%s' port, \n\ \tthe name of the internal_node. The '%s' port, specified in the input_map, is used. E LIBG-68 Cell(%s): Mismatch in internal pins between\n\ \tthe v3.1 format and the state table. Deleting the table. W LIBG-69 Cell(%s): The '%s' input is specified as\n\ \tdelayed in the state table. It will be used. W LIBG-70 Cell(%s): Delayed inputs are specified in\n\ \tthe input_map of the '%s' port. They will be used. E LIBG-71 Cell(%s): The '%s' port was expected to be %s with\n\ \trespect to the '%s' port. E LIBG-72 Cell(%s): Cannot find an implicit internal pin in\n\ \tthe v3.1 format to match the '%s' internal pin. W LIBG-73 Cell(%s): Table inputs for the '%s' port exceed 16 inputs. E LIBG-74 Cell(%s): No internal_node output pin is found. E LIBG-75 Cell(%s): The state_function on the '%s' port has\n\ \tan invalid port in the expression. W LIBG-76 The '%s' test cell pin on the '%s' cell\n\ \thas a timing arc. The timing arc is ignored. E LIBG-77 The '%s' test cell pin on the '%s' cell\n\ \thas a conflicting pin type. W LIBG-78 The '%s' test cell pin on the '%s' cell\n\ \thas a conflicting pin type. Removing the test cell. E LIBG-79 The '%s' test cell pin on the '%s' cell\n\ \thas a conflict between the function and the test type. W LIBG-80 The '%s' test cell pin on the '%s' cell has a\n\ \tconflict between the function and the test type. The test cell is removed. E LIBG-81 Cell(%s): translates into a combinational cell. E LIBG-82 The test cell on the '%s' cell is not Test Compiler supported. W LIBG-83 The test cell on the '%s' cell is not Test Compiler supported.\n\ \tRemoving the test cell. W LIBG-84 The '%s' port in the '%s' cell does not\n\ \thave a function in the test cell descriptions. The cell is a black box. E LIBG-85 The '%s' port in the '%s' cell does not\n\ \thave a function in the test cell descriptions. W LIBG-86 The '%s' port in the '%s' cell has a timing\n\ \tarc related to '%s' that is inconsistent. E LIBG-87 Cell(%s): the internal node has L/H or H/L but\n\ \tno input has L/H or H/L. Deleting the table. E LIBG-88 The '%s' port in the '%s' cell has a timing\n\ \tarc related to '%s' that is inconsistent. W LIBG-89 The '%s' port in the '%s' cell has an inconsistent\n\ \tfunction in the test cells. E LIBG-90 The '%s' port in the '%s' cell has an inconsistent\n\ \tfunction in the test cells. E LIBG-91 The '%s' attribute is required when both 'clear'\n\ \tand 'preset' are present in the sequential model and the %s '%s'\n\ \tis used in the function attribute of the output pin(s) of the cell. W LIBG-92 The '%s' port in the '%s' cell has a circular dependency. E LIBG-93 The '%s' port in the '%s' cell has a circular dependency. W LIBG-94 The '%s' cell needs a noninverted output. E LIBG-95 The '%s' cell needs a noninverted output. W LIBG-96 The '%s' port in the '%s' cell is used in both test and\n\ \tnon test mode. E LIBG-97 The '%s' port in the '%s' cell is used in both\n\ \ttest and non test mode. W LIBG-98 The '%s' test cell has an incompatible non test mode. E LIBG-99 The '%s' test cell has an incompatible non test mode. W LIBG-100 The '%s' port in the '%s' cell has both a function\n\ \tand a test attribute. The test_cell will be deleted. E LIBG-101 The '%s' port in the '%s' cell has both a function\n\ \tand a test attribute. W LIBG-102 The '%s' cell has more than one clock. E LIBG-103 The '%s' cell has more than one clock. W LIBG-104 The '%s' pin of the '%s' design is not a clock pin\n\ and should not be used in the 'related_pin' of '%s' timing arc. E LIBG-105 There is a missing timing arc between the '%s' and '%s'\n\ \tpins in the '%s' cell. A timing arc of the right timing_type\n\ \tis expected between the two specified pins of the cell. W LIBG-106 The '%s' timing type is invalid between the\n\ \ttwo specified pins. E LIBG-107 The complex state_function is not allowed in the '%s' test cell. E LIBG-108 The three_state attribute is not allowed in the '%s' test cell. W LIBG-109 Asynchronous specifications in the '%s' cell are\n\ \tincompletely specified. W LIBG-110 Asynchronous specifications in the '%s' cell \n\ are incomplete or are not mutually exclusive.\n\ \tThe cell has been made a black box. W LIBG-111 Design Compiler does not support the values for\n\ \tclear_preset_var? in the '%s' cell. The cell has been made a black box. E LIBG-112 The timing check condition represented in this timing\n\ \tgroup is not mutually exclusive with the timing check condition\n\ \trepresented in the timing group on line %d. E LIBG-113 The timing check starting and ending conditions\n\ \trepresented in this timing group are not mutually exclusive with the\n\ \ttiming check starting and ending conditions represented in the \n\ \ttiming group on line %d. W LIBG-115 The when attribute uses '%s' pins\n\ \tthat cannot be found in the %s %s. W LIBG-116 No test_scan_in/test_scan_in_inverted signal \n\ \ttypes exist on the '%s' test_cell cell. Converting the entire cell to a black box. W LIBG-117 No test_scan_out/test_scan_out_inverted signal \n\ \ttypes exisit on the '%s' test_cell cell. Converting the entire cell to a black box. W LIBG-118 The clocked_on_also function on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin.\n\ \tConverting the entire cell to a black box. W LIBG-119 The test_scan_clock_b signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin.\n\ \tConverting the entire cell to a black box. W LIBG-120 The test_scan_in signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin.\n\ \tConverting the entire cell to a black box. W LIBG-121 The test_scan_in_inverted signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin.\n\ \tConverting the entire cell to a black box. W LIBG-122 The test_scan_enable signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin.\n\ \tConverting the entire cell to a black box. W LIBG-123 The test_scan_enable_inverted signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin.\n\ \tConverting the entire cell to a black box. E LIBG-124 test_scan_clock signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin.\n\ \tConverting the entire cell to a black box. E LIBG-125 The test_scan_clock_a signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin.\n\ \tConverting the entire cell to a black box. W LIBG-126 The test_clock signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin. \n\ \tConverting the entire cell to a black box. W LIBG-127 The '%s' clocked test cell is not valid \n\ \tbecause it has a master-slave cell as its nontest mode.\n\ \tConverting the entire cell to a black box. W LIBG-128 Invalid nontest mode for test_cell on the '%s' cell;\n\ \tthere are more than 2 sequential elements. \n\ \tConverting the entire cell to a black box. W LIBG-129 Invalid nontest mode for test_cell on the '%s' cell. \n\ \tThis mode describes a ganged cell. W LIBG-130 The nontest mode for test_cell on the '%s' cell is invalid.\n\ \tThe '%s' slave port does not directly feed the output. W LIBG-131 The nontest mode for test_cell on the '%s' cell is invalid.\n\ \tThe '%s' state pin is not a latch for a master-slave configuration. W LIBG-132 The test cell for auxiliary clocked lssd '%s' cell is not\n\ \tvalid because its nontest mode is not a flip-flop. W LIBG-133 The test_cell on the '%s' cell cannot have more than one\n\ \ttest_scan_in/test_scan_in_inverted signal type. This happens on \n\ \tthe '%s' port. W LIBG-134 The '%s' port in test_cell on the '%s' cell has a\n\ \ttest_scan_out signal type on an inverted output. W LIBG-135 The '%s' port in test_cell on the '%s' cell has a\n\ \ttest_scan_out_inverted signal type on a noninverted output. W LIBG-136 The test cell on the '%s' cell cannot have more than one\n\ \ttest_scan_enable or test_scan_enable_inverted signal type. This \n\ \thappens on the '%s' port. W LIBG-137 The test_scan_clock '%s' port in test_cell on the '%s' cell\n\ \tdoes not have an active sense. W LIBG-138 The test_scan_clock_a '%s' port in test_cell on the '%s' cell \n\ \tdoes not have an active sense. W LIBG-139 The test_scan_clock_b '%s' port in test_cell on the '%s' cell\n\ \tdoes not have an active sense. W LIBG-140 The test_clock '%s' port in test_cell on the '%s' cell does\n\ \tnot have an active sense. W LIBG-141 The '%s' port in test_cell for the '%s' cell has an invalid\n\ \tsignal type %s. W LIBG-142 The LSSD test_cell for the '%s' cell has neither\n\ \ta test_scan_clock_b signal type nor a master-slave configuration as its non test mode. W LIBG-144 The test_cell for the '%s' cell is not valid because\n\ \tit has missing or extra test signals. W LIBG-145 Cannot derive full function based on test_cell\n\ \ton the '%s' cell in a library with DPCM vendor specific delay model. W LIBG-146 Cannot derive full function based on test_cell\n\ \ton the '%s' cell due to previous warnings or errors. E LIBG-147 No test_scan_in/test_scan_in_inverted signal\n\ \ttypes exist on the '%s' test_cell cell. E LIBG-148 No test_scan_out/test_scan_out_inverted signal\n\ \ttypes exist on the '%s' test_cell cell. E LIBG-149 The clocked_on_also function on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin. E LIBG-150 The test_scan_clock_b signal type on the '%s' port for \n\ \ttest_cell on the '%s' cell is not specified on the correct pin. E LIBG-151 The test_scan_in signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin. E LIBG-152 The test_scan_in_inverted signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin. E LIBG-153 The test_scan_enable signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin. E LIBG-154 The test_scan_enable_inverted signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin. E LIBG-155 The test_scan_clock signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin. E LIBG-156 The test_scan_clock_a signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified on the correct pin. E LIBG-157 The test_clock signal type on the '%s' port for\n\ \ttest_cell on the '%s' cell is not specified correctly. E LIBG-158 Invalid nontest mode for test_cell on the '%s' cell.\n\ \tThere are more than 2 sequential elements. E LIBG-159 Invalid nontest mode for test_cell on the '%s' cell. \n\ \tThis describes a ganged cell. E LIBG-160 The nontest mode for test_cell on the '%s' cell is invalid.\n\ \tThe '%s' slave port does not directly feed the output. E LIBG-161 The nontest mode for test_cell on the '%s' cell is invalid\n\ \tThe '%s' state pin is not a latch for a master-slave configuration. E LIBG-162 The test_cell on the '%s' cell cannot have more than one\n\ \ttest_scan_in or test_scan_in_inverted signal type. This happens on the \n\ \t'%s' port. E LIBG-163 The '%s' port in test_cell on the '%s' cell has a\n\ \ttest_scan_out signal type on an inverted output. E LIBG-164 The '%s' port in test_cell on the '%s' cell has a\n\ \ttest_scan_out_inverted signal type on a noninverted output. E LIBG-165 The test cell on the '%s' cell cannot have more than one\n\ \ttest_scan_enable or test_scan_enable_inverted signal type.\n\ \tThis happens on the '%s' port. E LIBG-166 The '%s' test_scan_clock port in test_cell on the '%s' cell\n\ \tdoes not have an active sense. E LIBG-167 The '%s' test_scan_clock_a port in test_cell on the '%s' cell\n\ \tdoes not have an active sense. E LIBG-168 The '%s' test_scan_clock_b port in test_cell on the '%s' cell\n\ \tdoes not have an active sense. E LIBG-169 The '%s' test_clock port in test_cell on the '%s' cell does \n\ \tnot have an active sense. E LIBG-170 The '%s' port in test_cell for the '%s' cell has an invalid\n\ \tsignal type %s. E LIBG-171 The LSSD test_cell for the '%s' cell has neither\n\ \ta test_scan_clock_b signal type nor a master-slave as its nontest mode. E LIBG-172 The test_cell for the '%s' cell is not valid because\n\ \tit has missing or extra test signals. E LIBG-173 Cannot derive full function based on test_cell\n\ \ton the '%s' cell due to previous warnings or errors. E LIBG-174 The '%s' clocked test cell is not valid\n\ \tbecause it has a master-slave configuration as its nontest mode. E LIBG-175 The test cell for the '%s' auxiliary clocked lssd cell is not \n\ \tvalid because its nontest mode is not a flip-flop. E LIBG-176 Neither the memory_read nor the memory write group\n\ \tis allowed on scalar ports. E LIBG-177 The '%s' cell is a ROM, and ROMs cannot have any\n\ \tmemory_write groups. E LIBG-178 The '%s' cell is a RAM, and RAMs must have at\n\ \tleast one memory_read port and at least one memory_write port. E LIBG-179 The '%s' cell is a ROM, and ROMs must have at\n\ \tleast one memory_read group. E LIBG-180 The '%s' bus has a %s group, but the '%s' cell\n\ \thas no memory group. E LIBG-181 In the '%s' cell, the '%s' data bus has a width of %d,\n\ \tbut the memory group has a word width of %d. E LIBG-182 The '%s' memory_write data bus can not be an output. E LIBG-183 In the '%s' cell, the '%s' address bus is not defined. E LIBG-184 In the '%s' cell, the '%s' address bus has a width of %d,\n\ \tbut the memory group has an address width of %d. E LIBG-185 The '%s' memory address can not be an output. E LIBG-186 In the '%s' cell, the '%s' memory_read data bus\n\ \tcannot be an input. E LIBG-187 In the '%s' cell, The %s '%s' attribute is not\n\ \tthe name of a port or bus. E LIBG-188 In the '%s' cell, the %s '%s' bus has a width of %d,\n\ \tbut the memory group has a word width of %d. E LIBG-189 In the '%s' cell, the memory_write group cannot\n\ \thave both the enable attribute and the clocked_on attribute. E LIBG-190 In the '%s' cell, the v3.1 sequential syntax is not\n\ \tsupported on memory cells. E LIBG-191 The '%s' memory output cannot have a function. E LIBG-192 The '%s' port that has both memory_read and memory_write\n\ \tmust have the inout direction. E LIBG-193 The '%s' port that has both memory_read and memory_write\n\ \tmust have a three_state expression. W LIBG-194 The function attribute on the '%s' pin is ignored. W LIBG-195 A bundle is not supported in the memory group. E LIBG-196 The inverted_output attribute is not defined in the '%s' output port. W LIBG-197 In the '%s' cell, the '%s' and '%s'\n\ \tmemory read or memory write ports have the same address attribute. E LIBG-198 The '%s' pin of the '%s' design must be an '%s'. E LIBG-199 The '%s' input port in the '%s' cell cannot have timing arcs. E LIBG-201 The min_period and min_pulse_width attributes are not allowed on the '%s' port in the '%s' cell. I LIBG-202 In the '%s' cell, the '%s' internal pin is\n\ \treplaced with the inverted '%s' output pin. W LIBG-203 The '%s' test cell has no function. E LIBG-204 The '%s' test cell has no function and the cell is black box. W LIBG-205 Cell(%s): The function cannot be recognized\n\ \tby Design Compiler. E LIBG-207 The logic represented by the 'when' string (%s) in this\n\ \t%s group is not mutually exclusive with the logic represented by\n\ \tthe 'when' string (%s) in the %s group on line %d. W LIBG-208 Different number of pins on the '%s' test_cell are found.\n\ \tThe test_cell is removed. W LIBG-209 Unable to find the '%s' pin on the '%s' test_cell.\n\ \tThe test_cell is removed. E LIBG-210 The '%s' pin of the '%s' cell has conflicting signal_types\n\ \tbetween the cell and the test_cell. W LIBG-211 Cell '%s' contains unused input pin(s).\n\tIt is labeled dont_use and dont_touch. W LIBG-212 The logic represented by the '%s' when string in this %s group\n\ \tdoes not sensitize one or all pins in the '%s' related_pin attribute for the %s function attribute. W LIBG-213 The default internal power is not needed for the %s pin. W LIBG-214 The default internal power is required for the '%s' pin. E LIBG-215 The '%s' when condition includes the '%s' related pin. W LIBG-220 The '%s' equation on the '%s' cell evaluates\n\ \tto a '%s' constant. W LIBG-221 Cell %s, referred to by cell %s, does not exist. W LIBG-222 Cell %s, referred to by cell %s, is multibit. W LIBG-223 Cells %s and %s have different interfaces. W LIBG-224 Cell %s has unequal bus or bundle widths. W LIBG-225 Errors have been detected. The single_bit_degenerate\n\ \tattribute is removed from cell %s. W LIBG-226 Only cell %s has geometry_print %s. W LIBG-228 Failed to transform the function of cell '%s' to a netlist. The cell becomes a black box for Formality. W LIBG-229 Cell '%s' has non-disjoint input. W LIBG-230 Internal pin '%s' is dangling. The pin is removed. I LIBG-231 Internal pin '%s' is for dcm timing. E LIBG-232 The 'function' attribute on the '%s' internal Pin/bus of the\n\ \t'%s' cell is not allowed. E LIBG-233 The 'clock_gate_enable_pin' attribute is defined on more than one\n\ \tpin in the '%s' cell. E LIBG-234 The '%s' cell cannot be used as a clock gating cell. E LIBG-235 The '%s' attribute is either not\n\ \tdefined on any pin in the integrated clock gated '%s' cell\n\ \tor it is defined on a wrong pin. E LIBG-236 The '%s' clock gate cell has the wrong number of pins. E LIBG-237 The '%s' clock gate cell has the wrong type of pins. E LIBG-238 The '%s' clock gate cell is not of type '%s'. I LIBG-239 The combinational timing arc from '%s' to\n\ \t'%s' is resolved into the three_state_enable type. W LIBG-240 The phase relationship of the outputs of cell '%s'\n\ \tis different from that of its test cell at line %d. E LICSVR-1 Variable '%s' has invalid value '%s'.\n\tAllowed values are: 'package', 'individual', 'package individual'\n\tand 'individual package'. E LICSVR-2 Could not obtain a license. E LICSVR-3 SYNOPSYS_DS is not set. You must set this environment\n\tvariable to the root of the installed Synopsys software. E LICSVR-4 DISPLAY is not set. You must set this environment\n\tvariable before running the Synopsys software. E LICSVR-5 Can't initialize the license server. E LICSVR-6 The Synopsys License Server has crashed. E LINK-1 Can't find %s port '%s' on reference to '%s' in '%s'. E LINK-2 Too many ports on reference to '%s' in '%s'. E LINK-3 Width mismatch on port '%s' of reference to '%s' in '%s'. E LINK-4 Too few ports on reference to '%s' in '%s'. W LINK-5 Unable to resolve reference '%s' in '%s'. E LINK-6 Could not find pin '%s' on design '%s' for cell '%s'. E LINK-7 Recursive hierarchy detected in design '%s'. E LINK-8 Cannot resolve enumeration for cell '%s' on design '%s'. W LINK-9 Unable to resolve reference to synthetic module '%s' in '%s'. E LINK-10 '%s' was not identified as a synthetic library module\n\ \tand could not be successfully elaborated from design library '%s'. E LINK-11 Unconstrained port '%s' in design referenced by '%s' in '%s'.\n\ \tThis version does not support unconstrained ports. W LINK-12 Unable to find library '%s'. This was probably caused by bad Synopsys installation. W LINK-13 design library '%s' was used in design '%s'\n\ \tbut it was never defined. Ignoring. W LINK-14 Instance of '%s' is defined in both libraries\n\ \t'%s' and '%s', which are both visible in design '%s'.\n\ \tThe first library will be used. E LINK-15 Cannot continue with auto_link disabled. Set 'auto_link_disable = false'. W LINK-16 Parameter mismatch in linking reference '%s' by name.\n\ \tLinked to '%s', which has the correct parameters. W LINK-17 Design '%s' was renamed to '%s' to avoid\n\ \ta conflict with another design that has the same name but\n\ different parameters. W LINK-18 Parameter mismatch in linking reference '%s' by name.\n\ \tCan't find design. W LINK-19 "Port '%s' was unresolved on reference to '%s' in \ '%s'. W LINK-20 "Attempting to resolve reference '%s'\n\ \tfrom non-synthetic design library '%s'. W LINK-21 Design '%s' has %d extra %s port(s) than \n\t reference '%s' in '%s'. E LINK-22 Reference '%s' in '%s' is a preserved function and \n\t cannot have inout ports. E LINK-23 Design '%s' used to resolve reference '%s' in \n\t '%s' is a external netlist and cannot have inout ports. E LINK-24 Port '%s' of reference '%s' in '%s' \n\t is connected to port '%s' of the external netlist '%s'. \n\t The directions of these two ports are not compatible. W LINT-0 In design '%s', input pin '%s' of cell '%s' was left unconnected. %s assumed. W LINT-1 In design '%s', cell '%s' does not drive any nets. W LINT-2 In design '%s', net '%s' driven by pin '%s' has no loads. W LINT-3 In design '%s', net '%s' has no drivers. %s assumed. I LINT-4 In design '%s', net '%s' has multiple drivers. Wired AND assumed. E LINT-5 In design '%s', output port '%s' is not driven (inconsistent hierarchy). W LINT-6 In design '%s', input port '%s' drives wired logic.\n\ (port-direction may have been specified incorrectly.) E LINT-7 Recursive hierarchy detected in design '%s'. W LINT-8 In design '%s', input port '%s' is unloaded. W LINT-10 In design '%s', cell '%s' has no output pins. F LINT-11 In design '%s', db_object '%s' does not have a '%s' attribute. F LINT-12 Unable to db_gen_init '%s' from db_object '%s'. E LINT-20 In design '%s', cell '%s' does not have a reference. F LINT-21 Unable to db_new_attribute to db_object '%s'. W LINT-22 In design '%s', ref '%s' was not used. F LINT-23 Unable to remove attribute '%s' from db_object '%s'. W LINT-25 Design '%s' does not have any output ports. F LINT-26 Unable to db_set_attribute to db_object '%s'. E LINT-27 Object '%s' is not of class dd_design, and should not be seen by db_lint. W LINT-28 In design '%s', port '%s' is not connected to any nets. W LINT-29 In design '%s', input port '%s' is connected \ directly to output port '%s'. W LINT-30 In design '%s', %s. W LINT-31 In design '%s', output port '%s' is \ connected directly to output port '%s'. W LINT-32 In design '%s', a pin on \ submodule '%s' is connected to logic 1 or logic 0. W LINT-33 In design '%s', the same net is \ connected to more than one pin on submodule '%s'. W LINT-34 In design '%s', three-state bus '%s' has \ non three-state driver '%s'. I LINT-35 In design '%s', net '%s' has multiple \ drivers. Wired OR assumed. W LINT-38 In design '%s', net '%s' has multiple \ drivers (unknown wired-logic type). W LINT-39 In design '%s', net '%s' has %s \ emitters, exceeding the maximum of %s. W LINT-40 In design '%s', net '%s' has drivers with \ conflicting wired connection classes. W LINT-41 In design '%s', pin '%s' is not allowed \ to drive wired logic. W LINT-42 In design '%s', pin '%s' is not allowed \ to be driven by wired logic. I LINT-44 In design '%s', %s. W LINT-45 Design '%s' is instantiated %d times. W LINT-46 Design '%s', cell '%s', pin '%s' is illegally connected,\n\ \tsince primary output '%s' is unconnected. W LINT-47 In design '%s' net '%s' has a \ connection class violation: I LINT-99 Use the 'check_design' command for \ \n\t more information about warnings. W LINT-100 The design does not have back-annotated delays. W LINT-101 Missing %s delay annotation between pins '%s' and '%s' on cell '%s'. W LINT-102 The design does not have back-annotated cluster assignments. W LINT-103 Missing cluster annotation on cell '%s'. W LINT-104 The design does not have back-annotated cell locations. W LINT-105 Missing cell location for cell '%s'. W LINT-106 Missing %s delay annotation from pin '%s/%s' to pin '%s/%s' on net '%s'. W LINT-107 The design does not have back-annotated net capacitances. W LINT-108 Missing capacitance annotation on net '%s'. W LINT-109 Missing orientation annotation on cluster '%s'. W LINT-110 Missing bounding box for cluster '%s'. W LINT-111 Missing %s delay annotation for \fIsetup\fP arc from pin '%s' to pin '%s' on cell '%s'. W LINT-112 Missing %s delay annotation for \fIhold\fP arc from pin '%s' to pin '%s' on cell '%s'. W LINT-113 Missing %s delay annotation for 'preset' or 'clear' timing arc from pin '%s' to pin '%s' on cell '%s'. W LINT-114 Missing %s delay annotation from port '%s%s' to pin '%s/%s' on net '%s'. W LINT-115 Missing %s delay annotation from pin '%s/%s' to port '%s%s' on net '%s'. W LINT-116 Missing %s delay annotation from port '%s%s' to port '%s%s' on net '%s'. W LINT-117 The design does not have any back-annotation information. W LINT-118 The design has '%d' cells which do not have cluster\ annotation on them. The cells with missing annotations represent '%f'\ of all cells. W LINT-119 The design has '%d' cells which do not have locations\ annotation on them. The cells with missing annotations represent '%f'\ of all cells. W LINT-120 The design has '%d' cells annotated with \ clusters which have no orientation. The cells with this type of missing \ annotations represent '%f' of all cells. W LINT-121 The design has '%d' cells annotated with \ clusters which have no bounding box. The cells with this type of missing \ annotations represent '%f' of all cells. W LINT-122 The design has '%d' cells which have missing delay\ arc annotations. The cells with missing annotations represent '%f'\ of all cells. W LINT-123 The design has '%d' nets which have missing delay\ arc annotations. The nets with missing annotations represent '%f'\ of all nets. W LINT-124 The design has '%d' nets which do not have\ capacitance annotation on them. The nets with missing annotations \ represent '%f' of all nets. E LNK-001 Cannot read link_path file '%s'. I LNK-002 Design '%s' is already linked. I LNK-003 Design '%s' was not successfully linked:\n \t%d unresolved references. E LNK-004 Unsupported LSI reference '%s' to '%s'\n\ \tcannot be resolved W LNK-005 Unable to resolve reference to '%s' in '%s'. W LNK-006 Cannot resolve instance %s/%s (%s). E LNK-007 Cannot instantiate design '%s' in '%s'. E LNK-008 Cannot find port '%s' on design '%s', referenced by instance '%s'. E LNK-009 Reference '%s' to '%s' is missing the following ports:\n\ \t%s. E LNK-010 Too few ports on instance '%s' of '%s' in '%s'. E LNK-011 Too many ports on instance '%s' of '%s' in '%s'. E LNK-012 Width mismatch on port '%s' of reference to '%s' in '%s'. E LNK-013 Could not resolve %s port '%s' of reference to '%s' in '%s'. E LNK-014 Could not resolve direction of port '%s' of reference to '%s' in '%s'. W LNK-015 Could not swap '%s' ('%s') with '%s'%s. I LNK-016 Swap failed due to previous errors. E LNK-017 No design matched '%s'. E LNK-018 Cannot swap cells; design is not linked. E LNK-019 Can only swap in a single target design. E LNK-020 Cannot swap in '%s': it is the current design. I LNK-021 Previous messages occurred while trying to do:\n\ \t'%s'. W LNK-022 In design '%s', input pin '%s' of cell '%s' was left unconnected. E LNK-023 Recursive hierarchy detected in design '%s':\n%s. I LNK-024 All timing information (backannotation, exceptions, etc.)\n\ \tis being removed from design '%s'. User-created annotations\n\ \tmust be restored after relinking this design. I LNK-025 Link interrupted. Unlinking design: please wait... E LOGDB-0 Design is currently not represented as a PLA. E LOGDB-1 Cells at the current level of the design are not combinational. E LOGDB-2 Cannot write out design with INOUT ports. E LOGDB-3 Cannot write out design with ports with unknown direction. W LOUT-1 %s '%s' is renamed to '%s' in\n\ design '%s' because it isn't a legal name. W LOUT-2 %s '%s' is renamed to '%s' in\n\ design '%s' because of %s of the same name. W LOUT-3 Pin '%s' on cell '%s' has no direction. Not written. I LOUT-4 Net '%s' is renamed to '%s' in\n\ design '%s' because it's connected to the port by that name. W LOUT-5 The name of net '%s' in design '%s'\n\ can't be changed to the name of both ports '%s'\n\ and '%s' to which it's connected. W LOUT-6 Direction of port '%s' in design '%s' is unknown.\n\ It will not be declared as a port in the output LSI/NDL netlist. E LOUT-7 (Internal error) Pin '%s' cannot be found in cell '%s'.\n E LSIN-1 Can't open the input file. W LSIN-2 File %s [ Line %d ]:\n\ '%s' is not supported as an NC value .This is being reset to '0' [logic zero] E LSIN-3 File %s, line %d: Mixed explicit and implicit connections. E LSIN-4 File %s, line %d: Module '%s' used inconsistently. E LSIN-5 File %s, line %d: Illegal %s specification. W LSIN-6 File %s, line %d: Unsupported NC connection. E LSIN-7 File %s, line %d: Component '%s' could not be found. E LSIN-8 File %s, line %d: Cell '%s' could not be added. W LSIN-9 File %s, line %d: %s port '%s' specified twice. W LSIN-10 The value of variable 'lsiin_net_name_prefix' isn't valid--using 'NET_'. E LSIN-11 File %s [ Line %d ]:\n\ %s is not a valid NC value. W LSIN-12 File %s [ Line %d ]:\n\ 'use_global' is not supported. E MEM-1 Pointer %s is not within the range of allocated memory. E MEM-2 A memory pad has been overwritten at 0x%x. E MEM-3 Pointer was never allocated, was already freed or\ was not allocated from an item free group. E MEM-4 Memory group structure is not intact. F MEM-5 Out of memory. W MEM-6 A call to SBRK has been made outside the memory allocator.\ This should be avoided. E MEM-7 %s E MENO-1 No schematic exists for design '%s'. E MENO-2 Design '%s' has no external_scale defined in its symbol library. E MENO-3 Design '%s' has no route_grid defined in its symbol library. W MENO-4 Design '%s' has no landscape defined; assuming landscape. E MENO-5 All pins on symbol '%s' in library '%s' must have same Y coordinate. E MENO-6 Net connector symbol '%s' in library '%s' has %d pins; two are required. W MENO-7 Sheet '%s' of design '%s' exceeds Mentor's maximum size of %0.2f. E MENO-8 Off-sheet connector symbol '%s' has no name text. E MENO-9 Port symbol '%s' has no name text. E MENO-10 Symbol '%s' has no name text. W MENO-11 Cannot fix feedthroughs on sheet '%s'; no NETCON symbol found. W MENO-12 Symbol '%s' exceeds Mentor's maximum size of %0.2f. E MENO-13 Pin '%s' of symbol has unknown direction. W MENO-14 Unable to fix all feedthroughs on sheet '%s' of design '%s'. I MENO-15 Instance of connector symbol '%s' is being treated as a port. I MENO-16 Design '%s' had %d name changes. W MENO-17 Can't write symbol information for connector '%s'. E MENO-18 Can't find the symbol libraries attached to design '%s'.\n\ Check the value of the 'search_path' variable. E MENO-19 Can't write out a bussed design '%s'. E MENO-20 No schematic or symbol exists for design '%s'. I MENO-21 Schematic '%s' might have been modified due to netcon insertion. W MENO-22 Symbol for cell '%s' in design '%s' is too large for the sheet. E MEXT-1 Input group '%s' not defined. W MEXT-2 Input '%s' is already synchronized in group '%s' - not redefined. W MEXT-3 Technology library does not specify max_transition for all pins.\n\tUsing 5.0. Set extract_max_transition to override default. W MEXT-4 Detected max_transition violation in the circuit to be extracted. W MEXT-5 Pin '%s' has no clock defined.\n\tIgnoring paths to and from this device. W MEXT-6 Environment variable '%s' has not been set during this\n\t\ session. Using default value '%s'. W MEXT-7 Environment variable 'extract_model_tolerance' has a value that is too low.\n\tUsing minimum value '%s'. W MEXT-8 Environment variable 'extract_tolerance' has a value which is unreasonably high.\n\tUsing maximum value '%s'. E MEXT-10 Unknown format '%s' for the -output_format option E MEXT-11 Invalid operating condition '%s' specified. W MEXT-12 Pin '%s' is an internal start\n\ \t or end point. Ignoring paths to and from this pin. E MEXT-13 You must specify a list of input ports. E MEXT-14 You must specify either a group name \n\tor a list of input ports to clear. E MEXT-15 Some of the internal nets have RC annotation W MEXT-16 No clock path exists to pin '%s'.\n\tIgnoring paths to and from this device. I MGI-1 %s E MGI-2 %s W MGI-3 %s E MGI-4 Failed to create or open '%s'. E MGI-5 Could not execute shell command '%s'. E MGI-6 More than one %s files are found in '%s'. E MGI-7 No %s file is found in directory '%s'. E MGI-8 Design '%s' contains %s which is not allowed. E MGI-9 Failed to link design '%s' created by '%s'. E MGI-10 File '%s' is not an executable file. E MGI-11 Unauthorized '%s' file name '%s' is found in directory\n\ \t'%s'. E MGI-12 No dc_shell script is found in directory '%s'. W MGI-13 Design '%s' contains cells that are not in\n\ \tthe target library '%s', these cells will be re-mapped to '%s'. E MGI-14 Unable to spawn a child process for the generator\n\ \t'%s' specifed within the '%s' synthetic library. E MGI-15 Unable to properly subinvoke generator '%s'. E MGI-16 Incorrect type for argument '%s' is detected in\n\ \tthe '%s' command. W MGI-17 Incorrect syntax detected in the '%s' command at '%s'. E MGI-18 Unrecognized return status code from generator %s. E MGI-19 %s exited with an error condition. Please see directory\n\ \t'%s' for more information. E MGI-20 Failed to communicate with generator %s via IPC. See\n\ \tdirectory '%s' for more information. E MGI-21 User interrupted execution of generator %s. E MGI-22 Generator %s failed to generate %s. Please see directory\n\ \t'%s' for more information. E MGI-23 Time out for generator %s. E MGI-24 Command string, '%s', exceeds the allowable length ('%d') when communicating with generator from the '%s' synthetic library. W MGI-25 The path '%s' specified by variable \ '%s' cannot be found. E MGI-26 The directory '%s' cannot be created. W MGI-27 The directory '%s' cannot be removed. W MGI-28 The library '%s' cannot be written to\n\ \t'%s'. E MGI-29 Invalid Module Compiler installation. W MIF-1 %s E MIF-2 %s F MIF-3 %s F MIF-4 %s E MODEL-1 The scaled cell model and the original model saved in the \ db file %s are different E MODEL-2 Port name %s found in %s design is not\n\ found in %s design (operating_condition - %s). W MODEL-3 Replacing the scaled cell which is already present for\n\ the operating condition %s E MODEL-4 The cell %s is not an ITS model E MODEL-5 The design %s does not instantiate a PT model I MODEL-6 Min delay arc from '%s' to '%s' missing for\n,\ \toperating_condition '%s', substituting with a max_delay arc. E MODEL-7 Cannot open file %s for writing. W MODEL-8 The arc from '%s' to '%s' is not being written\n\ \tout. E MODEL-9 Option '-remove_internal_arcs' cannot be used\n\ \twithout the '-library_cell' option. W MODEL-10 Option '-test_design' is valid only with\n\t\ option '-library_cell' W MODEL-11 Trying to update a library %s which is not present. E MOUI-1 Could not create menu item: '%s'. E MOUI-2 Widget name conflict: %s. E MOUI-3 Dialog %s is not posted. E MOUI-4 Could not read bitmap file: '%s'. F MOUI-5 Could not create the designs view.\n\ \tYour generic symbol library may be old or non-existent. E MOUI-6 Could not create viewer log file: '%s'. E MOUI-7 Minimum rise time must not be greater that maximum rise time. E MOUI-8 Minimum fall time must not be greater that maximum fall time. E MOUI-9 Unable to push into design %s E MOUI-10 Unable to open file: %s E MOUI-11 '%s': is a file. Choose a directory name. E MOUI-12 '%s': No write permission. Choose another directory. E MOUI-13 Please specify an output file name. E MOUI-14 Background '%s' task '%s' has exited abnormally. E MOUI-15 You cannot execute '%s' because it is the current view_log_file. E MOUI-16 No design has been selected to plot. E MOUI-17 Can't plot design '%s' because the schematic could not be created. E MOUI-18 No plot file specified. E MOUI-19 Specified selecting color '%s' is not a valid color. E MOUI-20 Only schematics can be plotted. E MOUI-21 Additional errors suppressed.\n\ \tSee the Command Window for a full error message listing. W MOUI-22 Unable to execute watcher process: '%s'. E MOUI-23 HDL library '%s' does not exist.\n\t\tClick on "Create New Library if it Doesn't Exist"\n\t\tin the "Analyze File" dialog to override this error E MOUI-24 Command %s requires at least one selected object. I MOUI-25 Multi-lined command flushed. E MOUI-26 Command incomplete. Command ignored. E MOUI-27 Can't invoke Design Analyzer because the value of\n\ \tthe %s variable contains options\n\ \twhich are ambiguous. Please fix the value of this variable in\n\ \tyour initialization file and re-invoke Design Analyzer.\n\ \tTo see the valid options to create_schematic, use\n\ \tthe help command in dc_shell. E MOUI-28 Unable to Highlight Selected object(s). W MOUI-29 Ignoring the value of the variable default_schematic_options\n \ \tbecause it is incorrect. Type 'help create_schematic' in the\n\ \tCommand Window or 'create_schematic' in the Help->Commands\n\ \tdialog box for a description of the options to the\n\ \tcreate_schematic command. E MOUI-30 String required for the option(s) : %s. E MOUI-31 Invalid instance name: '%s'. W MOUI-32 '%s' does not have a schematic object. F MUTIL-1 Could not create menu item '%s'. F MUTIL-2 More than one menu item has the name '%s'. F MUTIL-3 Could not open menu files. E NG-1 Generation error: %s (%s). E NMA-1 Collapse name space rule conflicts with equal ports/nets rule. E NMA-2 Negative max_length rule '%d' is invalid. E NMA-3 Max_length rule '%d' is invalid; it must be greater than 8. E NMA-4 Special rules '%s' is invalid. E NMA-5 Range specified in string '%s' is invalid. E NMA-6 Replacement character '%c' is invalid.\n\ \tIt is not an allowed character according to existing rules. E NMA-7 String '%s' is invalid; at least 10 chars must be allowed. I NMA-8 %d names changed in design '%s'. I NMA-9 No names changed in design '%s'. E NMA-10 A %s named '%s' already exists in design '%s'. E NMA-11 name mapping string '%s' illegal. E NMA-12 name mapping pattern string '%s' illegal. W NMA-13 Variable "bus_naming_style" is not defined. Use "%s" in change_names command. W NMA-14 Variable "bus_naming_style" contains characters that are not defined within \ the "-allowed" character set in current name rule. They are found in the following type(s) \ of objects: "%s" W NMA-15 In design '%s', there exists duplicate reference '%s'.\n\ it ignores the second reference. W NMA-16 In design %s, %s bus member '%s' changed to '%s'. W NMA-17 File %s,\n\ \tline %d: Can't find %s '%s' in %s '%s'. W NMA-18 The variable "%s" was set to "%s" from "". E NMA-19 File %s, Line %d:\n\ \tAn expected delimiter '%s' is missing from the names file.\n\ \tReading of the file has been terminated. E NMA-20 File %s, Line %d:\n\ \tAn unexpected delimiter '%s' has been encountered in the names file. \n\ \tReading of the file has been terminated. W NMA-21 No valid name changes found in names file '%s'. E NMA-22 Too many errors in names file '%s'. I NMA-23 %d names changed using names file '%s'. W NMA-24 File %s,\n\ \tline %d and\n\ \tFile %s,\n\ \tline %d : Unsupported multiple names files.\n\ \t%s '%s' was the new name of %s '%s' in %s '%s'. E NMA-25 Can't open names file '%s'. W NMA-26 File %s,\n\ \tLine %d: ObjectType: %s\n\ \tBusMemberName: '%s' BusPortName: '%s'\n\ \tchange_names cannot be applied to individual bus members.\n\ \tPlease specify the BusPortName instead. W NMA-27 File %s,\n\ \tline %d: Can't find %s name '%s'. W NMA-28 File %s, line %d and\n\ \tFile %s, line %d \n : duplicate change for %s '%s'. \n\ \tThe previous change will be overwritten by the latest one. W NMA-29 File %s,\n\ \tline %d: unsupported class string '%s' in '%s'. E NMA-30 Invalid class string '%s'. E NMA-31 '%s' doesn't specify a unique %s\n\ \tPlease use complete specification: full_file_name:%s_name E NMA-32 Design '%s' is not in the system. W NMA-33 File %s,Line %d:\n\ \t A %s named '%s' already exists in design '%s'. E NMA-34 File %s, Line %d:\n\ \tAn incomplete line has been encountered in the names file. \n\ \tReading of the file has been terminated. E NMA-35 File %s, Line %d:\n\ \tThis line does not have any effect on changing names in the\ %s command. E NMA-36 Can't open names file '%s' for writing. W NMA-37 Multiple changes to '%s'. E NMA-38 Option target_bus_naming_style '%s' is invalid. W NMA-39 In design %s, %s bus member '%s' contains member '%s' with different base name. E OPT-100 %s terminated abnormally. E OPT-101 The target library does not contain an inverter.\n\ \tAn inverter is required for mapping. E OPT-102 The target library does not contain all required gates.\n\ Either a NOR, or an AND and an OR gate (two-input) is required for mapping. I OPT-103 Verification Failed. I OPT-104 Verification is too expensive...unable to complete. I OPT-105 Flattening is too expensive...unable to complete.\n Total Endpoints: %d Endpoints unable to be flattened: %d W OPT-106 Cell %s conflicts with the %s in the target library. W OPT-107 Cell %s conflicts with another %s in the same design. I OPT-108 Design '%s' has no optimization constraints set. W OPT-109 In design %s, there are sequential cells not driving any load. W OPT-110 %s libraries have conflicting technology types.\n\t%s '%s' has technology '%s',\n \tand %s '%s' has technology '%s'. W OPT-113 %s libraries have conflicting delay models.\n \tLibrary '%s' has delay model '%s',\n \tand library '%s' has delay model '%s'. E OPT-114 Delay model '%s' in library '%s' is not supported. W OPT-115 The target library '%s' was compiled with a version 1.1\n\ \tLibrary Compiler; this version has a known bug when compiling\n\ \tmultiple-output combinational gates.\n\ \tTo avoid this problem, either obtain a version of this library which\n\ \twas compiled with version 1.2 or greater, or use the 'dont_use'\n\ \tcommand to disable all of its multiple-output combinational gates. W OPT-116 The target library '%s' was also compiled using version 1.1. I OPT-119 Compatibility version is less than '%s'. I OPT-120 Compile will ungroup all hierarchy that is not 'dont_touch'. I OPT-121 Replacing three-state busses with multiplexed busses. I OPT-122 Unable to remove three-state busses from design '%s'. E OPT-123 Unable to verify the two designs because at least \n\ \tone of the designs contains a state table. E OPT-124 Use the 'uniquify' command to fix multiply instantiated \ designs. I OPT-125 Unable to map three-state cells. I OPT-126 Leaving generic three-state cells in design. E OPT-127 Designs which contain synthetic library parts cannot be %s when\n\t'synthetic_library' is not specified or synthetic libraries are disabled. E OPT-128 There are conflicts between cells in libraries %s:%s (%s) and %s:%s (%s). W OPT-129 The three_state bus '%s' drives more than one port\n\ and cannot be split apart because at least one of the ports is an inout\n\ mode port. W OPT-130 The cell '%s' has no drive (drive == 0.0)\n\ and therefore no net driven by that cell will be buffered. W OPT-140 Could not buffer the multiple port net %s because\n\ \tdoing so would increase the connection class violation of the design. I OPT-150 Timing loop detected. I OPT-151 %s interrupted. Saving intermediate design. W OPT-153 Unable to maintain nets '%s' and '%s' as separate \ entities. E OPT-155 ECL technology libraries are not supported. W OPT-156 max_power attribute is ignored on non-ECL designs. E OPT-157 Cannot perform reoptimize_design with generic\n\ \tlogic which is not dont_touched. Use report_cell to list unmapped \ \tcells in the design. E OPT-160 Unable to model design '%s'. W OPT-161 Text file for model '%s' contains illegal or incomplete library compiler code. E OPT-162 Model can only currently handle busses which are arrays of bits. E OPT-163 Library '%s' must use the same technology as design '%s' to add a model. I OPT-170 Changed wire load model for '%s' from '%s' to '%s'. I OPT-171 Changed minimum wire load model for '%s' from '%s' to '%s'. W OPT-180 File '%s' already exists; appending to the end of it. E OPT-181 Could not open file '%s' for writing. E OPT-190 Must have an expert license to use 'compile -in_place'. E OPT-191 Must have an expert license to use 'balance_registers'. E OPT-192 Must have a Design Compiler Expert license to use complex clocking. W OPT-193 Must have a Design Compiler Expert license\n\ \tto use 'balance_registers'. I OPT-194 Expert license required for latch time-borrowing. E OPT-195 Must have %s license(s) to use\n\ \t%s. E OPT-196 \ The target technology is '%s'. The design '%s' can only be optimized or mapped to an FPGA technology because either '%s' or at least one of its sub-designs was read or elaborated using the FPGA specific HDL-Compiler. The following design(s) in '%s' were read or elaborated by the FPGA specific HDL-Compiler: %s . E OPT-197 You must have a BOA-BRT license to run the\n\ \tpipeline_design or optimize_registers commands. W OPT-200 Library cell '%s' has a valid function-id,\n\ \tbut it has also been annotated with the user_function_class\n\ \tattribute. Resolving this conflict by ignoring the\n\ \tuser_function_class attribute for this library cell. W OPT-201 Library cells '%s' and '%s' have\n\ \tdifferent pin information, but they have been assigned the\n\ \tsame user_function_class. Resolving this conflict by ignoring\n\ \tthe user_function_class attribute on the latter library cell. W OPT-202 Variable '%s' is obsolete. W OPT-203 Library cells '%s' and '%s' have\n\ \tdifferent function_id, but they have been assigned the\n\ \tsame clock_gating_integrated_cell attribute. Resolving\n\ \tthis conflict by removing the latter library cell from\n\ \tthe clock_gating class. E OPT-205 Inconsistent references found for cell '%s'. W OPT-206 The sequential library cell '%s' does not have any\ setup or hold timing arcs. E OPT-210 Variable '%s' is malformed near '%s' and will be ignored. I OPT-220 Switching to base optimization engine for the current compile run. W OPT-221 The new optimization engine might not produce the best results for the specified target library. W OPT-306 Could not find %s '%s' in design '%s'. W OPT-309 Design '%s' contains unmapped cells.\n\ \tUse report_cell to list unmapped cells in the design. W OPT-314 Disabling timing arc between pins '%s' and '%s' on \ cell '%s'%s W OPT-318 Inserting delay to fix %s violation of %.2f at %s '%s'. I OPT-319 Complementing port '%s' in design '%s'.\n\ \t The new name of the port is '%s'. W OPT-320 Illegal value for variable port_complement_naming_style. \ Inverter optimization disabled for design '%s'. W OPT-403 Could not find cell '%s' in design '%s'. W OPT-407 There are no unconnected '%s' pins with signal type '%s' in block '%s.' W OPT-408 No associated_clock found for clocked_on_also %s '%s' in block '%s'. W OPT-450 Could not find net '%s' in design '%s'. E OPT-455 This design has no %ss for distribute_capacitance. W OPT-460 Ignoring dont_touch on net '%s' because it is connected only to\n\ \t generic logic which must be mapped. Use all_connected to see net connections. W OPT-461 Dont_touch on net '%s' may be overridden by compile because it\n\ \tis connected to generic logic. Use all_connected to see net\n\ \tconnections. E OPT-462 The following net has multiple drivers which are logically\n opposite in function: '%s'\nThis is an illegal design. Type 'help OPT-462' for more details. W OPT-463 Deleting scan chain information from design '%s'. I OPT-470 Using 'high' timing effort. I OPT-471 Using 'low' timing effort. I OPT-472 Using fast delay calculation mode. W OPT-473 Cannot perform multibit optimization on '%s' '%s'. I OPT-600 Translate interrupted. Saving intermediate design. W OPT-601 No sequential cell of target library has synchronous set/reset inputs as required by cell '%s' W OPT-700 Dual-site technology attributes are inconsistent across libraries.\n\ \tThese attributes will be ignored. W OPT-800 Removing some annotated net capacitances from design '%s'. W OPT-801 Removing some annotated net resistances from design '%s'. W OPT-802 Removing some annotated pin to pin connect delays. W OPT-803 Removing annotated pin to pin cell delays. I OPT-804 Removing all annotated delays from design '%s'. W OPT-805 Net '%s' already has '%s' for annotated resistance. '%s' is discarded. W OPT-806 Net '%s' already has '%s' for annotated capacitance. '%s' is discarded. W OPT-807 Annotation on pin '%s' is invalid because its cell, '%s', is not a leaf cell. W OPT-808 Connect delays annotated to and from this pin are removed. W OPT-809 Cell delays annotated from this pin are removed. E OPT-810 Direction of pin '%s' cannot be of type '%s'. E OPT-811 Direction of port '%s' cannot be of type '%s'. W OPT-812 Object '%s' is invalid. It must be a pin of a leaf cell or a port. W OPT-813 Timing check annotated to and from this pin is removed. E OPT-814 Pins '%s' and '%s' are not on the same cell. W OPT-815 There is no '%s' timing arc between pins\n\ \t'%s' and '%s'. W OPT-822 Pins (or ports) '%s' and '%s' are not on the same net.\n\ The back-annotated data between these two objects is removed. I OPT-830 Removing annotated delays from pin '%s' to pin '%s'. I OPT-831 Removing delays annotated to pin '%s'. I OPT-832 Removing delays annotated from pin '%s'. I OPT-833 Deleted pin to pin delay values will be approximated via automatically annotated resistance. W OPT-834 There is no timing annotated between pin '%s' and pin '%s'. W OPT-835 Overwriting the %s delay between pin '%s' and pin '%s' with (%f). I OPT-836 Annotated delays on net/cells have been modified/deleted. W OPT-837 Design '%s' already has annotated delays, \n \ read_timing and set_annotated_delay only annotate worse delays. E OPT-850 %s '%s' has annotated delays already including load delay.\n Annotate delays including load delay or remove old annotated delays. E OPT-851 %s '%s' already has annotated delays, and these\ annotated delays do not include load delay. \n\ \tYou must either annotate delays without including load delay; or\ remove old annotated delays. W OPT-852 Use of the best_case_tree delay model during reoptimize_design -post_layout is discouraged. W OPT-853 Target library does not contain any 2-1 multiplexor. W OPT-854 Ignoring dont_touch attribute on cell(s) in multiplexor implementation '%s' E OPT-900 replace_fpga terminated abnormally. E OPT-901 replace_fpga interrupted. Saving intermediate design. W OPT-902 This site does not have an FPGA License. Trying to \ obtain a CMOS license and enable CMOS optimizations. NO FPGA SPECIFIC \ OPTIMIZATIONS WILL BE ENABLED ! E OPT-903 The technology of the target library is the Xilinx %s \ series FPGA. Optimization requires that the library contain the Xilinx \ programmable cell core cell(CLB). Either the CLB cell does not exist in the \ library or a dont_use attribute has been placed on the cell. W OPT-904 The replace_fpga command has already been run on this \ design, or sub-designs below this design. The proper methodology is to run \ replace_fpga AFTER this command. W OPT-905 The replace_fpga command has already been run on this \ design, or sub-designs below this design. Partitioning information created by\ replace_fpga may become invalid as a result. The proper methodology is to run \ replace_fpga AFTER this command. E OPT-906 The FPGA cell '%s' does not contain the proper instance specific configuration information. W OPT-907 Inverter Removal Optimization is being disabled because an FPGA license is not available. W OPT-908 FPGA-specific Library Component Optimization is being disabled because an FPGA license is not available. E OPT-909 The target technology is '%s'. Using fpga_shell or fpga_analyzer requires that the target technology be FPGA. E OPT-910 Target library must contain a usable N-input lut cell. W OPT-911 Target library contains multiple lut output marker cells. W OPT-912 replace_fpga is not valid for designs implemented\n\ \twith this target library. Use the '-force' option to override this message. E OPT-913 Aborting replace_fpga due to lack of a usable output marker cell. W OPT-914 No single bit degenerate for multibit library cell '%s'. W OPT-915 Cannot perform multibit optimization on '%s' '%s'. W OPT-916 Incorrect setting for bus naming style variables. W OPT-917 Losing member of multibit component '%s'. W OPT-918 Multibit library cell '%s' will not be used in multibit optimization. W OPT-919 Invalid value '%d' for environment variable '%s'; resetting it to '%d'. E OPT-920 Found an unmapped cell '%s' in the design. I OPT-931 Global routing high fanout non-ideal net '%s'. W OPT-932 High fanout net '%s' is skipped by global route. E OPT-1000 Need to insert a pad on port '%s' before compiling. E OPT-1001 Multiple tristate buffers are driving pad net '%s'. W OPT-1002 Example pad '%s' is not in the library. W OPT-1003 Exact pad '%s' is not in the library. W OPT-1004 No matching pad found for port '%s'; W OPT-1005 Relaxing user-specified IO pad constraints on port '%s' W OPT-1006 Pad '%s' connected to port '%s' is dont-touch. No optimization done. I OPT-1007 Insert_pads interrupted. Saving intermediate design. E OPT-1008 Insert pads terminated abnormally. W OPT-1009 Port '%s' has no net attached to it: no pad inserted. W OPT-1010 Output port '%s' is not driven: no pad will be inserted. W OPT-1011 Target library has no pads in it. No pads inserted. W OPT-1012 Design '%s' has no pad constraints. No pad inserted. W OPT-1013 Net '%s' is dont_touch (connected to port '%s'). No pad inserted. W OPT-1014 I/O pad attribute mismatch on port '%s' W OPT-1015 Connection class of port '%s' does not match that of any I/O pads. I OPT-1016 Remove_pads interrupted. Saving intermediate design. E OPT-1017 Remove pads terminated abnormally. W OPT-1018 Pad already present on port '%s'. No new pad inserted. W OPT-1019 Input port '%s' is not loaded: no pad will be inserted. W OPT-1020 Inout port '%s' not driven by a tristate element. Assumed to be an output port. W OPT-1021 Inout port '%s' assumed to be an input port. W OPT-1022 IO pad '%s' is unusable: unknown logic function. W OPT-1023 IO Pad '%s' ( '%s' ) has unknown logic function E OPT-1024 Cannot insert a pad to drive bidirectional port '%s' W OPT-1025 Multiple drivers for net '%s' I OPT-1100 Balance_buffer interrupted. Saving intermediate design. E OPT-1101 Balance_buffer terminated abnormally. W OPT-1102 Cannot find %s '%s' W OPT-1103 Pin (or port) '%s' has no net attached to it. I OPT-1104 A memory leak has been detected (%s). W OPT-1200 Library cell '%s' has INOUT port(s). Not considered for \ sequential mapping. W OPT-1201 Library cell '%s' could not be modeled for sequential mapping. W OPT-1202 Library cell '%s' has unknown behavior W OPT-1203 Combinational loop detected at '%s' during sequential mapping W OPT-1204 The cell '%s' will not be considered for \ sequential optimization. W OPT-1205 The register '%s' may not be optimally implemented\ because of a lack of compatible components with correct clock/enable phase. W OPT-1300 Location based buffer insertion disabled. W OPT-1301 Location based buffer removal disabled. E PARSE-1 %s: %s on line %d at or near '%s'. E PARSE-2 %s on line %d at or near '%s'. E PDEFP-1 The PDEF file contains cluster data for the design '%s'; \n\ \tthis cluster data cannot be annotated on the design '%s'. W PDEFP-2 The PDEFVERSION values we accept are '%s'. W PDEFP-3 The cluster '%s' has been duplicated; the most recently\n\ \tread description of the cluster will be kept, while all previous\n\ versions will be overwritten. W PDEFP-4 The cell instance '%s' does not exist. W PDEFP-5 The cell instance '%s' has already been listed under\n\ \tcluster '%s'; this previous classification will be overwritten. E PDEFP-6 %s at or near token '%s'. W PDEFP-7 The name of the cluster '%s' contains the character '/', \ which cannot be processed by dc_shell commands. W PDEFP-8 The cell instance '%s' is not a leaf cell. Its presence\n\ within this cluster will be ignored. E PDEFP-9 The subdesign '%s' of the current design '%s'\n\ \tcontains unmapped cells. The entire design must be fully mapped. W PDEFP-10 A percentage utilization less than 0.0 was specified. W PDEFP-11 A percentage utilization greater than 100.0 was specified. W PDEFP-12 No UTILIZATION has been specified; the MAX_UTILIZATION value\n\ cannot be correctly interpreted in its absence, so it will be ignored. W PDEFP-13 The attribute '%s' has been specified more than once for\n\ \tthe object '%s'; the new value will override the old. W PDEFP-14 The attribute '%s' has been specified with a value whose\n\ \ttype is not %s; this value will be ignored. W PDEFP-15 The wire_load '%s' for cluster '%s' could not be found. W PDEFP-16 The cell instance '%s' is not linked. Its presence\n\ \twithin this cluster will be ignored. W PDEFP-17 The attribute '%s' of %s '%s' \n\ \tis not recognized and will be ignored. W PDEFP-18 The attribute '%s' has been specified with an invalid\n\ \tvalue. The value must be %s. W PDEFP-19 The attribute '%s' has been specified more than once for\n\ \tthe cluster file %s; the new value will override the old. W PDEFP-20 Attributes ignored for hierarchical cell %s. W PDEFP-21 Invalid NAMEPREFIX index (%d) for cell %s. W PDEFP-22 Reading LOC attribute in a PDEF 1.x file. W PDEFP-23 There is no cluster information to write out. W PDEFP-24 The attribute %s %s will be not written out. W PDEFP-25 Obstruction size will be ignored in this version.\ use CLUSTER RECT attribute to represent the obstruction size. W PDEFP-26 The pin '%s' does not exist. W PDEFP-27 All the warnings will not print out when using -quiet. E PDEFP-28 The PDEF file does not contain core area data for the design '%s'. W PDEFP-29 Ignore unknown orientation '%s'. W PDEFP-30 Cells could be moved out of boundary. W PDEFP-31 The net instance '%s' does not exist. W PDEFP-32 The net instance '%s' has already been listed under\n\ \tcluster '%s'; this previous classification will be overwritten. W PDEFP-33 This obstruction becomes placement obstruction. \ Obstruction size will be ignored for placment obstruction.\ use CLUSTER RECT and CLUSTER X_BOUNDS/Y_BOUNDS attribute to represent the obstruction size. W PDIN-1 Ignore '%s'. W PDIN-2 Ignore '%s'. W PDIN-3 Ignore '%s'. W PDIN-4 The attribute '%s' is in relative coordinates. W PDIN-5 The attribute '%s' is in absolute coordinates. W PDIN-6 The attribute '%s' is treated as a user attribute. W PDIN-7 Inherited cluster attributes are not supported. E PLAI-1 Can't read file \"%s\". E PLAI-2 Illegal command at line %d. E PLAI-3 Port %s declared twice at line %d. W PLAI-4 Unknown value '%s' for .phase keyword.\n\ \tPositive phase will be used for all outputs. W PLAI-5 Unknown PLA type \"%s\" at line %d. W PLAI-6 Unknown command \"%s\" ignored at line %d. E PLAI-7 Design name must be specified at line %d. E PLAI-8 Ports incompletely specified at line %d. E PLAI-9 Mismatched number of inputs. E PLAI-10 Mismatched number of outputs. E PLAI-11 No product terms for PLA found in file. E PLAI-12 ON-set and OFF-set overlap. E PLAI-13 Mismatched number of outputs and phase values.\n\ \tPositive phase will be used for all outputs. E PLAI-14 Invalid character on or near line %d. E PLAI-15 Unknown port '%s' in .field statement at line %d. E PLAI-16 Invalid order of input and output ports at '%s' at line %d. E PLAI-17 The use of the percent operator has resulted in an ambiguous specification. W PLAI-18 Ignoring row at line %d since previous row(s) containing the percent operator cover all input conditions implied by this row. E PLAI-19 Ambiguous output values specified at lines %d and %d. E PLAI-20 Port %s declared twice. E PLAO-0 Design is currently not represented as a PLA. E PLAO-1 Cells at the current level of the design are not combinational. E PPLI-1 register RTL Net %s[%d:%d], because its individuals bits are not available" E PPLI-2 specify the path for the testbench module models in the\ $read_rtl_saif() command. E PPLI-3 Port %s Ignored." E PPLI-4 of memory. Cannot create more VCL links" E PPLI-5 " $set_toggle_region must always be done before toggle_stop" E PPLI-6 must always be done before calling on $toggle_stop." E PPLI-7 of memory. Cannot create DP Hash table/list." E PPLI-8 are 0 nets registered. This typically happens when \ the only input parameter provided has no ports and you requested the \ dp_top_ports_only option for non-recursive-port registration." E PPLI-9 must always be done before calling on $toggle_reset." E PPLI-10 %s with less than 2 connections ignored." E PPLI-11 module instance %s does not match the cell \ specification in the SAIF file. No sdpd info is registered for this \ instance." E PPLI-12 " $toggle_stop must always be done before toggle_report" E PPLI-13 "read_lib_saif() must be called before the \ $set_toggle_region() E PPLI-14 "read_rtl_saif() must be called before the $set_toggle_region() E PPLI-15 "set_toggle_reion() must be called before $toggle_start(). E PPLI-16 "You have to also include a RTL forward SAIF file using \ $read_rtl_saif() command because you included an MPM forward SAIF file. E PPLI-17 "set_gate_level_monitoring() must be called before $toggle_start(). E PPLI-18 "set_toggle_reion() must be called before $toggle_report(). E PPLI-19 "set_toggle_reion() must be called before $toggle_start(). E PPLI-20 consecutive $toggle_start() calls are not allowed. F PROC-1 PROC(%s): Could not start child. E PROC-2 Could not fork child process. E PROC-3 Could not connect to child process. E PROC-4 Could not establish child connection. I PROC-5 Child process returned unexpectedly. E PROC-6 Unknown host '%s'. E PS-1 Bad plot command '%s'. E PS-2 Bad plot command. E PS-3 Can't open plot file '%s'. W PSCH-1 Can't plot design '%s' because it doesn't have a schematic.\n\ \tYou can create a schematic using the create_schematic command. W PSCH-2 Can't plot design '%s' because it doesn't have a symbol view.\n\ \tYou can create a symbol using the create_schematic -symbol_view command. E PSYN-001 Design has synthetic cells. E PSYN-002 Design has unmapped cells. E PSYN-003 Command '%s' had an error while executing. Aborting. E PSYN-004 Technololgy data not supplied. E PSYN-005 Design %s has no associated physical design. W PSYN-006 Core area for block not defined. E PSYN-007 Port %s has no location. E PSYN-008 Cell %s has no location. E PSYN-009 Blockage %s has no dimensions specified. E PSYN-010 No site array specified. E PSYN-011 Site array has no rows specified. E PSYN-012 Row has no sites specified. E PSYN-013 PhysOpt license is not enabled. E PSYN-014 No physical library cell for library cell %s. E PSYN-015 Dimensions of library cell %s not specified. E PSYN-016 No physical pin for library pin %s/%s. E PSYN-017 No location specified for library pin %s/%s. E PSYN-018 Site %s is not defined in physical library. E PSYN-019 Dimensions of site %s are not specified. E PSYN-020 Spacing between sites is not a multiple of site width on rows. E PSYN-021 Could not read the following physical library: W PSYN-022 The library cell %s is not legal on some rows.\n\ \tThis can degrade the quality of the placement result. E PSYN-023 Site array has rows and columns specified at the same time. W PSYN-024 The '%s' cell in the '%s' technology library does not\n\ \thave corresponding physical cell description. W PSYN-025 The '%s' cell in the '%s' physical library does not\n\ \thave corresponding logical cell description. W PSYN-026 This physical library is missing '%s' technology information. E PSYN-027 Can not link logical library '%s' with physical library '%s'. E PSYN-028 Failed to link logical library '%s' with physical library '%s'. W PSYN-029 Failed to find any physical library. E PSYN-030 Failed to find physical cell '%s'. E PSYN-031 Failed to find physical cell pin '%s'. E PSYN-032 Site array has irregular rows specified. E PSYN-033 Site array has negative site count specified. E PSYN-034 Library has no associated physical library. W PSYN-035 No physical library specified. I PSYN-036 Linking logical library %s with physical library %s. E PSYN-038 Site array extends beyond core area. W PSYN-039 The '%s' cell in the '%s' technology library is being\n\ \tmarked as "dont_use". W PSYN-040 Cell '%s' is being marked as "dont_touch" because it has\n\ \ta "fixed placement" attribute. E PSYN-041 cannot place the block because it is over capacity (density is %5.1f%%). E PSYN-042 There are blockages that either lie either partially\n\ \tor completely outside the bounds of the block. W PSYN-043 There are some cells that are located on illegal locations.\n\ \tThese cells will be snapped to the nearest legal location. E PSYN-044 A legal Placement could not be found. E PSYN-045 The library pin %s/%s does not have consistent directions \n\ \tin the physical and logical library. W PSYN-046 The cell %s is multi-row high. This can degrade the quality of the placement result. E PSYN-047 Can not find sites in any physical library. W PSYN-048 Unrecognized distance unit in the physical library. Assumes 1um. W PSYN-049 Overwrite the given core area (%f %f) (%f %f) with the new core area (%f %f) (%f %f). W PSYN-050 The given core area (%f %f) (%f %f) is different from the the core area (%f %f) (%f %f) from the site array definition in the PDEF file. W PSYN-051 Can not find site %s in physical library. E PSYN-052 Error in argument '%s'. '%s'. I PSYN-053 '%s'. I PSYN-054 Use -verbose option to find more about the legality violations. W PSYN-055 Cell %s overlaps with a Cell %s. W PSYN-056 Cell %s overlaps with a blockage. W PSYN-057 Cell %s is not on a row. W PSYN-058 The pin direction of '%s' pin on '%s' cell in the '%s' technology\n\ \tlibrary is inconsistent with the same-name pin in the '%s' physical library. W PSYN-059 Initial Location does not exists for cell %s. E PSYN-060 Error in the Execution of Detailed Placer. E PSYN-061 A cell of type '%s' was illegal for all sites in the block. E PSYN-062 Unable to find legal locations for all multi-row cells. W PSYN-063 Some areas of the block have densities much greater than 100%%.\n\ \tOne example is rows %d to %d with a density of %.1f%% W PSYN-064 The average displacement of a cell after legalization is %.1f rows. E PSYN-065 The site array contains more than two types of rows\ based on their heights. W PSYN-066 This obstruction with (%f %f) (%f %f) is exceeding its parent cluster boundary (%f %f) (%f %f). W PSYN-067 The obstruction layer %d is treated as a placement obstruction. W PSYN-068 This row (%f %f) (%f %f) is exceeding the core area (%f %f) (%f %f). E PSYN-070 Specified phys_info_db '%s' has not be read in by the 'read_phys_info_db' command. E PSYN-071 Specified phys_info_db '%s' is not unique in memory. E PSYN-072 phys_info_db '%s' has no physical information, not a placed netlist. E PSYN-073 Cannot find hierarchy '%s' in phys_info_db '%s'. E PSYN-074 Cannot find hierarchy '%s' (under instance path '%s') in phys_info_db '%s'." I PSYN-075 Deriving physical timing model for design '%s'. E PSYN-076 Back annotation aborted. E PSYN-077 Bad value %d for %s. E PSYN-078 Cell %s has no location. E PSYN-079 Cell %s has location. E PSYN-080 No floorplan is defined for the current design for top-down or incremental physical synthesis. E PSYN-081 The lower-left corner coordinates are bigger than upper-right corner coordinates. E PSYN-082 The ungroup option has been disabled.\ Please use "ungroup -all -flatten" befor use "physopt". W PSYN-083 Customer wire load models are ignored in physical synthesis. E PSYN-084 Command %s should be issued before issuing command %s. E PSYN-085 The value of attribute %s is smaller than the value of the attribute %s. W PSYN-086 Net '%s' is connected to pad cell and other cells. I PSYN-087 Inheriting location from pad pin '%s/%s' to port '%s'. I PSYN-088 Setting a don't-touch on net '%s', because it is connected to a pad cell. F PT-001 %s is not enabled. E PT-002 Unrecognized feature name '%s'. I PT-003 You already have a '%s' license. E PT-004 You don't have a '%s' license to remove. E PT-005 Can't remove your '%s' license: %s. E PTE-001 There are no arcs from pin '%s' to pin '%s' on cell '%s'. W PTE-003 Some timing arcs have been disabled for breaking timing loops\n\ \tor because of constant propagation. Use the 'report_disable_timing'\n\ \tcommand to get the list of these disabled timing arcs. E PTE-004 The pin '%s', which is a generated clock pin, is either \ in a loop or is in the fanout of two clock sources. I PTE-005 Invalidating all auto-disabled timing arcs. E PTE-006 Cannot specify '%s' as the group name. W PTE-007 Attempt to remove a clock gating check that was not previously set.\ E PTE-008 No%s timing arc in cell '%s(%s)' from pin %s'%s' to pin '%s'. E PTE-009 No %s arcs from pin '%s'. E PTE-010 No %s arcs to pin '%s'. W PTE-011 No%s timing arc in cell '%s(%s)' with condition '%s' from pin %s'%s' to pin '%s'. W PTE-012 A non-unate path in clock network detected.\n\ Propagating noninverting sense for clock '%s'\n from pin '%s'. W PTE-013 Some clock relationships result in a common base period which require\n\ \t clock waveforms to be expanded more than 1000 times. PrimeTime limits \n\ \t clock waveforms expansion to be no more than 1000. Please check your \n\ \t clocks\ and apply set_false_path between unrelated clock domains. E PTE-014 No net timing arc from pin '%s' to pin '%s'. E PTE-015 Net delay from pin '%s' to pin '%s'\ncannot be \n\ \tannotated because of a timing assertion on hierarchical pin '%s'. I PTE-016 Expanding clock '%s' to base period of %.2f\n\ (old period was %.2f, added %d edges) I PTE-017 Inferring %d clock-gating checks. I PTE-018 Abandoning fast timing updates. E PTE-019 report_delay_calculation is not enabled for library '%s'. E PTE-020 The master clock %s has %d edges in a period. Cannot\n\ do frequency multiplication. E PTE-021 The generated clock '%s' is in the fanout of clock\n\ source %s. E PTE-022 Generated clock '%s' is not in the fanout of its \n\ master clock. W PTE-023 The generated clock '%s' has not been expanded,\n\ \tplease create its master clock. E PTE-024 The following generated clocks '%s' form a loop. E PTE-025 The master of the generated clock '%s' is not \n\ connected to any clock source. I PTE-026 Found %d generated clock master pins that are not \ connected to clock sources. I PTE-027 Found %d loops in the generated clock network. W PTE-028 The variables timing_disable_bus_contention_check \n\ and timing_disable_floating_bus_check are both set to true. Reverting the \n\ setting of these variables to the default (false) value. E PWR-1 Clock '%s' has not been created. E PWR-2 The static probability must have a value between\n\ \t0 and 1. Ignoring the specified value. E PWR-3 The toggle rate value must be non-negative.\n\ \tIgnoring the specified value. E PWR-4 The period value must be greater than 0.\n\ \tIgnoring the specified value. W PWR-5 -period and -clock option both specified. \ Using the value from -period. W PWR-10 Black-box output '%s/%s' has not\n\ \tbeen annotated with switching information. Using default values\n\ \tof (%f, %f) for static probability and toggle rate, respectively. W PWR-11 Breaking combinational loop at cell '%s'. This cell\n\ \twill be treated as a primary input for purposes of power estimation. I PWR-12 The derived %s value (%f) for the\n\ \tclock net '%s' conflicts with the value annotated\n\ \twith the set_switching_activity command (%f). Using\n\ \tthe %s value. E PWR-13 Target library(s) are not characterized for internal power. Compile with power constraints is NOT recommended. W PWR-14 Clock %s no longer exists. set_switching_activity \ will be discarded for net %s. I PWR-15 Net '%s' has a static probability\n\ \tvalue but no toggle rate. Estimating the toggle rate from the\n\ \tstatic probability. I PWR-16 Design '%s' does not have any dynamic\n\ \tpower information. Use the report_power command to perform a\n\ \tdynamic power analysis of the design. W PWR-17 There is set_max_%s_power constraint unit but the library is unitless. W PWR-18 There are conflicting set_switching_activity commands on %s %s. W PWR-19 There are %d set_switching_activity conflicts. E PWR-20 Object '%s' is not a %s. W PWR-21 The %s option must be positive. W PWR-22 The %s can only be used in\n\ \tconjunction with the %s. E PWR-23 '%s' is not a valid value for the '%s' option. I PWR-24 The target library(s) contains cell(s), other than black boxes, that are not characterized for internal power. I PWR-25 The design contains cell(s), other than black boxes, that are not characterized for internal power. W PWR-26 The library cells used by your design are not characterized for internal power. W PWR-27 The design %s has been mapped to the gate. rtl2saif only works on the pre-mapped GTECH level netlist. W PWR-30 The %s option cannot be used in conjunction\n\ \twith the %s option(s). The %s option is ignored. W PWR-31 No valid %s were specified in %s.\n\ \tIgnoring the %s. W PWR-32 Sort mode '%s' applies only to the %s option. E PWR-33 Transition_type must be either rising or falling. W PWR-34 %d incomplete rise or fall specifications for pin %s of cell %s. W PWR-35 Incorrect state-dependent static probability for cell %s. This state-dependent static probability is being ignored. W PWR-36 The static probabilities specified on cell %s add up to more than 1. These probabilities are being scaled. W PWR-37 The static probabilities specified on cell %s add up to less than 1. These probabilities are being scaled. W PWR-38 Overriding existing static probability for same condition on cell %s. E PWR-40 Unable to obtain a Power-Analysis license. E PWR-41 The '%s' command is not supported in dp_shell. W PWR-42 Unable to obtain a HighLevel-Power-Analysis license. W PWR-50 Switching activity has been annotated on nets connected to combinational logic. This information may be lost during a full compile. E PWR-51 Cannot read library %s. E PWR-52 Cannot find file name to write state and path dependent SAIF forward-anotation file. E PWR-53 Cannot open file %s to be written. E PWR-54 The number of library files and library paths must be the same. W PWR-55 The library does not contain any state/path dependent cells, or\ state/path dependent information is not needed in the SAIF file. No SAIF output file is \ generated. W PWR-56 The bus naming style specified, %s, is invalid. E PWR-57 Target libraries must be specified when running power analysis. E PWR-60 The time unit in the -unit option must be one of these: \n\ \ts, ms, us, ns, ps, fs. E PWR-61 The number in the -scale option must be positive. W PWR-62 The -unit option is not specified. By default, \n\ \tit is assumed to be ns. W PWR-63 The -scale option is not specified. By default, \n\ \tthe timing unit is scaled by 1. W PWR-64 The -strip option is obsolete in this release. DesignPower will \ use it as if the -instance option is specified. In the future, please use the -instance \ option. E PWR-65 You have specified both -instance and -strip options, but with\ different values. Please re-enter the read_sif command with -instance option only. W PWR-70 The cell %s does not comply with the bus naming style\ %s. W PWR-71 The bus naming style %s is not supported. E PWR-72 The path_dep option must be a pin or set of pins on cell %s E PWR-73 Specification of state-dependent toggle rate must be for only one pin. E PWR-74 Specification of state-dependent toggle rate must be for a pin. E PWR-75 The conditions in the state-dependent toggle rate must be in terms of pins on that cell. W PWR-76 The current static probability on %s is different from the existing one. Using new static probability. E PWR-77 Specification of a path-dependent toggle rate can only be for an output or inout pin. E PWR-78 The path_dep option must contain either input or inout pins. E PWR-79 The start and end point of a path must be different pins. W PWR-80 There is no defined clock in the design. W PWR-81 Sequential cell %s with no output activity annotation. E PWR-82 Incorrect toggle rate specification for %s. \n\ \tSpecification of state-dependent, path-dependent, or separate \n\ \tspecification of rise/fall toggle rates must be for a pin. E PWR-83 Specification of state-dependent static probability must be for a cell. E PWR-84 Specification of a path-dependent toggle rate must be for only one pin. E PWR-85 Specification of a path-dependent toggle rate must be for a pin. W PWR-87 The state or path dependent toggle rate \n\ \tspecification for pin %s of cell %s does not match the state\n\ \tor path dependent specification for the library cell. Ignoring user-specified information for this pin. W PWR-88 The path-dependent toggle rate specification for pin %s of cell %s is not complete, all of the related pins are not specified. W PWR-89 Multiple equivalent path-dependent toggle rate specifications for pin %s of cell %s. Ignoring all your toggle rate specifications for this pin. W PWR-90 There was an extra rise/fall toggle rate \n\ \tspecification for pin %s of cell %s. Because all of the state \n\ \tand path dependencies for this pin were already specified, this \n\ \tspecification is ignored. W PWR-91 The state or path dependent toggle rate \n \ \tspecification for pin %s of cell %s is not complete. All states \n\ \tand paths must be specified. Ignoring all user-specified toggle \n\ \trates for this pin. W PWR-92 Too many state or path dependent toggle rate specifications\ for pins %s of cell %s. Ignoring all user-specified toggle rates for this pin. W PWR-93 There is both a separate rise/fall and an average \ toggle rate specification for pin %s of cell %s. Because this library cell\ has a separate rise/fall internal power model, the average\ specification is ignored. E PWR-94 Cannot find file name to write RTL forward-annotation\ SAIF. E PWR-95 Cannot open file %s to be written. W PWR-96 There are sequential cells with no output activity annotation. E PWR-97 You have not set the environment variable\n\ \t'power_preserve_rtl_hier_names' to TRUE. The rtl2saif command\n\ \tcannot proceed. E PWR-98 There must be a toggle rate or static probability specified when you specify the -toggle option. E PWR-99 You must provide -instance option to specify which instance\ in the SAIF file will be annotated onto the current design in the dc_shell. E PWR-100 The state dependent condition cannot contain the pin that has the switching activity specified. I PWR-105 Not clock-gating register %s since -minimum_bitwidth \ constraint is violated after splitting. W PWR-106 The -max_fanout option will be ignored \ unless the variable %s is set to TRUE. E PWR-107 The value of -max_fanout (%d) cannot \ be less than the value of -minimum_bitwidth (%d). W PWR-108 The register %s could not be considered for splitting \ since the variable %s is not set to TRUE. E PWR-109 The max_fanout value cannot be non-positive: %d. W PWR-110 The setup/hold time for the clock gate \ is negative: %s. E PWR-111 The minimum register bank size \ cannot be negative: %d. E PWR-112 The circuitry specified for gating the \ clocks of %s-edge triggered registers does not match the \ specified latch style. E PWR-113 The gate %s specified for clock gating \ has multiple outputs. This is not allowed. E PWR-114 The gate %s specified for clock gating \ is not a %s. E PWR-115 The cell list specified for clock \ gating is too short: %s. E PWR-116 The cell list specified for clock \ gating is too long: %s. E PWR-117 The pre gate specified for the \ clock gating circuitry has an invalid function %s. E PWR-118 The main gate specified for the \ clock gating circuitry has invalid function %s. E PWR-119 The post gate specified for the \ clock gating circuitry has invalid function %s. E PWR-120 Clock gating cannot be performed \ if no clock gating style has been set. E PWR-121 The gate %s specified for clock gating \ does not have the correct number of %d input pins. E PWR-122 The gate %s specified for clock gating \ does not exist in the target library. W PWR-123 The enable signal of flip-flop %s \ is computed by circuitry which is fed by flip-flops triggered \ by different edges. Clock gating will not be applied to \ the current flip-flop. W PWR-124 The enable signal of flip-flop %s \ is computed by circuitry which is fed by a design input port. \ Clock gating will not be applied to the current flip-flop. W PWR-125 The enable signal of flip-flop %s \ is computed by circuitry which is fed by flip-flops triggered \ by unknown edges. Clock gating will not be applied to \ the current flip-flop. E PWR-126 The clock gating style is incorrect. E PWR-127 Incorrect specification of the \ control point in the clock gating style. E PWR-128 Incorrect specification of the \ control signal in the clock gating style. E PWR-129 The observability logic's xor tree \ depth did not have a non-negetive value. E PWR-130 The sequential cell is neither none \ nor latch: %s. W PWR-131 With the specified clock gating style, \ an inverter will be created to connect the ENCLK pin of the \ clock gating circuitry with the clock pin of the register \ block. W PWR-132 The clock gating style was \ not changed. E PWR-133 Incorrect specification of the \ observability point in the clock gating style. W PWR-134 No warnings will be given \ about testability implications of clock gating style. W PWR-135 Clock pins of flip-flops \ are not controllable after clock gating. W PWR-136 Clock gating signals will \ not be observable. W PWR-137 The test clock waveform \ must be compatible with the clock gating cell. W PWR-138 For this scan style, the \ clock gating style need not specify a control point. E PWR-139 The library cell %s specified for clock gating \ has the dont_use attribute set, but not the is_clock_gating_cell \ attribute. W PWR-140 Command was called without \ an option and has no effect. E PWR-141 The pin specification \ for the clock gate is incorrect. E PWR-142 The operand isolation style is not set. E PWR-143 Operand isolation style is incorrect. W PWR-144 The operand isolation style was not changed due to\ errors. E PWR-145 The percentage area penalty allowed cannot be negative. E PWR-146 The logic specified for operand isolation is not valid. E PWR-147 The operand isolation logic list is too short. W PWR-148 Isolation operations list is empty. W PWR-149 Conflict between included and excluded isolation\ operations. E PWR-150 Syntax error in MPML file. E PWR-151 Error in executing the code in an MPM. E PWR-152 Error while linking MPM with design object. E PWR-153 Error while calculating library information. E PWR-154 No library name specified in the parameter for\ -mpm_name option. E PWR-155 One and only one option (-prop_sa|-sim|-dynamic_power|\ -static_power) can be used with the \fBtest_mpm\fP command. E PWR-156 Wrong combination of options while defining association.\ The -remove cannot be used with the %s option. E PWR-157 Wrong combinations of options for the load_mpm command.\ One, and only one of the two options -compile_only and -mpm_name can be used. \ The -newlib option can be used only with the -mpm_name option. E PWR-158 MPM %s not found in library %s. E PWR-159 %s file %s not found. E PWR-160 The design contains cells other than combinational\ ones. E PWR-161 Unable to write to file %s. W PWR-162 The switching activity propagation model is too large. E PWR-163 Internal error in the MPM module. E PWR-164 MPM %s already exists in the library %s. E PWR-165 Cannot use -remove option with -mpm_name option. E PWR-166 Cannot use -remove option with -reference option. E PWR-167 Neither -referene nor -remove option specified. E PWR-168 Neither -mpm_name nor -remove option specified. E PWR-169 Wrong combinations of options for the load_mpm \ command. The -newlib option has to be used with the -mpm_name option. E PWR-170 The %s with name %s that was \ specified for clock gating only has inverted outputs. I PWR-171 The library cell %s specified for clock gating \ has the dont_use and the is_clock_gating_cell attribute set. E PWR-173 Creating a reference for the library \ cell %s is not possible since another reference with the same \ name exists already. E PWR-174 Library %s already exists in memory. E PWR-175 Cannot use -newlib option for a library \ which already exists in memory. W PWR-180 There is no %s cell in the target library,\ assuming 0 power for these cells E PWR-190 The library cell %s specified for use as an \ integrated clock gating does not exist in the libraries specified. E PWR-191 The library cell required for use as an \ integrated clock gating does not exist in the libraries specified. \ The required attribute is %s. E PWR-192 The library cell %s specified for use as an \ integrated clock gating does not have the correct value for the \ clock_gating_integrated_cell attribute. The attribute required is %s. E PWR-193 The library cell %s specified for use as an \ integrated clock gating does not have the \ clock_gating_integrated_cell attribute. The value required for this \ attribute is %s. E PWR-194 Invalid option for the set_clock_gating_style command. \ If you specify the "integrated" option for the -positive_edge_logic or \ -negative_edge_logic options, you cannot specify any inverters/buffers \ before or after it. W PWR-195 The setup and hold values are ignored for the \ integrated cell. For these cells the setup and hold must be specified \ on the library. E PWR-196 The value of the "clock_gating_integrated_cell" \ attribute (%s) is not a valid value. Please correct this. E PWR-197 Could not find the exact pin matches with the \ integrated clock gating cell %s. E PWR-198 Could not find design port %s on the clock gating \ design %s. E PWR-199 Could not find the %s pin with the correct attribute \ on the specified integrated clock gating cell %s. W PWR-200 The DB design has existing user-annotated switching \ activity data. Not all such data is overwritten by the SAIF file. You may\ want to clean up user-annotated switching activity and read the SAIF file\ again. E PWR-201 Can't find the %s file (%s). E PWR-202 Currently, BC does not support the integrated clock gating cell. W PWR-203 Clock %s related to max_toggle_rate object %s\ no longer exists. W PWR-204 There are conflicting set_max_toggle_rate commands on\ object %s. I PWR-205 The derived max_toggle_rate value (%f) for the\n\ \tclock net '%s' conflicts with the value annotated\n\ \twith the set_switching_activity command (%f). Using\n\ \tthe %f value. W PWR-210 The clock gating design has more than one cell \ with clock-gating setup or hold attributes. Only of the setup and one \ of the hold attributes will be transfered to the integrated cell. E PWR-211 Object '%s' is not a net or cell. E PWR-212 -type option accepts only rtl or gate name. W PWR-213 The report_saif command was called without\ specifying either -type gate or -type rtl. Using the default (gate). E PWR-214 -input_list option expects -input . E PWR-215 -input_list option expects -weight . E PWR-216 Error in read_saif process. E PWR-217 Empty list in input_list option. E PWR-218 Weight value must be between 0 and 100. E PWR-219 The number of saif files is different of the number of weights in input_list. E PWR-220 The sum of weights must be 100. E PWR-221 The -only option cannot be used with -gated -ungated or the -gating_element options. I PWR-222 Producing default clock-gating report. I PWR-223 Skipping DRC option. I PWR-224 -simple_merge option is not set, default is -cps_propagation. E PWR-225 SDPD is not supported in this release. E PWR-226 SAIF files must have the same time unit. E PWR-231 No clock-gated register specified as an argument to the group_clock_gated_registers command E PWR-232 %s is not a clock-gated register. E PWR-233 Clock-gated registers do not belong to the same design instance. E PWR-234 Cannot use both -default and -exclusive options together. E PWR-240 Neither static_probability nor toggle_rate specified. E PWR-241 Invalid value %s for the -select option. E PWR-242 Invalid value %s for the -type option. I PWR-243 Resetting switching activity for the specified objects. E PWR-250 Specification of cell internal power must be for a pin. E PWR-251 Command %s not supported in pe_shell. W PWR-252 RTL-Power-Analysis license must already by checked\ out for this command to run, and you should be in pe_shell. W PWR-253 RTL-Power-Analysis license not available. E PWR-254 Error detected during read design. E PWR-255 Error detected during read constraints. E PWR-256 Error detected during creating models. E PWR-257 Error detected in reading switching activity. E PWR-258 Error detected during reporting RTL power estimation. E PWR-259 link_library not set or empty. E PWR-260 target_library not set or empty. E PWR-261 The option "-format" is required. E PWR-262 HDL designs required to read in. E PWR-263 The option "-top_design" is required. E PWR-264 Wrong instance name in -saif option. E PWR-265 Wrong SAIF name in -saif option. E PWR-266 SAIF name not found. E PWR-267 Activity file name not found. E PWR-268 -saif and -activity_file options are mutually exclusive. E PWR-269 -saif requires two names (saif_name and instance_name). E PWR-270 Value required for the '-saif' or '-activity_file' argument. E PWR-271 Only clock gating is supported with the following syntax '-transform gate_clock'. E PWR-272 synth_library not set or empty. W PWR-280 %s is not a buffer cell and will be ignored. W PWR-281 %s buffer cell does not exist. W PWR-282 The link library does not contain a buffer. E QTM-1 Cannot create the QTM model '%s' before saving the existing\n\ one E QTM-2 There is no QTM model that is currently being defined. E QTM-3 Unable to load the library '%s' W QTM-4 Technology library '%s' has been already been loaded W QTM-5 The parameter '%s' has already been set to '%f',\n\ overriding with the new value W QTM-6 The parameter '%s' has already been set to '%s',\n\ overriding with the new value E QTM-7 The option '%s' cannot be used in conjunction with '%s' E QTM-8 To use option '%s', the option '%s' has to be used. E QTM-9 To use option '%s', a library should have been\n\ specified, but no library has been specified for this model W QTM-10 The path type '%s' has already been defined,\n\ redefining the path type with the new one E QTM-11 The library cell '%s' is not present in the technology\n\ library you have specified E QTM-12 The '%s' pin '%s' you have specified, is not present\n \ in the cell '%s' W QTM-13 Fanout count not specified for the path type '%s',\n\ using the default fanout of %d W QTM-14 The drive type '%s' has already been defined,\n\ redefining the drive type with the new one W QTM-15 The load type '%s' has already been defined,\n\ redefining the load type with the new one W QTM-16 The port '%s' has already been created in the model\n\t\ replacing the original port with the new port E QTM-17 Must specify one of '%s', or '%s' options E QTM-18 The '%s' QTM parameter '%s' used has not been defined E QTM-19 The port '%s' used in the arc is not defined E QTM-20 The '%s' port for a '%s' arc must be a '%s' port\n,\ but port '%s' is of type '%s' E QTM-21 The port '%s' is not a bus, but you have implied a \ bus structure. E QTM-22 The bus index specified %d:%d for the bus '%s', out of the bus\n\ array bounds %d:%d E QTM-23 The arc which is an edge arc (launch) has\n\ more than one port (%d) as the from port E QTM-24 The global '%s' parameter has not been defined, you cannot \n\ define a '%s' arc E QTM-25 Cannot get clock pin for the cell '%s' E QTM-26 Cannot find a '%s' arc in the cell '%s'\n\ from the clock pin '%s'. E QTM-27 Cannot find the pin '%s' in the cell '%s' E QTM-28 Pin '%s' is not of type '%s' E QTM-29 Could not find arc of type '%s' coming %s \n\ the pin %s E QTM-30 Could not find arc from clock '%s' to the\n\ output pin '%s' E QTM-31 The port '%s' is not defined in the QTM model. E QTM-32 The port '%s' for which the drive is defined is neither\ an output port nor inout port E QTM-33 The drive type '%s' used is not defined E QTM-34 The port '%s' for which the load is defined is neither\ an input/clock/inout port E QTM-35 The load type '%s' used is not defined. E QTM-36 There is no pin '%s' of type %s in the cell '%s'. E QTM-37 No arc exists from '%s' to '%s' in the lib_cell %s. I QTM-38 Path Type: %s, Cell: %s, Input Pin: %s, Output Pin: %s \n\ Delay : %f I QTM-39 Load Type: %s, Cell: %s, Pin: %s. I QTM-40 Drive Type: %s, Cell: %s, Input Pin: %s, Output Pin: %s . I QTM-41 Parameter: %s, Cell: %s, Clock Pin: %s, Input \n\ \tPin: %s \ Constraint Value : %f. I QTM-42 Parameter: clk_to_output, Cell: %s, Clock Pin: %s, Output Pin: %s \n\ Delay Value : %f E QTM-43 Parameter '%s' cannot be a negative number E QTM-44 Port '%s' not defined to be a clock E QTM-45 Port '%s' not of the type input/inout. E QTM-46 Port '%s' not of the type output/inout. E QTM-47 Port '%s' not of the type input/inout. W QTM-48 The port '%s' has invalid name. W QTM-49 Wire Load Model '%s' doesn't exist in the library.\n\ Using 0 capacitance. F RB-1 Rulebase name '%s' is already taken. E RB-2 Rulebase divide by zero error. E RB-3 Cannot insert atom '%s' in rulebase. W RB-4 Could not load rulebase utilities. E RB-5 Could not open file '%s'. F RB-6 Binary table format error. E RB-7 Cannot insert rule '%s' in rulebase. E RB-8 Cannot insert class '%s' in rulebase. F RB-9 Stream I/O error on '%s'. F RGEN-1 Topology error in target net near '%s'. F RGEN-2 Topology error in replacement net near '%s'. F RGEN-3 Cannot write a file in '%s'. F RGEN-4 Cannot find attribute '%s' on object '%s'. W RPT-1 Reports may be inaccurate and/or incomplete due to interrupt. W RPT-2 %d unresolved references are not included in this report. W RPT-3 No timing information for '%s'. I RPT-4 Reported the %d requested paths; other paths have identical delays. E RPT-5 Illegal -%s list. E RPT-6 No match for %s '%s'. I RPT-7 This design contains unmapped logic. I RPT-8 This design contains black box (unknown) components. I RPT-9 This design contains at least one timing loop at pin: '%s'. W RPT-10 Design '%s' has no schematic. E RPT-11 This design has no %ss. W RPT-12 This design has no %s. W RPT-13 The replace_fpga command has been run on portions\n\ \tof this design. Since replace_fpga replaces fpga resources by gates the\n\ \treport you are about to see may not accurately convey table lookup usage\n\ \tinformation. It is better to use report_fpga BEFORE replace_fpga. E RPT-14 A %s report can not be generated for %s designs. E RPT-15 Conflicting inputs for the options '%s'. W RPT-16 Corrupt or unreadable pathname.\n\ \tThe problem is at the pathname '%s',\n\ \tone of the components of the pathname, or one level below the pathname.\n\ \tAborting processing for this pathname. W RPT-17 Missing synthetic library information for the cache entry\n\ \t'%s'.\n\ \tThis report will use parameter names like 'unknown_param_1'. E RPT-18 Syntax error in -parameters input option at or near '%s'. W RPT-19 Inconsistent number of parameters for the cache entry\n\ \t'%s'.\n\ \tThis report will use parameter names like 'unknown_param_1',\n\ \tif there are parameters. I RPT-20 This design has been annotated with physical cluster hierarchy. E RPT-21 The report_clusters command cannot be specified for the \n\ design '%s', which has no physical cluster hierarchy. E RPT-22 The design '%s' has no cluster named '%s'. E RPT-23 The -cells option can be supplied only if a -cluster is specified. W RPT-24 Problems encountered with removing the file or directory\n\ \t'%s'.\n E RPT-25 Clock '%s' cannot be used for all_registers because it has no period. E RPT-26 Unable to find clock '%s'. W RPT-27 Some clocks have no period defined. These clocks will not\n\tbe considered for timing. E RPT-30 Cannot find wire load '%s' in design '%s'. W RPT-31 There is no porosity information in library '%s'. W RPT-32 There is no porosity information in link libraries. E RPT-33 Could not find the specified %s pin. E RPT-34 Library cell delay information is protected. E RPT-35 There is no cell or net delay arc between pins '%s' and '%s'.\n\ \tThe pins must be on the same net or the same cell. E RPT-36 There is no library associated with the cell\n\ \tattached to the 'to' pin. E RPT-37 Must specify exactly one '%s' pin for this command. E RPT-38 Timing arc type '%s' is not supported for this command. W RPT-40 The '-insts' option is available only with a TestManager license.\n\ \tIt will be ignored. W RPT-41 The faults annotated on the design are being ignored. W RPT-42 Constraint generation interrupted. Constraint\n\ \tfile may be incomplete or inaccurate. W RPT-45 The value for '%s' must be between '%s' and '%s'.\n\tUsing default value of '%s' instead. E RTDC-3 The sequential cell '%s' drives the clock in this\n\ \tdesign. This cannot be retimed. E RTDC-4 The cell '%s'\n\ \tdrives the clock in this design. Only buffer and inverter\n\ \tcells are allowed on the clock network. E RTDC-5 No net driving clock pin of '%s'. E RTDC-6 Retiming cannot be performed with this clocking scheme. E RTDC-7 The following cell(s) contain sequential elements\n\ \tand have the dont_touch attribute set. Cannot retime. E RTDC-8 Sequential cell '%s' is not a flip-flop. Cannot retime. E RTDC-9 More than one clock signal has been detected.\n\ \tMultiple clock signals not allowed for retiming. The different \n\ \tclocks have sources in '%s' and '%s'. W RTDC-10 No movable flip-flops in design. Nothing to retime. W RTDC-12 No designs have the balance_registers, \n\ \toptimize_registers or pipeline_design attribute set. Nothing to retime. E RTDC-13 Retiming interrupted. W RTDC-14 Retiming failed. No registers have been moved. W RTDC-15 Design contains registers that will be retimed.\n\ \tCannot verify. E RTDC-16 The design contains generic combinational\n\ \tlogic. Cannot retime. E RTDC-17 Design contains unmapped DesignWare parts. Cannot retime. W RTDC-19 Clock period after accounting for\n\ \tworst case set-up and median clock to Q/QN delay is\n\ \tnon-positive. Original clock period is %.2f, estimated\n\ \tclock period is %.2f. The number of registers will\n\ \tbe minimized at the minimum possible period, that is,\n\ \tthe target clock period is zero. E RTDC-20 Negative clock cycle specified with -period option. E RTDC-21 No clock connected to flip-flops. Unable to determine\n\ \tthe clock period. W RTDC-22 No clock period specified with clock %s. W RTDC-23 No clock found on '%s'.\n\ \tTrying flip-flops in the design. E RTDC-24 Retiming is not supported for Xilinx 4000 designs. E RTDC-25 The target library does not contain an\n\ \tinverter. W RTDC-26 The flip-flop '%s' selected by \n\ \t'set_register_type' is unacceptable for retiming because\n\ \tno setup time is available for this flip-flop.\n\ \tAttempting to search the target library for a\n\ \tD flip-flop with reasonable setup. E RTDC-27 No good flip-flop found in library. Cannot model\n\ \tthe design. E RTDC-29 A combinational loop was found in design.\n\ \tRetiming cannot operate on such designs. E RTDC-30 The design has master-slave sequential elements as well \ as flip-flops. \n\ \tAll sequential elements must be of the same kind. W RTDC-31 The master clock has period %.2f, the slave\n\ \thas period %.2f. Choosing master clock period as target for area\n\ \toptimization. W RTDC-32 Cell '%s' has no timing information. Treating it \n\ \tlike an external module. W RTDC-33 Must have Behavioral Compiler license to handle cells without timing information. W RTDC-34 The following registers are considered to be\n\ \t'fixed' during retiming to preserve timing requirements. They are\n\ \tendpoints of point to point exceptions such as 'set_false_path'. E RTDC-35 Designs with flip-flops driving a reset pin\n\ \tcannot be retimed. E RTDC-36 Designs using gated resets cannot be retimed. E RTDC-37 Cannot retime a design with several driving\n\ \tpins for the asynchronous set or clear. One pin found is \n\ \t'%s', another one is\n\ \t'%s'. E RTDC-38 Cannot retime flip-flops with asynchronous set\n\ \tand clear at the same time. E RTDC-40 Flip-flop with two asynchronous pins connected.\ Cannot retime. E RTDC-41 The following cell(s) have at least one pin,\n\ \twhich is bidirectional (inout) or for which the direction cannot\n\ \tbe inferred (for example because the the cell itself is an unresolved\n\ \treference). Cannot retime. W RTDC-42 Port '%s' has a negative I/O delay set. This is \n\ \tnot supported for retiming. Using zero instead. W RTDC-43 The input port '%s' has an input delay that is \n\ \tsmaller than the estimated average clock-to-Q delay used by the\n\ \tretiming algorithm. For optimal results, make sure to set an input\n\ \tdelay that is realistic. This can be done by using the\n\ \t'set_input_delay' or 'characterize' commands. W RTDC-44 The output port '%s' has an output delay that is\n \ \tsmaller than the estimated average setup time used by the retiming\n\ \talgorihm. For optimal results make sure to set an output delay\n\ \tthat is realistic. This can be done by using the 'set_output_delay'\n\ \tor 'characterize' commands. E RTDC-45 The clock tree is configured such that cell '%s' and cell '%s' are sensitive to opposite edges of the clock applied to the clock port of the design. Cannot retime. E RTDC-46 The clock tree feeds cell '%s' which is non sequential and does not feed any sequential cells. Cannot remove the clock tree. W RTDC-47 There are buffer or inverter cells in the\n\ \tclock tree. The clock tree has to be recreated after\n\ \tretiming. E RTDC-48 A master-slave flip-flop has been chosen as the preferred\ flip-flop for a normal flip-flop type design. Cannot retime. E RTDC-49 A single-phase clock flip-flop has been\n\ \tchosen as the preferred flip-flop for a master-slave\n\ \ttype design. Cannot retime. E RTDC-50 Cell '%s' has too many pins. Cannot retime. W RTDC-51 The clock tree feeds cell '%s' which is non sequential and does not feed any sequential cells. E RTDC-52 The following cell(s) are tristate cells.\n\ \tCannot retime. E RTDC-53 The design '%s' is not purely combinational. It\n\ \tcannot be pipelined. E RTDC-54 The target library does not contain any edge triggered\n\ \tflip-flops. E RTDC-55 The target library does not contain a simple D\n\ \tflip-flop without additional logic. E RTDC-56 Could not find the port '%s' in the design. W RTDC-57 The value provided by the '-period' option for\n\ \toptimize_registers will now be corrected by the setup time and\n\ \tclock-to-Q delay of the preferred flip-flop. E RTDC-58 A loop without registers on the net was\n\ \tdetected in the design taking into account hierarchical cells\n\ \twith the dont_touch attribute set to true. I.e. these cells\n\ \tare viewed as a single cell. Retiming cannot operate on such\n\ \tdesigns, although the netlist on the leaf cell level does not\n\ \tcontain combinational feedback loops. W RTDC-59 The 'optimize_registers' attribute or the \n\ \t'pipeline_design' attribute has been set on a design but no \n\ \tlicense for this feature is authorized. The retiming will be \n\ \tperformed using the 'balance_registers' functionality.\n W RTDC-60 The design contains the following cells\n\ \t which have no influence on the design's function but cannot\n\ \t be removed (e.g. because a dont_touch attribute has been set\n\ \t set on them). Retiming will ignore these cells in order to \n\ \t achieve good results:\n\ %s\n W RTDC-61 The design contains the following cells\n\ \tfrom the GTECH library. The results of retiming may not be\n\ \tvalid: W RTDC-62 The design contains the following multibit\n\ \tregisters, which can be moved by retiming. For retiming they\n\ \twill be decomposed into single bit registers. To avoid this\n\ \tput a 'dont_touch' attribute on these cells. W RTDC-63 The flip-flop '%s' selected by \n\ \t'set_register_type' is unacceptable for retiming because\n\ \tit cannot be used to represent all necessary flip-flop functions.\n\ \tAttempting to search the target library for a suitable\n\ \tD flip-flop. W RTDC-64 The flip-flop '%s' selected by \n\ \t'set_register_type' is unacceptable for retiming because\n\ \tit is not a scan flip-flop. Since this is a scan replaced\ \tdesign, the flip flop will only be used for retiming \n\ \tcalculations. Another flip-flop may be used for replacement. E RTDC-65 The current (sub)-design is \n\ \tscan routed. Retiming would invalidate the scan \n\ \trouting. E RTDC-66 The current (sub)-design has \n\ \tscan logic. Retiming would invalidate the scan \n\ \tlogic. E RTDC-67 A timing arc with a negative\n\ \tdelay was found. Cannot retime. W RTDC-68 There is not enough information available about the\n\ \tfunctionality of the library cell of flip-flop cell\n\ \t %s.\n\ \tIt cannot be retimed. It will be treated as a fixed flip-flop. W RTDC-69 The flip-flop cell %s has either the force_00 or\n\ \tthe force_11 input connected, or it has both the force_01 and the force_10\n\ \tconnected to a non-constant net. This type of cell cannot be supported \n\ \tby retiming. Therefore it will not be moved. W RTDC-70 The flip-flop cell %s is a multibit cell. For \n\ \tretiming the cell's synchronous set, clear or load enable capabilities \n\ \twill not be utilized. W RTDC-71 The flip-flop cell %s is connected at both\n\ \tthe asynchronous preset pin and the asynchronous clear pin. The\n\ \tlibrary cell for this cell has identical reset values for the\n\ \tQ and the QN output in case both the preset and the clear are\n\ \tactive simultaneously. If this situation can occur in the circuit\n\ \tthe retimed circuit may have a behavior differing from that of the\n\ \toriginal circuit. E RTDC-72 The target technology library does neither contain\n\ \ta two input AND nor a two input NAND gate. On of these is necessary to\n\ \tconnect flip-flops with two reset inputs correctly after retiming. E RTDC-73 The target technology library does neither contain\n\ \ta two input OR nor a two input NOR gate. On of these is necessary to\n\ \tconnect flip-flops with two reset inputs correctly after retiming. E RTDC-74 The retiming graph that has been constructed \n\ \tfor the design to be retimed does not contain any nodes. W RTDC-75 The %s option has been set to\n\ \tdecompose and the %s option has been set to dont_care.\n\ \tUsing preserve instead. W RTDC-76 The transformation option has been set to\n\ \tdont_touch or dont_retime and the state option has been set to\n\ \tdont_care for %s registers. Using preserve for the state. E RTDC-77 The cell %s \n\ \thas has an illegal value of the transform_for_retiming attribute. E RTDC-78 The cell %s \n\ \thas has an illegal value of the state_for_retiming attribute. W RTDC-79 The cell %s \n\ \thas the dont_touch or dont_retime and the dont_care attribute set.\n\ \tUsing preserve instead. W RTDC-80 The cell %s \n\ \thas the decompose and the dont_care attribute set.\n\ \tUsing decompose and preserve instead. E RTDC-81 The clock system is too complicated for retiming. E RTDC-82 The backward justification during retiming\n\ \tfailed. E RTDC-83 The forward justification during retiming\n\ \tfailed. W RTDC-84 The cell %s \n\ \thas at least one asynchronous pin connected\n\ \tand the decompose transform attribute is set for it.\n\ \tThe any synchronous functionality of this cell \n\ \twill be handled by decomposing. Asynchronous clear\n\ \tor set will be handled using multiclass functionality. W RTDC-85 The cell %s \n\ \thas at least one asynchronous pin connected\n\ \tand the decompose transform attribute is set for it.\n\ \tSince the default transformation for asynchronous \n\ \tcells is dont_touch, this cell will not be moved. W RTDC-86 One or more cells in the design\n\ \tto be retimed have the retiming state attribute set to\n\ \tdont_care. The behavior of the retimed circuit may \n\ \tdiffer from that of the original circuit. W RTDC-87 Net %s has the synch_set_reset attribute\n\ \tset. The following sequential cells in the net's fanout may\n\ \tbe moved away from the net during retiming. W RTDC-88 The optimize_registers or the\n\ \tpipeline_design attribute has been set on a design\n\ \tbut the BOA-BRT license is not available. W RTDC-89 A retiming attribute (optimize_registers,\n\ \tbalance_registers, pipeline_design) has been set on a design\n\ \tbut the DC-Expert license has not been authorized. Retiming\n\ \tcannot be performed. W RTDC-90 A retiming attribute (optimize_registers,\n\ \tbalance_registers, pipeline_design) has been set on a design\n\ \tbut the DC-Expert license is not available. W RTDC-91 The design contains combinational cells\n\ \tthat are not from the target library. W RTDC-92 A timing arc with a negative\n\ \tdelay was found found on cell %s (%s)\n\ \tfrom pin %s to pin %s.\n\ \tUsing zero delay instead. W RTLOUT-1 The designware operation '%s' is not one of the\n\ \tpredefined designware operations. As a result, a call to a function\n\ \twith the same name of the operator will be written out, and the\n\ \tcontents of that function will need to be provided. W RTLOUT-2 \ The DesignWare operator '%s' has a port '%s'\n\ \tfor which HDL type information could not be extracted. This port will\n\ \tbe declared as a vector of bits (for example, std_logic_vector\n\ \tin VHDL), in the generated RTL code. This can result in errors\n\ \tduring subsequent analysis of the HDL code. I RTLOUT-3 Synthesizable RTLOUT is being written. E RTLOUT-4 Only non-levelized (structural) %s shall be generated with -rtl_script option. E RTLOUT-5 Writing synthesizable RTLOUT was not successful. E RTLOUT-6 Currently we do not allow a subdesign to be written for synthesizable RTLOUT. When we use `write -script_file' command, please do not specify any design name. I RTLOUT-7 %s is an alias for %s. E RTLOUT-8 Design %s didn't link properly. E RTLOUT-9 Writing a synthesizable RTLOUT was not successful because of a failure in the preprocess step. Please make sure that you generate a new scheduled.db using the new schedule executable. E RTLOUT-10 Option -rules_name should only be used to generate a synthesizable RTLOUT. Hence, -rtl_script must be given at the same time. I RTLOUT-11 User-specified rename rules\ shall be applied. E RTLOUT-12 Applying user-specified rule %s was not successful. I RTLOUT-13 Default rename rules are applied to pass design constraints from Behavioral Compiler to Design Compiler. E RTLOUT-14 Application of default renaming rules was not successful. E RTLOUT-15 Option -rtl_script should only be used for a BC design which has been manipulated for synthesizable RTLOUT. E RTLOUT-16 Currently, write -rtl_script command should be used to write only the entire design hierarchy. Please use -hierarchy option with -script_file option. E RTLOUT-17 You may not use %s option with -rtl_script option. E RTLOUT-18 -rules_name option should be used with -rtl_script option. E RTLOUT-19 The design is not scheduled by Behavioral Compiler. E RTLOUT-20 Missing implementation directives for design %s. E RTLOUT-21 Design %s contains RTL process %s. Synthesizable RTLOUT is not supporting a design which contains an RTL process. A manual manipulation of RTL processes is advised. I RTLOUT-22 Sharing and implementation directives for process '%s': I RTLOUT-23 Sharing is prohibited on the process. E RTLOUT-24 Output file name must be specified with -output option when you write a synthesizable RTLOUT. I RTLOUT-25 %s name '%s' changed to '%s' E RTLOUT-26 The format should be either VHDL or Verilog for synthesizable HDLOUT. I RTLOUT-27 Register bank, %s's enable signal is masked by M port. In synthesizable HDLOUT, the register bank will be written in bit-level instead of word-level to indicate which bits are masked. I RTLOUT-28 %s %s is written in the rtlout. I RTLOUT-29 %s %s is instantiated, and must be resolved via link. I RTLOUT-30 Mapping to target_library %s. I RTLOUT-31 Synthesizable RTLOUT will generate constraint.script in both dcsh and dctcl because bc_synrtl_write_dcsh_and_dctcl is on. The current dc_shell is running in %s mode. Therefore, the given file name is used to write in %s script, and %s is used to generate a %s script. E SAIF-1 The SAIF file contains switching data for the design '%s'; \n\ \tthis switching data cannot be annotated on the design '%s'. W SAIF-2 The SAIFVERSION values we accept is '%s'. E SAIF-3 The time unit in a SAIF file must be one of these: \n \ \ts, ms, us, ns, ps, fs. E SAIF-4 The time_scale in a SAIF file must be one of these: \n\ \t1, 10, 100. E SAIF-5 %s at or near token '%s'. W SAIF-6 The object '%s' does not belong to\n\ \tthe instance '%s'. The object is ignored. W SAIF-7 The -instance parameter, '%s' is\n\ \ta substring of the object '%s', but it is not a complete\n\ \tname. The object is ignored. W SAIF-8 The object '%s' has been found without\n\ \ta containing module, after '%s' is stripped off. The object\n\ \tis ignored. E SAIF-9 The simulation duration time is less or equal to 0. E SAIF-10 The read_saif command can only read a \ backward-annotation SAIF file. E SAIF-11 This file has a version number greater than 2.0, but\ it does not contain the "DIRECTION ..." construct. E SAIF-12 Unable to open file %s. W SAIF-13 Cannot find the equivalent %s pin of the cell %s. E SAIF-14 Path dependent switching activity has to be\ specified inside the state dependent switching activity. E SAIF-15 Only timing attribute information can be specified\ inside the LEAKAGE construct. W SAIF-16 Can't find object '%s'. E SCAN-1 Can't open init file '%s'. E SCAN-2 Init file '%s' has improper format. E SCAN-3 Invalid data format. E SCAN-4 %s: Lexical Error on line %d at or near '%s'. E SCD-2 Operations in resource '%s' can not be shared\n\tbecause they may execute in the same control step %s E SCD-4 Operations in resource%s are part of a\n\tdata flow cycle %s E SCD-7 You must specify the module using 'map_to_module' if you want\n\tto set the implementation%s I SCD-9 Additional cells were grouped along with specified cells \n\tbecause they must be in the same design as the grouped logic which they control. I SCD-10 Some cells were not grouped because they must be in the same \n\tdesign as the logic which they control. I SCD-11 Some cells were duplicated in both the original and grouped \n\tdesign because these cells control logic in both the original and grouped design. W SCD-12 Operation '%s' can not be included in a resource. It will not be implemented on '%s' %s E SCHD-1 %s '%s' in design '%s' has no symbol. E SCHD-2 %s '%s' in design '%s' has no symbol library. E SCHD-3 The symbol library of %s '%s' in design '%s' has no name. W SCHD-4 Symbols were generated because they were not found in any library. E SCHD-5 %s '%s' has no symbol. E SCHD-6 Could not load bitmap file '%s'. E SCHD-7 Could not find reference name for cell '%s' on the schematic.\n\ \tWas this schematic created with an older version of Synopsys software? E SCHD-8 '%s' is not a valid justification specification. E SCHV-1 Plot command is not available. W SDFN-1 The delay type variables must be: 'minimum' 'typical' or 'maximum'. '%s' is invalid, '%s' will be used by default. W SDFN-2 The library '%s' has no time unit specified, '%s' is assumed. W SDFN-3 No library was found on the search path, time unit '%s'\n\ is assumed. E SDFN-4 The SDF file contains delays for the design '%s', \n\ they cannot be annotated on design '%s'. W SDFN-6 Cell delay could not be annotated between pin '%s', \n\ and pin '%s' for the design '%s'. W SDFN-7 Interconnect delay could not be annotated between pin '%s',\n\ and pin '%s' for the design '%s'. W SDFN-9 Instance '%s' could not be found. W SDFN-10 Pin '%s'/'%s' could not be found. E SDFN-11 Port '%s' could not be found. W SDFN-12 Net delay could not be annotated on pin or port '%s' \n\ for design '%s'. W SDFN-13 The SDF file contains negative cell delays. W SDFN-14 The SDF file contains negative net delays. E SDFN-15 SDF version '%s' is not supported. Use version '%s'. I SDFN-16 Reading '%s' values for '%s'. W SDFN-17 '%s' is read as an instance of '%s' but is linked to design '%s'. E SDFN-20 '%s' is not a valid triplet name for max. E SDFN-21 '%s' is not a valid triplet name for min. E SDFN-22 If minimum triplet name is 'none', the maximum triplet \n\ \tname cannot be 'none'. E SEC-0 Software is not licensed for this machine. E SEC-1 %s E SEC-2 Cannot open key file '%s' or a licensing environment parameter has not been set correctly. E SEC-3 Encryption file header is corrupt. E SEC-4 Unknown encryption method. W SEC-5 License for '%s' expires within %2d days. W SEC-6 License for '%s' has expired. E SEC-10 Software is not licensed for this machine. E SEC-11 Software is not yet enabled or has expired. E SEC-12 Can't communicate with the license server. E SEC-13 The date/time difference between your host and the license\n\ \tserver host is too great. E SEC-14 Key file syntax error: %s. E SEC-15 Key file '%s' has an unrecognized format. E SEC-16 Can't read the '%s' file. E SEC-17 Internal licensing error number %d: %s. E SEC-18 Unknown internal licensing error number: %d. E SEC-20 This site is not authorized for license(s):\n %s E SEC-21 Failed to checkout license for feature(s):\n %s I SEC-22 %s feature '%s'. I SEC-23 Waiting for required feature(s). (%s) E SEC-50 All '%s' licenses are in use. E SEC-51 This site is not licensed for '%s'. E SEC-52 Requested more licenses for '%s' than supported in the key file. E SEC-53 The end-user license options EXCLUDE you from using '%s'. E SEC-54 The end-user license options don't INCLUDE you for using '%s'. E SEC-55 Can't remove your '%s' license. You must always have one or\n\ more of the following license(s): %s. I SEC-80 Attempting to reacquire license for '%s'; wait %d minutes. I SEC-81 Reacquired license for '%s' after %d minutes. W SEC-82 License server is busy, retrying. W SEC-83 Timeout value must be between %d and %d; using default of %d. W SEC-84 Unable to obtain a license for '%s'.\n\ \t Obtained a license for '%s' instead.\n\ \t '%s' contains these features:%s. E SEC-85 Communication with the license server failed; error number %d. E SEC-86 This site is not licensed for third party software; error number %d. E SEC-100 This can only be used with software that is network licensed. I SEC-101 No one is using any feature from the license server. E SEC-102 Unable to get an optimize license. E SEC-103 You must have a Design-Analyzer or one of the optimize licenses to use this feature. I SEC-104 Checking out the license '%s'. I SEC-105 Checking in the license '%s'. E SEL-001 No such collection '%s' W SEL-002 Collection '%s' has inappropriate type (%s). W SEL-003 Nothing implicitly matched '%s' W SEL-004 No %ss matched '%s' E SEL-005 Nothing matched for %s E SEL-006 More than one object matched for '%s'. E SEL-007 Invalid index %d for collection %s W SEL-008 Collection/attribute class '%s' has not been defined W SEL-009 Collection class '%s' cannot be %s W SEL-010 %s objects from '%s' were of the %scorrect class. W SEL-011 Some objects (%s) could not be queried. I SEL-012 Iteration for collection %s was terminated\n\tbecause the collection was modified or deleted. E SEL-013 Regular expression error: %s. E SEL-014 At least one %scollection required for argument '%s'%s W SEL-015 Ignored all implicit elements in argument '%s'%s E SIF-1 Parse error near symbol \"%s\" on or near line %d in file %s E SIF-2 Package \"%s\" multiply defined %s E SIF-3 Illegal port direction %s E SIF-4 Parameter \"%s\" multiply defined %s E SIF-5 Variable \"%s\" multiply defined %s E SIF-6 Block \"%s\" multiply defined %s E SIF-7 Instance \"%s\" multiply defined %s E SIF-8 Label \"%s\" multiply defined %s E SIF-9 Port \"%s\" multiply defined %s E SIF-10 Can't exit block \"%s\" %s E SIF-11 For loop variable \"%s\" not defined %s E SIF-12 Illegal block direction %s E SIF-13 Right-hand-side must be attribute, type(), or const() %s E SIF-14 Symbol \"%s\" not found %s E SIF-15 Can't get attribute \"%s\" of a string %s E SIF-16 Can't find attribute \"%s\" of \"%s\" %s E SIF-17 Port \"%s\" direction not defined %s E SIF-18 Illegal character or symbol (%d) %s E SIF-19 Attributes may not not be nested %s E SIF-20 Malformed attribute specification %s E SIF-21 Varargs too big in '%s' %s W SIF-22 Built-in function %s does not exist (ignored). W SIF-23 Inout port \'%s\' drives a scan-in pin. This\n\ VHDL design cannot support parallel-loading. E SIF-24 No primary input bidirectional control signal specified.\ No vectors generated. W SIF-25 Scan cell "%s" is within a hierarchical design module \ and references a non-unique instance in the design.\n\ \tThis VHDL design cannot support parallel loading. E SIF-26 Port \"%s\" must be specified as a bidirectional control \ port BEFORE invoking create_test_patterns. No vectors generated. E SIF-27 Apparent inconsistency between vector data base and netlist data base. Could not find \'%s\' in vector data base. E SIF-28 Trying to specify parallel load for a protocol that is incapable of supporting it. W SIF-29 Maximum number of input timing definitions supported by the TSTL2 format exceeded. Subsequent specifications will be ignored. W SIF-30 write_test_max_cycles value specified is too small, value will be ignored W SIF-31 Cell '%s' does not have its set and observe pins specified W SIF-32 Scan chain '%s' does not have a scan %s port. W SIF-33 Output net '%s' seems to be shorted to output net '%s', \ and they both drive the same scan data pin of scan cell '%s'. E SIF-34 Can not find library needed by this design E SIF-35 %s , scan package for parallel-loading is not created. E SIF-36 Could not find data base reference for scan cell '%s' . E SIF-37 Could not get bit value for primary port '%s' in test \ program. This port is present in the current design. E SIF-38 Clock port '%s' can not be found in test protocol. \ This port is present in the current design. E SIF-39 Scan chain number '%d' can not be found. \ Possible test protocol problem. E SIF-40 The vector file '%s' created by TestSim has been corrupted. E SIF-41 Can not find scan %s port of scan chain number '%d'. \ Possible test protocol problem. E SIF-42 Can not find data for scan port named '%s' in test \ protocol. Possible test protocol problem. E SIF-43 Can not find vector index '%d' for port '%s' in test \ protocol. Possible test protocol problem. E SIF-44 Using bidirectional port '%s' as clock is currently unsupported E SIF-45 Scan chains in this design are not parallel loadable because not all scan cells are both controllable and observable. W SIF-46 Bidirectional ports switch mode after/during some clock pulses. You may get mismatches when simulating these vectors. E SIF-47 Formatting of vectors in this format is not currently supported for designs with multibit cells. I SIF-48 Design has multibit cells. Please make sure your WGL translator can correctly interpret the WGL output generated. W SIF-49 Some timing values are being rounded to integers.\ This may cause simulation mismatches. E SIF-50 Multiple declaration of terminal '%s' in instance '%s' W SPEF-1 Missing or unknown library unit. I SPEF-2 Path delimiter = %s. I SPEF-3 Pin delimiter = %s. W SPEF-4 Missing or unknown capacitance library unit. E SPEF-5 No DC design in memory. W SPEF-6 Failed to lookup annotated delay between '%s' and '%s'. W SPEF-7 Failed to lookup elmore node for '%s'. W SPEF-8 Uncomplete RC annotation between '%s' and '%s'. W SPEF-9 Inconsistent backannoted data detected. I SPEF-10 Library unit = %d %s. I SPEF-11 Scale factor = %f. I SPEF-12 Capacitance scale factor = %f E SR-1 Can't find module to implement operation '%s'%s E SR-2 Can't implement all operations of resource(s) '%s'\n\t\ on any available module %s E SR-3 Can't find implementation '%s' for module '%s'\n\t%s E SR-4 Data class '%s' is not recognized. E SR-5 Can't find the %s '%s' in synthetic_library.\n\tResource sharing has been aborted %s E SR-6 Can't find the bussed port '%s' on design '%s'.\n\tResource sharing has been aborted %s E SR-7 Cannot find instantiated synthetic module '%s'\n\t\ in the libraries listed in 'synthetic_library'. E SR-8 The %s is shorted to the %s.\n\tResource sharing does not support operations that are\n\tshorted together. W SR-9 The operation '%s' has been deleted because\n\tit was not needed. I SR-10 Reporting of resource costs is no longer supported. E SSH-1 Unknown host '%s'. E SSH-2 Can't execute program '%s'. E SSH-3 File '%s': Permission Denied. E SSH-4 Could not connect to %s subshell I SSH-5 Abnormal Exit -- program %s function %s host %s E SSH-6 '%s' is not a valid feature name for '%s'. W SYMB-1 The symbol attribute '%s' was lost during translation to db. E SYMB-2 Couldn't write to the file '%s'. W SYMB-3 Encountered an end of file before processing was finished\n\tin file '%s'. W SYMB-4 Corrupted data file '%s' ...\n\t%s. W SYMB-5 The file '%s' is not a symb file. W SYMB-6 Can't read in this version of data file ... please regenerate\n\tthe data file '%s' by re-analyzing its source. W SYMB-7 The value of the current time in the operating system\n\tis earlier than the time of the source file.\n\tThe timestamp that will be used to save the .syn file\n\twill be the time of the source file. E SYNDB-1 Could not find parameter '%s' on module '%s'. W SYNDB-2 Could not find design '%s' associated with module '%s'. E SYNDB-3 A port could not be found on the %s '%s' which matches\n\ \tthe port '%s' on the %s '%s'. E SYNDB-5 A design named '%s' has already been associated with module '%s'. E SYNDB-6 The port '%s' on the module has a different direction than the port '%s' on the design. E SYNDB-7 A parameter could not be found on the %s '%s' which matches\n\ \tthe parameter '%s' on the %s '%s'. E SYNDB-8 Could not compile the synthetic design '%s'. E SYNDB-9 Could not model the compiled synthetic design '%s'. E SYNDB-10 The parameter '%s' for the module '%s' hasn't been specified\n\ \ton the reference '%s'. E SYNDB-11 Could not build the synthetic design '%s'. W SYNDB-12 A reference has been made to the module '%s' which has\n\ \thad no designs specified which can implement it. E SYNDB-13 Could not find the required attribute 'default_implementation'\n\ on the module '%s' W SYNDB-14 The attribute 'default_implementation' is required on the\n\ synthetic library module '%s'. E SYNDB-15 Module '%s' has an implementation '%s' which has a \n\ syntax error in the contained implementation '%s'. E SYNDB-16 In module '%s' implementation '%s', the contained \ operator '%s' cannot be found. E SYNDB-17 In module '%s' implementation '%s', the contained \ module '%s' cannot be found. E SYNDB-18 The synthetic library operator '%s'\n\ is referred to in the (linked) current design, but it cannot be\n\ found among the .sldb files. E SYNDB-19 The synthetic library module '%s'\n\ is referred to in the (linked) current design, but it cannot be\n\ found among the .sldb files. E SYNDB-20 Cannot find the synthetic library implementation '%s' of module '%s'. E SYNDB-21 The stall pin attribute is illegal on module %s. E SYNDB-22 %s binding '%s' must be associated\n\ \twith a %s module '%s'. E SYNDB-23 Improper use_resource name '%s' in binding '%s' of module '%s'. E SYNDB-24 Stable pin '%s' of binding '%s' of module '%s' has\n\ a changed value in the next state. E SYNDB-25 Unable to use implementation '%s' in module '%s'. W SYNDB-26 Implementation '%s' in module '%s' has a "dont_use"\n\ implementation as a result of "dont_use" lower level synthetic part '%s' E SYNDB-27 Referenced module '%s' has no implementation. W SYNDB-28 Module '%s' has no implementation. This module\n\ will not be considered during resource sharing. E SYNDB-30 Cannot find valid synthetic library implementations for module '%s'. E SYNDB-31 The check implementation reference group '%s'\n\ \twithin module '%s' refers to an implementation,\n\ \t'%s', which is not found in the current set of synthetic libraries. E SYNDB-32 The generator named '%s' does not exist within\ the '%s' library. E SYNDB-33 Implementation '%s' of module '%s' is not a valid implementation for the design when 'dw_prefer_mc_inside = false'. E SYNDB-34 Cannot find valid synthetic library module for operator '%s'.\ E SYNENC-1 Syntax error in HDL source file "%s". E SYNENC-2 "%s" is not a plain file. E SYNENC-3 cannot open file '%s' for reading. E SYNENC-4 cannot open file '%s' for writing. E SYNENC-5 Error while reading source file for encryption. E SYNENC-6 Internal encryptor error. I SYNENC-7 Processed file '%s'. I SYNH-1 The synthetic implementation was read from a cache. I SYNH-2 Read implementation '%s' for synthetic design '%s'\n\tfrom design library '%s'. I SYNH-3 Modeled %s(%s).\n\t(Wire load = %s Operating Conditions = %s) I SYNH-4 The synthetic model was read from a cache. E SYNH-7 Module '%s', implementation '%s' does not have a library attribute. E SYNH-8 Can't link to module '%s' implementation '%s'\n\ \tin synthetic part '%s'. W SYNH-9 Synthetic library implementation '%s' in module '%s' is an empty netlist. E SYNH-10 Port number %d of implementation '%s' of\n\tsynthetic module '%s' should be '%s'. E SYNH-11 Direction of port '%s' in implementation '%s'\n\t does not match the declared synthetic module '%s'. E SYNH-12 Width of port '%s' in implementation '%s'\n\t does not match the declared synthetic module '%s'. E SYNH-13 Port '%s' in implementation '%s'\n\t is not declared in the synthetic module '%s' E SYNH-14 Cannot find a valid implementation for module '%s'. E SYNH-15 Missing connection for input pin '%s' for binding\ '%s' in module '%s' for operation '%s'. E SYNH-16 Design hierarchy is not allowed inside a\n\ synthetic library part. The module '%s' implementation '%s'\n\ has hierarchy in it. E SYNH-17 Cannot find a legal implementation of any module \n\tto implement the operations bound to the resource '%s'. E SYNH-18 Cannot find a legal implementation of any module \n\tto implement the operator '%s'. W SYNH-19 Module '%s' was not found in the files of synthetic_library.\n\tImplementation of synthetic design '%s' (cell '%s')\n\tis not being reconsidered. W SYNH-20 set_implementation '%s' was not found in the files of\n\tsynthetic_library. Implementation of synthetic design\n\t'%s' (cell '%s') is not being reconsidered. I SYNH-21 Modeled %s(%s). W SYNH-22 Current implementation '%s' of module '%s'\n\twas not found in the files of synthetic_library.\n\tImplementation selection of synthetic design\n\t'%s' (cell '%s') will take longer. E SYNH-30 An incorrect range has been specified for parameter '%s'. E SYNH-31 The specified parameter set doesn't match the\n\t\ required parameter set for module %s. E SYNH-32 Failed to generate the module due to previous errors. W SYNH-33 Cannot find any module with the given name. E SYNH-34 Cannot find any valid implementation for module '%s' to match \n\t\ the requested implementation name. E SYNH-35 Too many parameters have been specified. E SYNH-36 Too few parameters have been specified. E SYNH-37 Parameter name mismatch. This module requires parameter '%s'.\n\t The provided parameter name is '%s'. W SYNH-38 '%s' is not a valid wire load in the specified technology library. E SYNH-39 '%s' is not a valid operating condition in the specified \ technology libraries. W SYNH-40 No known implementation matched '%s'. E SYNH-41 The implementation '%s' is not legal for implementing \n\tthe operations bound to resource '%s'. W SYNH-42 IIS optimization was skipped because the appropriate license could not be checked out.\n W SYNH-43 Syntax error in the 'synthetic_library' variable assignment.\n\ \tDefault value will be used. W SYNH-44 The synthetic library module '%s'\n\ \timplementation '%s' failed to link. W SYNH-45 Test logic has been inserted in %s.\n \ \tSkipping incremental implementation selection for that design. E SYNH-46 Could not find port '%s' in implementation '%s'\n\ \tof synthetic module '%s'. W SYNH-47 No stall value has been specified for processor input pin\n\ \t%s for binding %s in module %s and operation %s. W SYNH-48 The following module/implementation/parameters are invalid\n\ \tcombinations, they were ignored: %s W SYNH-50 Select operator cannot be built through the MGI. W SYNH-51 The array naming style of the synlib part %s is different than the current bug_naming_style setting %s. Skipping Incremental Implementation Selection for the design. I SYNL-4 Ignoring dont_touch on synthetic instance '%s' of '%s'. E SYNL-5 Can't find parameter '%s' in specification \"%s\". E SYNL-6 Malformed parameter specification \"%s\". E SYNL-7 '%s' is an invalid or out-of-date synthetic library. W SYNL-8 Can't find operator '%s' for binding '%s' in module '%s'.\n\tBinding ignored. E SYNL-9 Can't find oper_pin '%s' for binding '%s' in module '%s'. E SYNL-10 Direction of operator pin '%s' does not match direction\n\ \tof module pin '%s' in binding '%s' of module '%s'. E SYNL-11 Cannot find a module for '%s'.\n\tSynthetic libraries disabled. E SYNL-12 Can't find synthetic file '%s' in the synlib_search_path. E SYNL-13 %s. E SYNL-14 Parameter '%s' does not evaluate to %s\n\t%s. E SYNL-15 Parameter '%s' not defined\n\t%s. E SYNL-16 The synthetic library part implementation '%s' should be\n\ \tavailable for use during the compile command,\n\ \tbut the implementation is not enabled because all of the\n\ \tfollowing regular licenses have been checked out:\n\ \t%s.\n\ \tThe users of the licenses are listed in the following error message.\n E SYNL-17 Unknown input oper_pin '%s' specified as permutable on operator '%s'. W SYNL-18 Input oper_pin '%s' multiply specified as permutable. W SYNL-19 The limited license '%s' is being checked out to enable the\n\ \tsynthetic library part implementation '%s'.\n\ \tNote: designs cannot be written out if they have synthetic library\n\ \tparts enabled with limited licenses. E SYNL-20 The synthetic library part implementation '%s' should be \n\ \tavailable for use during the compile command,\n\ \tbut the implementation is not enabled because all of the \n\ \tfollowing limited licenses have been checked out: \n\ \t%s.\n\ \tThe users of the licenses are listed in the following error message.\n W SYNL-21 The license '%s' is not legal and will be ignored\n\ \tfor the synthetic library part implementation '%s'. W SYNL-22 The write cache directory '%s' is not listed\n\t\ as one of the read cache directories.\n\t\ Synthetic library parts written out to the cache\n\t\ cannot be read back from the cache. E SYNL-23 Synthetic module '%s' cannot be linked because port width(s)\n\tcannot be determined. E SYNL-24 Synthetic library '%s'\n\tis from an incompatible version of the software. E SYNL-25 Pin association '%s' does not correspond to \n\ta module pin in binding '%s' for module '%s'. W SYNL-26 Binding '%s' multiply defined for module '%s'.\n\ \t Binding ignored. W SYNL-27 Priority for implementation '%s' of module \n\t'%s' is out of range. Using the default value '%d'. W SYNL-28 Can't find operator pin '%s' for binding '%s' in module '%s'.\n\tBinding ignored. E SYNL-29 Could not check out '%s' or '%s' license.\n\tCannot continue to process the libraries listed in the\n\t'synthetic_library' variable.\n\n\tSet "synlib_evaluation_mode = true" to evaluate parts. E SYNL-30 Could not check out '%s' license.\n\tCannot continue in synlib_evaluation_mode W SYNL-31 IMPORTANT: When the synlib_evaluation_mode variable is\n\ \tset to true, the cache_write variable should be set to a temporary\n\ \tdirectory (and the directory included in the cache_read variable)\n\ \tso that the limited designs will be written there. When synlib_evaluation_mode\n\ \tis returned to false, do not use the temporary directory in \n\ \tcache_write or cache_read. Ignoring this warning will result in limited\n\ \tdesigns being stored in your cache, and when they are retrieved\n\ \tthey will convert your design to a limited design (and disable\n\ \tthe ability to write the designs to a file). W SYNL-32 The synthetic library part implementation '%s' should be\n\ \tavailable for use during the compile command,\n\ \tbut the implementation is not enabled because all of the\n\ \tfollowing licenses have been checked out:\n\ \t%s.\n\ \tWaiting for a license to become available.\n\ \tPress -C to interrupt the command.\n\ \tThe users of the licenses are listed in the following error message.\n E SYNL-33 Missing clock polarity for pipelined part '%s'. E SYNL-34 Missing polarity for asynchronous reset pin '%s' on pipelined part '%'. E SYNL-35 Missing polarity for synchronous reset pin '%s' on pipelined part '%'. E SYNL-36 Missing polarity for pipeline stall pin '%s' on pipelined part '%s'. E SYNL-37 Invalid pipeline stages '%s' is detected on pipelined part'%s'. E SYNL-38 Missing pipeline stages for this pipelined part '%s'. E SYNL-39 Data_class attribute on operator '%s' contains invalid value '%s'. W SYNL-40 Invalid string format '%s' for the permutable_inputs \n\ is detected on operator '%s'. E SYNL-41 Unable to read netlist '%s' for function reference '%s'. E SYNL-42 Unable to find design '%s' in the specified file '%s' \n\ for function reference '%s'. E SYNL-43 Design '%' contains generic logic element '%s' which is \n\ not allowed in an encapsulated function. E SYNL-44 Design '%' contains synthetic component '%s' which is \n\ not allowed in an encapsulated function. E SYNL-45 Design '%' contains hierarchical component '%s' which \n\ is not allowed in an encapsulated function. E SYNL-46 Unable to find function design '%s' for reference '%s' in '%s' root. E SYNL-47 Function '%s' does not have all required attributes of \n\ an encapsulated function. Therefore, this function will not be treated \n\ as a synthetic operator; It will remain to be just a hierarchical component.\ W SYNL-48 Binding '%s' in module '%s' cannot be bound to \n preserved function operator '%s'. Binding is ignored. W SYNL-49 External binding '%s' in library '%s' cannot be\n associated with preserved function module '%s'. Binding is ignored. E SYNL-50 MC doesn't handle gtech technology library. Use Foundation implementations instead.\ E SYNL-51 Some basic cells are missing from the target libraries. These cells are required by MC to build pseudo cell.\ E SYNL-52 Unable to obtain Foundation license to generate\n\ \tsynthetic parts. W SYNL-53 Removing the db file '%s' from the\n\ \ttarget_library list.\ E SYNL-54 No technology library is specified for mce generator to build netlist. Terminate the process.\ W SYNOPT-1 Cache element %s could not be written. W SYNOPT-2 Port %s of synthetic library part %s has invalid direction. W SYNOPT-3 Synthetic library models may be inaccurate because\n\ wire load information is not available from the technology library\n\ (ie: did not find wire_load_from_area or default_wire_load statement in library).\n\ User may want to remove from the cache the models created during this compile command. W SYNOPT-4 Improper octal value for variable cache_file_chmod_octal or cache_dir_chmod_octal: %s W SYNOPT-5 Cannot chmod the cache file or directory %s W SYNOPT-6 The synthetic library 'optimize' parameter value '%s' is not supported. \n\ A parameter value of 'fastest' will be used. W SYNOPT-7 The value 'scaled_to_fastest' for the synthetic library 'optimize' parameter\n\ requires the 'scaled_to_fastest_scale' parameter to be set.\n\ A default value of 1.1 will be used. I SYNOPT-8 Wrote %s as a cache element. I SYNOPT-9 Read %s as a cache element. W SYNOPT-10 The cache_read directory %s is not readable. W SYNOPT-11 The cache_write directory %s is not writable.\n\ So, no cache elements can be written. W SYNOPT-12 Cannot open file %s for writing. Check directory mode bits. W SYNOPT-14 Synthetic library part '%s' does not have an 'optimize' parameter.\n\ The optimize value 'fastest' will be used. I SYNOPT-15 The cache entry '%s'\n\ \tis out of date with respect to its entry\n\ \tin the design library '%s'\n\ \t(module '%s', implementation '%s').\n\ \tThe cache entry has been removed. W SYNOPT-16 The cache entry '%s'\n \ \tshould be removed, but the attempt to remove it has failed.\n\ \tThe entry should be removed because either it is corrupted\n\ \tor it is out of date.\n\ \tAn entry can be out of date with respect to either its entry\n\ \tin the design library '%s' \n\ \t(module '%s', implementation '%s')\n\ \tor its target library '%s'. I SYNOPT-17 The cache entry '%s'\n\ \tis obsolete or has been corrupted, so it is being removed. I SYNOPT-18 The cache entry '%s'\n\ \tis out of date with respect to its target library '%s'.\n\ \tThe cache entry has been removed. W SYNOPT-19 The cache entry '%s'\n \ \tshould be removed, but the attempt to remove it has failed.\n\ \tThe entry should be removed because either it is corrupted\n\ \tor it is out of date.\n\ \tThe entry is out of date with respect to its entry\n\ \tin the design library '%s'\n\ \t(module '%s', implementation '%s'). W SYNOPT-20 The cache entry '%s'\n \ \tshould be removed, but the attempt to remove it has failed.\n\ \tThe entry should be removed because either it is corrupted\n\ \tor it is out of date.\n\ \tThe entry is out of date with respect to its target library '%s'. W SYNOPT-21 The cache_read variable should be a list variable,\n\ \t but it was read as the string variable '%s'.\n I SYNOPT-22 The v3.3b cache element format has changed; removing cache entry \n\ \t'%s'\n E SYNOPT-23 There are %d legal implementations for the sequential module '%s',\n\ \tbut the variable synlib_sequential_module is set \ to 'one_implementation_choice'.\n W SYNOPT-24 The variable synlib_sequential_module is set to\n\ \t'multiple_implementation_choices', so there may be a significant \n\ \tperformance degradation. W SYNOPT-25 The dont_touch on the synthetic library implementation\n\ \t'%s' (module '%s') will be ignored. E TDB-1 Subrange direction does not match array declaration. E TEST-100 Methodology ambiguous, cannot choose between library cells %s and %s. E TEST-101 No ports included in the BSR. A register\n\ \tconsisting of a single shift-register stage must be provided. I TEST-102 GLOBAL tracing enabled for these nets in design '%s': I TEST-103 Output port '%s' is a user-specified three-state\n\ \tenable signal requiring a BSR control cell. I TEST-104 Nets '%s' have been specified\n\ \tfor LOCAL tracing during this vector or stream simulation. I TEST-105 Driven port '%s' characteristic '%s' changed\n\ \tto driving port '%s' characteristic '%s' due to BSR cell optimization. E TEST-106 Critical missing connection(s) encountered while processing\n\ \tbidirectional port `%s'. E TEST-107 Port `%s` can not be a TAP TDO. It is not an output port. W TEST-108 Internal failure: scan equivalence could not create a pseudo-hierarchy for cell %s/%s. W TEST-109 Design '%s' has invalid scan chain information. W TEST-110 Cell %s of type %s is not a test cell. W TEST-111 Test cell %s of type %s is not consistent with the methodology. W TEST-112 Cell %s (%s) is unknown (black box). I TEST-113 Cell %s (%s) is generic. W TEST-114 Type of wired net %s is unknown. W TEST-115 Three-state net %s is not properly driven. W TEST-116 Asynchronous pins of cell %s (%s) are uncontrollable. W TEST-117 Combinational feedback loop broken at pin %s of cell %s (%s). W TEST-118 The design contains unreachable circuitry (closed loops). W TEST-119 Cell %s of type %s is already a test cell. W TEST-120 No scan equivalent exists for cell %s (%s). W TEST-121 Cell %s (%s) can't be made scannable because it is dont_touched.\ W TEST-122 Cell %s (%s) is an unsupported complex latch. I TEST-123 Test design rule checking completed.\ W TEST-124 Violations occurred during test design rule checking.\ W TEST-125 Clock/enable pin %s of cell %s (%s) tied constant. W TEST-126 Clock/enable pin %s of cell %s (%s) has multiple sources. W TEST-127 Clock/enable pin %s of cell %s (%s) has a violated source. W TEST-128 Clock/enable pin %s of cell %s (%s) has internal sources. E TEST-129 Unable to compute signal sense at pin %s of cell %s (%s). E TEST-130 Contradictory path senses converge at pin %s of cell %s (%s). W TEST-131 Data pin %s of cell %s (%s) is driven by a clock/enable signal. W TEST-132 Sequential cell %s (%s) is a black box in combinational scan style I TEST-135 Clock port %s captures data on both edges. W TEST-140 The clock signal to cell %s (%s) is illegally gated. W TEST-141 There is an illegal path to cell %s (%s). W TEST-142 Sequential cell %s (%s) has constant logic 1/0 state. E TEST-143 Dont_touch has been applied to three-state cell `%s`.\n\ \tJTAG synthesis cannot proceed since Boundary Scan Register (BSR) cells\n\ \tcannot be associated with this three-stated port. E TEST-144 Encountered critical unresolved reference trying to\n\ \tprocess cell `%s'. W TEST-145 Pad-mapped JTAG is not IEEE 1149.1 compliant for port `%s`.\n\ \tCell `%s` (library cell type `%s`) has been inserted between the port pad\n\ \tcell and the Boundary Scan Register (BSR) cell. W TEST-152 Design has no scan-in port. E TEST-154 Duplicated test port %s. I TEST-160 BSR cell port drive limit '%d' exceeded.\n\ \tAnother BSR cell will be added to drive signal '%s'. W TEST-163 User scan-chain %d has length %d which exceeds desired maximum.\ W TEST-164 There are %d user scan-chains against only %d requested. W TEST-165 There are too few scan-cells (%d) to build requested chains W TEST-169 Normal mode clock pin %s of cell %s (%s) is uncontrollable. I TEST-170 There are %d other pins with the same violation. I TEST-171 There are %d other cells with the same violation. I TEST-172 There is one other pin with the same violation. I TEST-173 There is 1 other cell with the same violation. W TEST-174 %d scan-chains will be needed, against %d requested. I TEST-175 The loop contains: %s. I TEST-176 Scan insertion did not build any scan chains. W TEST-179 Design has no scan-out port. I TEST-180 Because pin %s of cell %s (%s) is not a three-state driver. I TEST-182 Because input port %s is not a three-state driver. W TEST-186 Shift clock pin %s of cell %s (%s) is illegally gated. W TEST-188 BSR cell optimization has pushed the cell associated\n\ \twith output port '%s' onto input port '%s'. The BSR cell for this input\n\ \tport has been specified as `observe-only'. \n\ \tThis is not compliant with the IEEE 1149.1 JTAG standard. E TEST-189 Three-state cell `%s' (library cell `%s')\n\ \twith missing or erroneous enable pin. W TEST-190 Mismatch between input vectors and design; input vectors are ignored. E TEST-191 Probable library error associated with cell `%s'.\n\ \tNo three-state enable signal associated with pin `%s'. E TEST-192 Dangling port `%s'\n\ \tcannot be included in the JTAG Boundary Scan Register (BSR). E TEST-193 Default JTAG component '%s', of component type\n\ \t'%s' not found in the JTAG component library associated\n\ \twith this design. E TEST-194 -- Intolerable 1149.1 Violation --\n\ \tThree-stated port '%s' is controlled by a feed-through input\n\ \tport '%s' that is excluded from the Boundary Scan Register. I TEST-195 JTAG pad synthesis will NOT include the following ports: I TEST-196 Port '%s' will not have a pad. W TEST-197 Cell %s (%s) is not scan controllable because it has overlapping master/slave clocks. I TEST-198 Because pin %s of cell %s (%s) has a test_isolate attribute. I TEST-199 Because driver %s is a three-state pin of black box cell %s (%s). I TEST-200 Faults on unused cell outputs are not considered, for example pin %s of cell %s (%s). I TEST-201 Faults on unconnected ports are not considered, for example port %s. I TEST-202 Cell %s (%s) will not be scanned due to a set_scan or set_scan_element command. I TEST-203 Faults on bidirectional (INOUT) pins are not considered, e.g. pin %s of cell %s (%s). I TEST-204 Latch cell %s (%s) assumed nonscan and \ using transparent latch model for testing. E TEST-206 Required logic %d on pin %s/%s conflicts with required logic %d on pin %s/%s. E TEST-207 Required logic %d on pin %s/%s conflicts with required logic %d on port %s. I TEST-208 No tests generated - conflicting signal requirements in design.\t Use the 'report_test -atpg_conflicts' command for more information. E TEST-210 Generation of test vectors terminated abnormally. I TEST-211 Scan insertion was not successful. There were unrecoverable processing errors. E TEST-212 Checking of test design rules terminated abnormally. W TEST-213 Making scan cells non-scan to meet area constraints. W TEST-214 Flip-flop-based clock gating is not supported. Cell %s is treated as an ordinary flip-flop and is not scan-replaced. I TEST-220 Starting test design rule checking for existing scan design. I TEST-221 Starting test design rule checking for unrouted scan design. I TEST-222 Starting test design rule checking. W TEST-223 Ignoring set_test_hold on test port '%s'. W TEST-224 Target library for design contains no scan-cell models. W TEST-225 All vectors are asynchronous and thus the design is not a valid scan design. Generated vectors will not be saved. I TEST-230 No BSR or TAP ports with port_is_pad attribute 'TRUE' encountered.\n\ \tJTAG synthesis will not include pad synthesis. W TEST-231 Specified Instruction Register (IR) size (%d) is larger\n\ \tthan the minimum (%d) required by the %d JTAG instructions recognized.\n\ \t(Size specified will be used.) I TEST-232 %d-bit JTAG Instruction Register (IR) being synthesized. E TEST-233 Conflicting routing positions have been assigned to a \ Boundary Scan\n\ \tRegister cell. The conflict occurs because a BSR cell assigned routing\n\ \tposition %d associated with port '%s' has been merged with\n\ \ta BSR cell assigned routing position %d associated with port '%s'. E TEST-234 JTAG component library '%s' not found. I TEST-235 Conflicting JTAG Boundary Scan Register (BSR) membership\n\ \tspecifications encountered. BSR cell optimization has pushed\n\ \tthe '%s' BSR cell associated with port '%s' onto a port\n\ \twhich has been excluded from the JTAG BSR. W TEST-236 JTAG configuration synthesized is not compliant\n\ \twith the IEEE 1149.1 JTAG Standard. E TEST-237 Unable to find pin '%s' of JTAG component '%s'\n\ \tin the JTAG component library '%s'. E TEST-238 JTAG component '%s', associated with option\n\ \tstring '%s' not found in the JTAG component library associated\n\ \twith this design. I TEST-239 %d core scan chain(s) recognized. I TEST-240 Port `%s` BSR cell `%s` is excluded from the BSR. I TEST-241 BSR cell `%s' shifted from position %d to position %d. W TEST-242 TAP input signal `%s` shared with a non-JTAG port. E TEST-243 Shared output signal `%s` cannot be used as TDO. W TEST-244 TAP port `%s` is not dedicated to JTAG.\n\ \tImplementation will be non-compliant. E TEST-245 Component `%s` of type\n\ \t`%s` is missing signal `%s`. E TEST-246 JTAG component `%s` of type\n\ \t`%s`: Erroneous signal `%s` direction `%s`.\n\ \tMust have direction `%s`. I TEST-247 Conflicting JTAG Boundary Scan Register (BSR) membership.\n\ \tBSR cell optimization has pushed the BSR cell associated with port\n\ \t'%s' onto JTAG Test Access Port (TAP) `%s`\n\ \twhich is excluded from the JTAG BSR. W TEST-248 JTAG Test Access Port (TAP) does not include\n\ \tthe asynchronous reset signal TRST. A Default protocol placing the\n\ \tJTAG logic in transparent mode cannot be automatically generated. E TEST-249 Pad exists on port '%s' to be included\n\ \tin the JTAG Boundary Scan Register. The pad must be removed. W TEST-250 Design has no bidirectional port mode information. I TEST-251 Test protocol assumes that bidirectional ports are turned %s during scan shift. I TEST-252 Test protocol assumes that bidirectional ports are turned %s during scan shift. I TEST-253 Test protocol assumes that bidirectional ports are turned %s during scan shift. I TEST-254 Scan insertion turned bidirectional ports %s during scan shift. I TEST-260 Inferred %s clock port %s (%.1f,%.1f). I TEST-261 Inferred active %s asynchronous control port %s. I TEST-262 Inferred capture clock group : %s. W TEST-263 Ignoring "test-hold" on port %s. I TEST-264 This is a(n) %s test protocol W TEST-280 Cell %s (%s) is always asynchronously set/cleared. I TEST-281 The network contains: %s. I TEST-282 The path contains: %s. I TEST-283 Cells with this violation : %s. I TEST-284 Pins with this violation : %s. I TEST-285 Cells with this condition : %s. I TEST-286 Pins with this condition : %s. I TEST-287 Nets with this violation : %s. I TEST-288 There is 1 other net with the same violation I TEST-289 There are %d other nets with the same violation. I TEST-296 There are %d cell%s not scanned because of area constraint. I TEST-297 There are %d cell%s not scanned because \ of timing constraints: %s. I TEST-298 There is 1 other port with the same violation I TEST-299 There are %d other ports with the same violation. I TEST-300 Ports with this violation : %s. I TEST-301 Extending scan in by one cycle because during the first cycle,\n\ \tsome scan chains do not shift in data. W TEST-302 Cell %s (%s) is not scan controllable. I TEST-303 Because asynchronous pin %s is uncontrollable. I TEST-304 Because clock pin %s is uncontrollable. I TEST-305 Because it clocks in an unknown value from pin %s. I TEST-306 Because it scans in an unknown value from cell %s. W TEST-310 Data can not be captured into cell %s (%s). W TEST-311 Data was captured in the master state of cell %s (%s) but scanned out of the slave state. W TEST-312 Data was captured in the slave state of cell %s (%s) but scanned out of the master state. W TEST-313 Data was captured in cell %s (%s) but was lost before it was scanned out of the cell. W TEST-314 Invalid value for variable test_infer_slave_clock_pulse_after_capture, assuming "infer". E TEST-315 Multiple clock groups cannot be pulsed in the same capture cycle. W TEST-320 No nets identified for tracing by name %s. I TEST-321 Trace nets @ %.1f value %s : %s. E TEST-330 Protocol foreach_pattern missing "parallel" cycles. E TEST-331 Pullup/pulldown net %s has illegal driver(s). W TEST-332 Input pin %s of cell %s (%s) is unconnected. It is assumed 'X' for the purpose of test. I TEST-333 Test pin %s of cell %s (%s) is unconnected. It is assumed inactive ('%s') for the purpose of test. E TEST-340 Partial scan logic cannot be inserted in the presence of generic logic. W TEST-341 User specification of chain '%s' has been split. W TEST-342 User specification of chain '%s' has been reordered. W TEST-343 A user-specified wire scan link overrides the\n\ \tinsertion of a lock-up latch before cell '%s'. E TEST-344 Cannot synchronize scan chain cells '%s' and '%s'. Both edges of clock '%s' occur before clock '%s' triggers. E TEST-345 Cannot synchronize scan chain. Connects cell '%s' (triggered by an early transition of clock '%s') to cell '%s' (triggered by a later transition). W TEST-346 There are %d specified scan chains. Cannot honor -chain_count specification of %d. W TEST-347 All specified chains are complete but %d %s not been assigned to a scan chain. Cannot honor -chain_count specification of %d. W TEST-348 Only %d scan chain %s free. Cannot honor -chain_count specification of %d. E TEST-349 Scan logic cannot be inserted in the presence of generic logic. W TEST-350 Cannot identify the core side pin of complex pad %s.\n\t\ Connecting test signal to the port side. W TEST-351 Cannot load object '%s' into chain '%s'. W TEST-352 Scan chain '%s' has zero elements. W TEST-353 %s '%s' has elements clocked by different clocks. W TEST-354 %s '%s' has elements clocked by different clock edges. W TEST-355 Cells with %d new incompatible clock %s have not been assigned to scan chains. Cannot honor -chain_count specification of %d. %s E TEST-356 Segment '%s' has no scan-in pin. E TEST-357 Segment '%s' has no scan-out pin. W TEST-358 Cannot use port '%s' as a '%s'. It's net has a dont_touch attribute. W TEST-359 %d bidirectional %s degenerated. Please check the test protocol. I TEST-360 Because independent scan data cannot be shifted into cells %s from cell %s. W TEST-361 Scan chain originating from port '%s' diverges after %s. W TEST-362 Scan chain originating from '%s' is not scan observable. The chain terminates at cells %s. W TEST-363 Scan chain terminating at '%s' is not scan controllable. The chain originates from cell %s. W TEST-364 Clock pin(s) of cell %s (%s) are not correctly set to their inactive state. I TEST-365 As a result, the following cells are not scan controllable: %s. W TEST-366 %d conditioned bidirectional %s not being forced %s. Please check the test protocol. W TEST-367 Scan link '%s' cannot be inserted inside the segment '%s'. It will be inserted at the end of this segment. W TEST-368 Cannot build functional scan chain for \ segment '%s', because the user specification violates\ the clock domain constraint. W TEST-370 Scan chain %d comprises user-specified cells from different clock domains. W TEST-371 Consecutive scan cells %s and %s are clocked by different clocks. W TEST-372 Consecutive scan cells %s and %s are clocked\ by different edges of the same clock. E TEST-373 Sequential cell %s (%s) has no clock information.\n\tIt will not be assigned to a scan chain. W TEST-374 Clock information for all sequential cells of design is missing. W TEST-375 Cannot add '%s' to chain '%s'. It already belongs to another chain. W TEST-376 Cannot add '%s' to chain '%s'. The element is not being scanned. W TEST-377 Cannot add '%s' to chain '%s'. The element already belongs to chain '%s'. W TEST-378 Cannot add '%s' to chain '%s'. The element already belongs to user segment '%s'. W TEST-380 Force simulation of multiple capture clocks. W TEST-381 Clock net '%s' is dont_touch. E TEST-382 Clock gating for partial scan aborted since\n\ \tnets that will be modified are marked as dont_touch. W TEST-383 Cell %s (%s) is not supported because it is a \ sequential cell with tristate outputs. Treating as black box. W TEST-384 Can't find clock to gate for non-scan cell '%s'. W TEST-385 Cannot find the core-side hookup pin for port %s.\n\t\ There are %d %s connected to it that are tristate or on pads.\n\t\ Connecting test signal to a new, dedicated test signal port. W TEST-386 Cannot find the core-side hookup pin for port %s.\n\t\ %d illegal active %s connected to it.\n\t\ Connecting test signal to a new, dedicated test signal port. W TEST-387 Cannot find the core-side hookup pin for port %s.\n\t\ Hookup pin design instance %s has a dont_touch attribute.\n\t\ Connecting test signal to a new, dedicated test signal port. W TEST-388 Cannot identify the core side pin of complex cell %s.\n\t\ Connecting test signal to a new, dedicated test signal port. W TEST-389 Cannot identify the core side pin of complex pad %s.\n\t\ Connecting test signal to a new, dedicated test signal port. W TEST-390 Multiple pullups and/or pulldowns found for net '%s'. W TEST-391 Net '%s' is not three stateable.\n\ \tRemoving all pullups and/or pulldowns. W TEST-392 Disconnecting pin '%s' to route global signals. W TEST-393 Pin '%s/%s' has a signal_type attribute %s that conflicts with its access pin type %s.\n W TEST-394 Disconnecting pin '%s' to route scan enable. W TEST-395 Can not unscan cell '%s' of type '%s'. No target library cell has it as its scan equivalent. W TEST-396 Cannot find the core-side hookup pin for port %s.\ Net %s, driven by this port, has illegal active drivers.\ Connecting test signal to a new, dedicated test signal port. W TEST-397 The scan out pin on cell '%s' in chain '%s' already drives the scan \ out port '%s'. No new dedicated scan out ports will be created on subdesigns. W TEST-398 Can not unscan cell '%s' of type '%s'. W TEST-401 Synchronization element %s(%s), clocked by capture clock %s, is in an unsupported configuration. I TEST-402 Because some sequential cells in its transitive fan-in and some sequential cells in its transitive fan-out are not clocked by capture clock %s. I TEST-403 Pin %s of cell %s in the transitive fan-in is clocked by capture clock %s. I TEST-404 Pin %s of cell %s in the transitive fan-out is clocked by capture clock %s. I TEST-405 Because a synchronization element is in its transitive fan-in. I TEST-406 Pin %s of synchronization element %s(%s) is in the transitive fan-in. I TEST-421 `SAMPLE' instruction renamed `SAMPLE/PRELOAD'. I TEST-424 TCK clock frequency `%e', calculated\n\ \tfrom clock period `%f', and technology library `%s'\n\ \ttime scale `%d' in units of `%s'. W TEST-425 Unable to calculate TCK frequency for technology library `%s'. I TEST-427 TCK clock frequency `%e', calculated\n\ \tfrom default clock period `%f', and technology library `%s'\n\ \ttime scale `%d' in units of `%s'. W TEST-428 The length of the RUNBIST signature (%d) does not equal the length of the '%s' register selected by the RUNBIST instruction. W TEST-429 The parameters for the '%s' instruction have been defined but the instruction could not be found in the design '%s'. W TEST-430 The subdesign scan chain '%s' is assumed to be non-inverting. W TEST-431 The scan segment '%s' is assumed to be non-inverting. I TEST-440 Combinational feedback loop is disabled at pin %s of cell %s (%s) by constant values. I TEST-441 Combinational feedback loop is disabled at pin %s of cell %s (%s) by logical values present during initialization. E TEST-447 Non-compliant Boundary Scan logic will be synthesized.\n\ \tInverting three-state output drivers encountered. E TEST-449 Wired logic driving output port '%s' encountered. W TEST-451 Cell %s (%s) is unknown (black box) because functionality for output pin %s is bad or incomplete. W TEST-452 Cell %s (%s) is unknown (black box) because output pin %s is always an X. W TEST-453 Cell %s (%s) is unknown (black box) because output pin %s is three-state but does not have a three-state function specified. I TEST-454 Because the information in the library db is incomplete\nor inconsistent. For this cell, the current version of Library Compiler\nissues the following message(s):\n\t"%s" W TEST-461 Generic sequential cell %s (%s) is not supported because both clocks are used. This cell is being black-boxed. W TEST-462 Cell %s (%s) is not supported because it has too many states (%s states). This cell is being black-boxed. W TEST-463 Master-slave cell %s (%s) is not supported because state pin %s is neither a master nor a slave. This cell is being black-boxed. W TEST-464 Master-slave cell %s (%s) is not supported because there are two or more master states. This cell is being black-boxed. W TEST-465 Master-slave cell %s (%s) is not supported because there are two or more slave states. This cell is being black-boxed. W TEST-466 Cell %s (%s) is not supported because the state pin %s has no clocks. This cell is being black-boxed. W TEST-467 Cell %s (%s) is not supported because the state pin %s is multi-port. This cell is being black-boxed. W TEST-468 Cell %s (%s) is not supported because it is a sequential cell with three-state outputs. This cell is being black-boxed. I TEST-470 Test design rule checking terminated with errors. W TEST-471 Asynchronous control pin %s of cell %s (%s) can change in the capture cycle. This can cause the cell to capture unreliably. I TEST-472 Cell %s launches response data from pin %s at %s edge of clock port %s (pin %s) at time %s. I TEST-473 Cell %s captures data on pin %s at %s edge of clock port %s (pin %s) at time %s. I TEST-474 There is a path from %s to %s. I TEST-476 Response data launched from the source register \ can cause a change on asynchronous control pin %s of cell %s. I TEST-477 Enable pin %s of cell %s becomes active at %s edge of clock port %s at time %s. W TEST-478 Pin %s of cell %s (%s) cannot capture reliably. I TEST-479 Cell %s launches response data from pin %s prior to the start of the capture cycle. E TEST-480 The following compliance enable port is a TAP port: '%s'. E TEST-481 The following compliance enable ports are TAP ports: E TEST-482 The '%s' port in the port-to-pin map for the \ package '%s' is not a port of the design '%s'. E TEST-484 The '%s' port of the design '%s' is missing from the\ port-to-pin map for the package '%s'. W TEST-486 The maximum line length specified must be at least %d. Using a value of %d as the maximum line length. W TEST-486b The maximum line length specified must be at most %d. Using a value of %d as the maximum line length. I TEST-487 Opened BSDL file '%s' for writing. E TEST-488 No valid packages were found for the design '%s'. W TEST-489 No default device package has been specified for the design '%s'. E TEST-490 No signal ports were found for the design '%s'. W TEST-491 No linkage ports were found for the design '%s'. W TEST-492 BSDL atom '%s' is longer than the maximum number of characters allowed in a line. W TEST-493 The following %s name %sis an illegal BSDL identifier: '%s'. W TEST-494 The following %s names %sare illegal BSDL identifiers: W TEST-495 The following %s name %sis a %s reserved word: '%s'. W TEST-496 The following %s names %sare %s keywords: W TEST-497 The JTAG test clock frequency has not been specified. Using a default value of 10.0 MHz as the JTAG test clock frequency. I TEST-498 Successfully generated BSDL file '%s'. W TEST-499 Violations occurred during IEEE 1149.1 compliance checking. W TEST-500 Physical design information is not available. The preview_scan command is running in -command insert_scan mode. I TEST-501 As a result, 1 other cell is not scan controllable. I TEST-502 As a result, %d other cells are not scan controllable. I TEST-503 As a result, 1 other cell is not scan controllable : %s. I TEST-511 Because asynchronous pin %s is uncontrollable. I TEST-512 Because it clocks in an unknown value from pin %s. I TEST-513 Because pin %s of cell %s (%s) is unknown. I TEST-514 Because port %s is unknown. I TEST-515 Because clock pin %s is uncontrollable. I TEST-516 Because cell did not receive a clock pulse. I TEST-517 Because cell did not receive scan-in data from an input port. I TEST-518 Because an illegal input combination was applied: Pin %s was %s. I TEST-519 Because clock is used as data on pin %s. I TEST-520 Because cell is set_scan or set_scan_element false. I TEST-521 Because pin %s of cell %s (%s) is unknown due to a set_test_isolate command. I TEST-522 Because pin %s of cell %s (%s) is unknown due to a previously reported violation. I TEST-523 Because port %s is unknown due to a set_test_isolate command. I TEST-524 Because port %s is unknown due to a previously reported violation. I TEST-525 Because cell contains data that was in cell %s (%s) at the start of scan shift. I TEST-526 Because input pin %s of cell %s (%s) is unconnected. I TEST-540 The drivers of the cone of logic ending at pin %s of cell %s (%s) are listed below. I TEST-541 Port %s is %s. I TEST-542 Port %s is %s due to a set_test_isolate command. I TEST-543 Port %s is %s due to a previously reported violation. I TEST-544 Port %s is a scan-in value. I TEST-545 Pin %s of cell %s (%s) is %s. I TEST-546 Pin %s of cell %s (%s) is %s due to a set_test_isolate command. I TEST-547 Pin %s of cell %s (%s) is %s due to a previously reported violation. I TEST-548 Pin %s of cell %s (%s) is a scan-in value. I TEST-549 Pin %s of cell %s (%s) is the value of pin %s of sequential cell %s (%s). E TEST-550 %s condition detected on bidirectional port %s. I TEST-551 Because the value of port %s in the protocol is %s. I TEST-552 The three-state cell %s is %s because of \ the following input pin values: %s. W TEST-554 Three-state net %s has both pull-up and pull-down \ resistor cells. I TEST-555 Pull-up cell%s: %s. I TEST-556 Pull-down cell%s: %s. W TEST-557 Bidirectional port %s with test_isolate attribute has inconsistent protocol value %s. Protocol value is ignored. E TEST-558 The variable atpg_bidirect_output_only is set \ to "true", but the bidirectional port %s cannot be forced into output mode. \ No vectors can be generated. I TEST-559 Bidirectional port %s changes value to %s at time %s. I TEST-560 check_test will not check for port changes \ that cause unreliable capture, because the variable \ test_check_port_changes_in_capture is set to "false". I TEST-561 Because bidirectional port driver %s is active. E TEST-562 %s condition detected on bidirectional port %s during scan shift. W TEST-563 Net %s, connected to bidirectional port %s, has three-state driver(s) with unknown mode during scan shift. I TEST-564 Port %s is attributed as %s. I TEST-565 Bidirectional port %s is inferred as %s. W TEST-566 %s condition detected on bidirectional port %s during scan shift. I TEST-567 The preceding violation will prevent test pattern generation. E TEST-568 Some test design rule checking violations prevent test vector generation. I TEST-569 The open-drain or open-source port %s cannot \ be used as a scan output. W TEST-580 All cells in multibit '%s' will not be scanned due to an explicit specification on cell '%s'. W TEST-581 All cells in multibit '%s' will be transparent due to an explicit specification on cell '%s'. W TEST-582 All the cells in multibit '%s' are violated. I TEST-583 Because multibit member cell '%s' is previously violated. I TEST-584 The multibit contains: %s. I TEST-585 There are %d other multibits with the same condition. I TEST-586 There is 1 other multibit with the same condition. W TEST-587 Multibits are ignored for partial scan selection. W TEST-588 Cannot model multibit cell %s; treating it as a black box. W TEST-590 Multibit specification on multibit component '%s' ignored. W TEST-591 There exists a cell %s on the bus which is not controllable. So the tristate disabling logic on this bus is not synthesized. W TEST-592 There is a contention while controlling cell %s on the bus. So the tristate disabling logic on this bus is not synthesized. I TEST-593 All cells in multibit component '%s' are violated. W TEST-601 Inferring default device package '%s'. I TEST-801 There is 1 such other violation. I TEST-802 There are %d such other violations. E TEST-811 Mandatory IEEE 1149.1 test port %s missing. E TEST-812 NO IEEE 1149.1 test ports have been identified. E TEST-813 %s TAP Controller state flops have been found, which is an insufficient number of state flops. There must be at least four. E TEST-814 TAP controller makes an illegal transition from state %s to state %s with TMS at logic value %s. The TAP controller should make transition to state %s. E TEST-815 Low halt state for TCK does not exist. E TEST-816 TRST does not reset TAP controller asynchronously. TRST specification ignored. W TEST-816a TRST reset TAP controller synchronously but not asynchronously. TRST specification ignored. E TEST-816b TAP controller is not reset at power up. E TEST-817 TDO driver can not be active in the TAP controller state %s. E TEST-818 TDO driver must be active in TAP Controller state %s. W TEST-819 Undriven input port %s is floating. When undriven, this port should behave as though it was driven by logic one. W TEST-821 TDO should not change on the rising edge of TCK in the TAP controller state %s. W TEST-822 TAP Controller should not be reset by the functional input %s. A dedicated reset port or power-up sequence is required. E TEST-823 TAP controller can not be initialized by the synchronizing sequence of 11111 on TMS. I TEST-824 Data is inverted during shift from TDI to TDO at cell %s of the shift register. I TEST-824a Data is inverted during shift from TDI to TDO at the TDO port cell %s. W TEST-824b Data is inverted during shift from TDI to TDO at cell %s of the shift register. E TEST-825 Cannot access Instruction Register during the shift-IR TAP controller state. E TEST-826 Illegal Instruction Register Length %s. E TEST-828 The capture value of the least significant bits\n\ \tin the instruction register is %s%s. It must be the fixed pattern "01". W TEST-829 The length of Device Identification Register is %s. It should be 32. W TEST-830a Unable to access any Register to be serially connected between TDI and TDO in the Test-Logic-Reset state. E TEST-832 Cannot access BYPASS Register during the shift-DR TAP controller state with the "all ones" instruction opcode. E TEST-834 Cannot access Boundary Scan Register during the shift-DR TAP controller state with the "all zeros" instruction opcode. E TEST-835 The capture value of the least significant bit in the Device Identification Register is logic zero. It must be logic one. E TEST-836 Illegal manufacturing code %s has been captured in the Device Identification Register. W TEST-837 No Register is selected to connect between TDI and TDO during instruction opcode %s. W TEST-838 A boundary scan register cell is missing on design INPUT port %s. W TEST-838a A boundary scan register cell is missing on design OUTPUT port %s. E TEST-839 A boundary scan register cell %s cannot be placed on TAP port %s. W TEST-840 A boundary scan register cell %s cannot be placed on compliance port %s. E TEST-841 Not able to infer the mandatory SAMPLE/PRELOAD instruction. W TEST-843 Logic cannot exist between boundary scan cell %s and design port %s. E TEST-844 The Instruction Register Update flops update on the rising edge of TCK instead of falling edge of TCK. W TEST-845 The compliance-enable pattern %s do not cause the component to be fully compliant with this standard. This pattern is being removed from the set of patterns. E TEST-846 The Boundary Scan Register Update flops update on the rising edge of TCK instead of falling edge of TCK. W TEST-847 The BSR Update flops illegally update during Update-DR under CLAMP instruction. W TEST-848 The BSR Update flops illegally update during Update-DR under RUNBIST instruction, while selecting annother TDR as shift register. W TEST-849 The tristate pin %s on\n\ \tthe cell %s has multiple Boundary-Scan Register controlling cells. W TEST-850 Initialization using TMS synchronizing sequence "11111" does not match the initialization using the TRST port or power-up sequence. This process will continue by using the TMS synchronizing sequence. E TEST-850a No external method to reset the TAP controller (such as TRST port or power-up) has been provided. This process will continue by forcing logic values on the TAP controller state elements. E TEST-851 The shift flops of Instruction Register are not clocking on the positive edge of TCK during the Capture-DR TAP Controller state. I TEST-854 There is a break in the shift register chain\n\ \tdue to cell %s being driven by an inactive element. I TEST-855 There is a break in the shift register chain\n\ \tdue to test data out (TDO) port not being driven by the shift register chain. W TEST-856 The design TDO port %s is not enabled. W TEST-857 Synchronous mode for the shift register was not inferred. There seems to be break in the shift register. W TEST-858 The update elements of the instruction register should not be reset on the rising edge of test clock TCK. W TEST-860 Boundary scan register cell %s is illegally merged. Only an input function can be merged with an output or control function. W TEST-860a Boundary scan register cell %s is illegally merged. The merged cell contains more than two functions. W TEST-861 The boundary scan register cells are not able to update the update flops, when the TAP Controller changes state from Capture-DR to Update-DR through Exit-DR only. These cells do update the update flops, when the TAP Controller changes state from Capture-DR to Update-Dr through Shift-DR. I TEST-864 This problem occurred because TDO port %s is\n\ \tdriven by a constant source. I TEST-865 The TDO port %s is not enabled during the shift-DR TAP controller state. W TEST-870 Design port %s is not forced to inactive state during the instruction opcode %s. E TEST-871 Illegal capture descriptor on the bsr cell %s for the instruction opcode %s for instruction %s. The capture source is %s. W TEST-872 Illegal Capture source descriptor for the EXTEST instruction on the input bsr cell %s. It should be primary input ports. E TEST-873 Illegal output conditioning during the EXTEST instruction on the output bsr cells. It should be conditioned by BSR cells. W TEST-874 The logic state of design port %s is not driven by the boundary scan register BSR cell %s during the instruction opcode %s. W TEST-875 The boundary scan register cell %s is not able to capture the logic state of design input port during the instruction opcode %s. E TEST-876 The output pin of the boundary scan register cell %s is not being driven by the update flop during EXTEST instruction with opcode %s. W TEST-877 The output pin of the boundary scan register cell %s is not being driven by the input pin during the instruction %s with opcode %s. W TEST-878 The capture value of the boundary scan register cell %s is not from the input pin %s during instruction with opcode %s. E TEST-879 Not able to locate a parallel output for the input boundary scan register cell %s. W TEST-880 A shift register of length %s has been selected for the BYPASS instruction with "all-ones" instruction opcode. The register should be of length one. E TEST-881 Illegal capture value of BYPASS register. W TEST-882 Illegal number of capture descriptors for the boundary scan register cell %s. W TEST-883 The TAP controller makes an illegal state transition from state %s to state %s with test clock TCK at the low halt state. E TEST-884 Illegal change in the TAP Controller state %s to state %s at TCK high halt state. E TEST-885 Illegal test clock TCK halt state. W TEST-886 The parallel output of the boundary scan register cell %s is not driven by the update flop using opcode %s, which is the INTEST instruction. W TEST-887 The parallel output of a clock boundary scan register cell %s is not driven according to rule 10.5.1g during %s with opcode %s. E TEST-888 The parallel output of an input boundary scan register cell %s is not driven by the parallel input with opcode %s, which is the SAMPLE instruction. W TEST-889 Boundary scan register cell %s is not standard(BC_0 to BC_7). This will be defaulted to BC_0 in the output BSDL. W TEST-890 Not able to locate the parallel input for the boundary scan register cell %s. E TEST-891 Not able to locate the parallel output for the boundary scan register cell %s. E TEST-892 Not able to locate the parallel output for the control boundary scan register cell %s. E TEST-893 Not able to locate the parallel input for the control boundary scan register cell %s. E TEST-894 Not able to locate the parallel input for the output boundary scan register cell %s. E TEST-895 Not able to locate the parallel output for the input boundary scan register cell %s. E TEST-898 The boundary scan register cell %s is not a valid cell type. I TEST-899 Scan routing is not complete. Signals '%s' need to be routed. I TEST-901 This problem occurred because design input\n\ \tport %s controls the logic. I TEST-902 This problem occurred because pin %s of\n\ \tcell %s drives a multiple driver net. I TEST-903 This problem occurred because the\n\ \tcell %s is black boxed. I TEST-904 This problem occurred because pin %s of\n\ \tthe cell %s is driven by a constant source. I TEST-905 This problem occurred because pin %s of the\n\ \tcell %s is driven by a weak 'z' signal. I TEST-906 This problem occurred because cell %s has\n\ \tmultiple inputs with indexed scan tokens. I TEST-907 This problem occurred because x-bdd of\n\ \tpin %s of cell %s is one. I TEST-908 This problem occurred because the asynchronous\n\ \tinput to cell %s is unknown. I TEST-909 Because the clock input to cell %s is unknown. I TEST-910 This problem occurred because the TMS port is\n\ \tcontrolled by design input port %s. I TEST-911 This problem occurred because TRST port\n\ \tis controlled by design input port %s. I TEST-912 This problem occurred because TCK port is\n\ \tcontrolled by design input port %s. I TEST-913 The sequential cell %s is driven by constant source. I TEST-914 This problem occurred because pin %s on the\n\ \tcell %s is unconnected. I TEST-915 This problem occurred because pin %s on\n\ \tthe cell %s has controlling value. I TEST-916 This problem occurred because port %s is unconnected. I TEST-917 This problem occurred because the tristate pin %s on\n\ \tthe cell %s has multiple controlling cells. I TEST-918 This problem occurred because the pin %s on\n\ \tthe cell %s is driven by multiple BSR cells. E TEST-930 NO Pad cell have been found on the design port %s. E TEST-931 Multiple Pad cells have been found on the design port %s. E TEST-932 Pad cell %s attached to design port %s is a black box. E TEST-933 The Bi-directional Pad cell %s attached to design port %s has no core logic output pin. E TEST-934 The Input Pad cell %s attached to design port %s has no core logic output pin. E TEST-935 The 3-State Output Pad cell %s attached to design port %s has no core logic input pin. E TEST-936 The 2-State Output Pad cell %s attached to design port %s has no core logic input pin. E TEST-937 The 3-State Output Pad cell %s attached to design port %s has no enable pin. W TEST-938 Design '%s' must be scan-replaced or scan-routed. I TEST-939 Scan chain reordering was not successful. There were unrecoverable processing errors. I TEST-940 Cumulated distance before and after scan reordering\n\ \tcould not be computed because XY information for scan cells\n\ \tis partial or unexistent. I TEST-941 Scan chain is user specified with '-complete true'.\n\ \tThe initial ordering of segments is not disturbed. I TEST-942 Scan chain is user specified with '-complete false'\n\ \tor split/reordered to meet clock domain constraints.\n\ \tThe reordering is done respecting user-segment positions. W TEST-943 All design output ports do not have tri-state pads. Hence HIGHZ instruction cannot be implemented. Removing the HIGHZ specification. W TEST-944 The IDCODE instruction has been specified, but \ appropriate environment variables have not been set to specify a\ valid, nonzero manufacturer identity, part number and version. W TEST-945 Illegal value for manufacturer_id. It can not be 00001111111 (127 decimal). W TEST-946 Overflow in the value asigned to manufacturer_id, part_number or version_number. E TEST-947 Boundary-Scan has already been inserted using 'insert_bsd' command.. E TEST-948 LSI 4-pattern STIL protocol could not be generated because no primary input bidirectional control signal has been specified. W TEST-953 Signal %s(%s, %s) drives clock inputs\n\tof %d flip-flops but is not reached by any test clock. W TEST-954 Signal %s(%s, %s) drives clock inputs\n\tof %d latches but is not reached by any test clock. I TEST-957 There are %d asyncs in the design. I TEST-958 There are %d test clocks in the design. I TEST-959 There are %d blackboxes in the design. W TEST-960 Sensitizable feedback loop detected at\n\t%s(%s, %s). W TEST-961 Clock pins of %d flip-flops are floating. W TEST-962 Clock pins of %d latches are floating. W TEST-963 Clock %s reaches %d flip-flops\n\tbut does not control them at beginning of cycle. W TEST-964 Clock %s reaches %d latches\n\tbut does not control them at beginning of cycle. W TEST-965 Clock %s reaches %d latches\n\tbut does not hold data in them at beginning of cycle. W TEST-966 No asynch reaches %d flip-flops with asynch control. W TEST-967 No asynch reaches %d latches with asynch control. W TEST-968 Asynch %s reaches %d flip-flops\n\tbut can not disable their asynch controls. W TEST-969 Asynch %s reaches %d latches\n\tbut can not disable their asynch controls. W TEST-970 Clock %s affects data inputs of %d flip-flops. W TEST-971 Clock %s affects data inputs of %d latches. W TEST-972 Clock %s affects both clock and data of %d flip-flops. W TEST-973 Clock %s affects both clock and data of %d latches. W TEST-974 Latch enabled by clock %s affects data\n\tinputs of %d latches on the same clock. W TEST-975 Latch enabled by clock %s affects data\n\tinputs of %d flip-flops\n\tclocked by the trailing edge of the same clock. W TEST-976 Clocks %s and %s cannot capture\n\ton %d latches with the other off. W TEST-977 Clocks %s and %s both capture on %d flip-flops. W TEST-978 Signal %s(%s, %s) illegally combines\n\tclock %s and latch data to clock %d flip-flops. W TEST-979 Signal %s(%s, %s) illegally combines\n\tclock %s and latch data to clock %d latches. W TEST-980 Signal %s(%s, %s) illegally combines\n\tclock %s and flip-flop data to clock %d flip-flops. W TEST-981 Signal %s(%s, %s) illegally combines\n\tclock %s and flip-flop data to clock %d latches. W TEST-982 Black box instance %s(%s, %s) feeds\n\tdata inputs of %d flip-flops. W TEST-983 Black box instance %s(%s, %s) feeds\n\tdata inputs of %d latches. W TEST-984 Black box instance %s(%s, %s) feeds\n\tclock inputs of %d flip-flops. W TEST-985 Black box instance %s(%s, %s) feeds\n\tclock inputs of %d latches. W TEST-986 Black box instance %s(%s, %s) feeds\n\tasynchronous control inputs of %d flip-flops. W TEST-987 Black box instance %s(%s, %s)\n\tfeeds asynchronous control inputs of %d latches. W TEST-988 Black box instance %s(%s, %s)\n\treceives data from %d flip-flops. W TEST-989 Black box instance %s(%s, %s)\n\treceives data from %d latches. W TEST-990 Black box instance %s(%s, %s)\n\tfeeds %d output ports. W TEST-991 Black box instance %s(%s, %s)\n\treceives data from %d input ports. W TEST-992 The argument to set_scan_register_type -type\ does not contain a valid scan equivalent for cell or design %s.\ Ignoring the -type specification and replacing %s with the best match. E TEST-993 Design has more than 6 TEST CLOCKs and TEST ASYNCs. W TEST-994 Clock %s affects multiple clock or asynch ports of %d registers.\ I TEST-995 %s (%s, %s) E TEST-996 Can not optimize the Boundary-Scan logic. Boundary-Scan logic is not inserted using 'insert_bsd' command. I TEST-997 Design has %d transparent latches. E TEST-998 Design has %d ports defined as both \n\tTEST CLOCKs and TEST ASYNCs. W TEST-999 Removing the 'set_scan_register_type' on the bit %s of multibit. E TEST-1001 Cannot open file %s in read or write mode. E TEST-1002 Error %s near %s at line number %d. E TEST-1003 Syntax errors found while parsing file %s. E TEST-1004 Scan flip-flop %s, specified in the place and route\ report file, was not found in scan chain %s of design. E TEST-1005 You must specify a target place and route\ tool using \fBset_scan_configuration -prtool\fP. E TEST-1006 Combinational logic found between %s and %s;\ you cannot use combinational logic in the scan path between \ scan flip-flops. E TEST-1007 Cannot create a net between two pins. E TEST-1008 Cannot find a scan-in pin for cell %s. E TEST-1009 Cannot find a scan-out pin for cell %s. E TEST-1010 Scan chain name %s in place and route report\ file differs from original name. E TEST-1011 Scan cell pins are not loaded properly. E TEST-1012 Invalid scan configuration. \ The number of scan chains, %d, specified by \fBset_scan_configuration -chain_count\fP,\ does not agree with the number of scan chains, %d, in the place and route\ report file. E TEST-1013 Invalid scan configuration. The \fBset_scan_configuration \ -add_lockup\fP is set to \fIfalse\fP, but there are lockup latches in the\ place and route report file. E TEST-1014 Invalid scan configuration. \ The clock mixing specification is inconsistent between the place and route \ report file and the scan configuration. W TEST-1201 The bidirectional port '%s' is degenerated. Please check the test protocol. W TEST-1202 The conditioned bidirectional port '%s' is not being forced '%s'. Please check the test protocol. E TEST-1203 '%s' is not a valid disable type for the internal tristate net '%s'. E TEST-1204 '%s' is not an internal or external tristate net. E TEST-1205 Multiple conflicting disabling options found for net. E TEST-1206 Multiple conflicting bidirectional conditioning specifications found. W TEST-1207 No disabling logic will be added on the net '%s' because it has some dont_touch'ed drivers. I TEST-1208 Cells with the dont_touch attribute : %s W TESTDB-1 Overwriting existing scan style %s. E TESTDB-2 Unable to create test vectors database file. E TESTDB-3 Unable to read test vectors database file '%s'. E TESTDB-4 Invalid test vector database file '%s'. W TESTDB-5 User defined test protocol deleted. E TESTDB-6 Port '%s' has an undefined direction.\n\ \tUnpredictable behavior might result. W TESTDB-100 Renaming port from '%s' to '%s'. E TESTDB-200 Badly placed '}' (line: %d). E TESTDB-201 test_protocol() group must be the first group in the protocol definition (line: %d). E TESTDB-202 Only one test_protocol() may be defined per file (line: %d). E TESTDB-203 The protocol_start() group only allowed within the test_protocol() group (line: %d). E TESTDB-204 The foreach_program() group only allowed within the protocol_start() group (line: %d). E TESTDB-205 The foreach_pattern() group only allowed within the foreach_program group (line: %d). E TESTDB-206 Illegally nested vector() group (line: %d). E TESTDB-207 Only one protocol_start() may be defined per protocol (line: %d). E TESTDB-208 Only one foreach_program() may be defined per protocol (line: %d). W TESTDB-209 Comments appearing before protocol_start() are ignored (line: %d). E TESTDB-210 Invalid vector() repetition value (line: %d). E TESTDB-211 set() statement only allowed within a vector() or stream() group (line: %d). E TESTDB-212 Invalid set() statement (line: %d). E TESTDB-213 Incorrect number of ports and signal values in assign() statement (line: %d). E TESTDB-214 Incorrect value '%s' for port '%s' (line: %d). E TESTDB-215 '%s' is not a port on the design (line: %d). E TESTDB-216 Invalid value '%s' for port '%s' (line: %d). E TESTDB-217 Invalid define_port_set() statement (line: %d). E TESTDB-218 Ambiguous use of the value replicator '[]' (line: %d). E TESTDB-219 Illegally nested stream() group (line: %d). E TESTDB-220 Invalid stream() repetition value (line: %d). E TESTDB-221 Unknown attribute '%s' (line: %d). E TESTDB-222 Attribute '%s' is not allowed within this group (line: %d). E TESTDB-223 Value of attribute '%s' must be a float (line: %d). E TESTDB-224 Value of attribute '%s' must be a list of two float values (line: %d). E TESTDB-225 Value of attribute '%s' must not be less than zero (line: %d). E TESTDB-226 The clock() group only allowed with the test_protocol() group (line: %d). E TESTDB-227 The clock period is not specified for the clock() group (line: %d). E TESTDB-228 The rise/fall waveform is not specified for the clock() group (line: %d). E TESTDB-229 The clock port sources is not specified for the clock() group (line: %d). E TESTDB-230 The trace_nets() statement only allowed within vector() and stream() groups (line: %d). E TESTDB-231 The trace_nets() statement takes a single string only (line: %d). W TESTDB-232 Can not specify strobe_width without specifying strobe time. Strobe_width specification ignored. E TESTDB-233 Can not specify a negative number for %s (%10.2f) E TESTDB-234 only a single value should be defined for the period of the tester cycle (line: %d). E TESTDB-235 Illegal symbolic values in set statement not nested in\ pattern group (line: %d). E TESTDB-236 Only one foreach_pattern() may be defined per protocol (line: %d). E TESTDB-237 Illegal symbolic values in set statement of stream group (line: %d). E TESTDB-238 Si and Pi/Po/Pio/Cp cannot be assigned in the same set statement (line: %d). E TESTDB-239 Illegal multiple strobing/capture vectors (line: %d). E TESTDB-240 Protocol foreach_pattern group missing parallel cycle (line: %d). E TESTDB-241 Scan-in operation occurs after parallel cycle (line: %d). E TESTDB-242 Illegal value U for port '%s' for first vector group (line: %d). E TESTDB-243 define_port_set is only allowed within test_protocol group (line: %d). E TESTDB-244 Illegal value U for port '%s' (line: %d). E TESTDB-245 Illegal value '%s' for non-clock port '%s' (line: %d). E TESTDB-246 Illegal value '%s' for clock port '%s' (line: %d). E TESTDB-247 Illegal parallel input vector (line: %d). E TESTDB-248 Parallel input vector changed before strobing (line: %d). E TESTDB-249 Parallel input vector changed before capturing (line: %d). E TESTDB-250 Illegal timing relationships between data, clock and strobe (line: %d). E TESTDB-251 So and Pi/Po/Pio cannot be assigned in the same set statement (line: %d). E TESTDB-252 Parallel input values are multiply defined for port '%s' (line: %d). I TESTDB-253 Foreach pattern section is being ignored E TESTDB-254 Scan chain specification '%s' includes repeated elements. W TESTDB-255 Scan chain '%s' overwrites an earlier specification. E TESTDB-256 Scan chains '%s' and '%s' have common elements. W TESTDB-257 Overwriting previously specified '%s' port '%s'. W TESTDB-258 Overwriting previously specified signal on port '%s'. Signal type '%s' conflicts with old type '%s'. W TESTDB-259 Overwriting previously specified scan signal on port '%s'. Access pin '%s' conflicts with old pin '%s'. W TESTDB-260 Overwriting previously specified '%s' for chain '%s'. W TESTDB-261 Overwriting scan signal '%s'. Can not share access pin '%s' with signal '%s'. W TESTDB-262 '%s' is the name of an existing scan link. It will be overwritten. E TESTDB-263 Scan chains '%s' and '%s' have common elements. Segment states are considered. E TESTDB-264 An existing scan segment has the name '%s'. Scan link specification is discarded. E TESTDB-265 Scan segment specification '%s' includes repeated elements. W TESTDB-266 Scan segment '%s' updates an earlier specification. E TESTDB-267 Scan segments '%s' and '%s' have common elements. E TESTDB-268 An existing scan link has the name '%s'. Scan segment specification is discarded. W TESTDB-269 Scan segment '%s' shares elements with chain '%s'. Cannot use segment to specify chains. W TESTDB-270 Scan segment '%s' overwrites an earlier specification that has a different scan style. W TESTDB-271 Your scan chain specification includes a sequence of %d scan links. All but the first is discarded. E TESTDB-272 Scan chain specification '%s' includes repeated elements when segments are expanded. W TESTDB-273 Net '%s' specified in trace_nets() statement does not exist in the design (line: %d). W TESTDB-274 Could not delete signal_type attribute on port '%s'. W TESTDB-275 Can not find scan chain '%s' to delete it. W TESTDB-276 Can not find scan segment '%s' to delete it. W TESTDB-277 Can not find scan link '%s' to delete it. W TESTDB-278 Can not find scan signal on port '%s' to delete it. I TESTDB-279 Using default scan style '%s'. E TESTDB-281 Unable to open '%s' for reading. E TESTDB-282 %s at or near token '%s' (Line: %d). E TESTDB-283 The '%s' port does not map to any package pin. E TESTDB-284 The '%s' port maps to %d package pins. E TESTDB-285 Multiple (%d) design ports map to the '%s' package pin. E TESTDB-286 No package command found in the pin map file. E TESTDB-287 The %s index of the '%s' bus in the pin map file is inconsistent\ with the bounds for the corresponding design bus. E TESTDB-288 The number of package pins specified (%d) does not match the width (%d) of the bus '%s'. W TESTDB-289 Overwriting the scan state of the design from '%s' to '%s'. W TESTDB-290 The client %s specified is not a valid dft client. I TESTDB-291 reverting value of environment variable '%s' to its default value.\ The default value is set to no client. I TESTGEN-1 reverting value of environment variable '%s' to its default value '%s'. W TESTGEN-2 '%s' is not a valid scan style. W TESTGEN-3 '%s' is not 'true' or 'false'. W TESTGEN-4 Cannot associate a '%s' signal with chain '%s'. I TESTGEN-5 reverting value of environment variable '%d' to its default value '%d'. W TESTGEN-6 '%s' does not include the substring '%%s'. W TESTGEN-7 Hookup sense value '%s' conflicts with the old value '%s'. E TESTSIM-10 The design could not be fully linked for fault simulation. E TESTSIM-11 Unable to map cell '%s' of type '%s' for TestSim. W TESTSIM-12 The cell '%s' will be treated as a black box during fault simulation. W TESTSIM-13 The technology library cell '%s' has been used in this design.\n\ \t Only its non-scan functionality will be simulated. W TESTSIM-14 The technology library cell '%s' has been used in this design.\n\ \t All instances of this cell will be treated as black boxes during fault simulation. E TESTSIM-15 Could not read the TestSim macro library, 'testsimmacro.db'. E TESTSIM-16 Could not read the TestSim library, '%s'. W TESTSIM-17 There are %d instances of black boxes in this design. E TESTSIM-20 The link_library is not defined. I TESTSIM-25 Cell '%s' in '%s' is not present in the library '%s'. E TESTSIM-30 Cannot write the intermediate file '%s'. E TESTSIM-31 Cannot read the intermediate file '%s'. E TESTSIM-32 The intermediate file '%s' has the wrong number of fields. W TESTSIM-40 Cannot close the intermediate file '%s'. E TESTSIM-50 Could not set up a symbolic link '%s' to the specified sif file '%s'. E TESTSIM-60 The FCOMP module used while creating the fault list failed. E TESTSIM-62 There are no unmasked untested faults to fault simulate. E TESTSIM-64 The PARTFLT module used while selecting a random sample of the fault list failed. E TESTSIM-65 The COLLAPSE module used while collapsing the fault list failed. E TESTSIM-66 Could not perform test assume/initial on pin '%s' of cell '%s', reference '%s' because of internal error. E TESTSIM-67 Could not map fault on cell '%s', reference '%s' because of internal error. E TESTSIM-70 The REPORTER module used in updating the master fault list failed. E TESTSIM-80 The VTRAN module used in translating the input vectors failed. E TESTSIM-90 The fault simulation module failed. I TESTSIM-95 Port '%s' of type '%s' will be %s to the value %d. W TESTSIM-96 Cannot find clock information for port '%s'. I TESTSIM-97 The pin '%s' will be frozen to the value %s during fault simulation because there is a test_assume attribute on it. I TESTSIM-98 The pin '%s' will be initially set to the value %s during fault simulation because there is a test_initial attribute on it. E TESTSIM-99 Can't set constant value 1/0 on pin %s because %s. E TESTSIM-100 Could not update the master fault list. I TESTSIM-110 A summary of the IDDQ strobes and coverage can be found in the '%s.iddq.rpt' file.\ \tA report on the vectors and circuit conditions that were invalid for IDDQ measurement can be found in the '%s.iddq.invalid' file.\ \tA list of the undetected IDDQ faults can be found in the '%s.iddq.undetected' file. E TESTSIM-130 Cannot write the testsim model to the file '%s'. E TESTSIM-131 Cannot read the testsim model file '%s'. E TESTSIM-132 The testsim model for the design '%s' is not present in the file '%s'. E TESTSIM-140 Port '%s' has a testsim_input_delay attribute. This will be\n\ ignored since this is not an input or bidirectional port. E TESTSIM-141 Port '%s' has a testsim_output_strobe attribute. This will be\n\ ignored since this is not an output or bidirectional port. E TESTSIM-142 The testsim_input_delay attribute %5.2f on port %s is more than the period %5.2f. Attribute ignored. E TESTSIM-143 The testsim_output_strobe attribute %5.2f on port %s is more than the period %5.2f. Attribute ignored. E TESTSIM-144 The testsim_input_delay attribute %5.2f on port %s is negative. Attribute ignored. E TESTSIM-145 The testsim_output_strobe %5.2f on port %s is negative. Attribute ignored. W TESTSIM-21009 Vector %d time %dns created %d conflict state%s. W TESTSIM-21010 Vector %d time %dns created %d floating net%s which drive%s logic gates. W TESTSIM-21104 Simulation did not stabilize within the maxdelta limit of %d\n\ \t during vector %d at time %u. W TESTSIM-21105 Simulation did not stabilize by the end of the clock cycle during\n\ \t vector %d at time %u. There are %d events still pending. W TESTSIM-21307 Vector %d time %dns bidirectional conflict at port %s. Input will be turned off and output not strobed. E TESTSIM-21601 Net number %d has an invalid fanout list.\n\ \tInvalid intermediate ckt file (or virtual TM 0/1 and TPO ckt).\n\ \tCheck your disk space availability. W TESTSIM-22005 The circuit contains floating element inputs. A floating input to a CMOS logic gate may cause both P and N transistors to be partially conducting. This may cause high IDDQ, and may invalidate IDDQ testing. W TESTSIM-22506 Vector %d time %dns actual state %s and expected state %s mismatch at port %s. Not strobed. W TESTSIM-22507 Vector %d time %dns actual state is unknown (%s) when expected state is known (%s) at port %s. E TESTSIM-22900 Cannot open output vector file %s. E TESTSIM-22901 Cannot open input vector file %s. E TESTSIM-22903 Pin %s in input vector file is not valid. E TESTSIM-22904 Pin %s with direction 'I' is not a primary input. E TESTSIM-22905 Pin %s with direction 'O' is not a primary output. W TESTSIM-22906 Strobe parameter not specified for output pin %s. It will be strobed at time 0. E TESTSIM-22907 Pin %s with direction 'B' is not a primary bidirectional pin. E TESTSIM-22908 Errors in the sif file %s. Cannot continue. E TESTSIM-22909 "Pin %s specified as a clock but it is not a primary input. E TESTSIM-22911 Unsafe element '%s' not found. E TESTSIM-22913 Errors in sif file. Cannot continue. E TESTSIM-22914 Scan cell '%s' not found. W TESTSIM-22915 Scan cell '%s' is a black box. The outputs of the cell will remain at 'X'. E TESTSIM-22916 Errors in sif file. Cannot continue. E TESTSIM-22918 Strobe parameter for output pin %s is greater than the PERIOD. E TESTSIM-22919 Strobe parameter for bidirectional pin %s is greater than the PERIOD. E TESTSIM-22920 Delay parameter for input pin %s is greater than the PERIOD. E TESTSIM-22921 Trailing edge parameter for clock\ pin %s is greater than the PERIOD. E TESTSIM-22926 Can't find pin %s that is to be held at\ constant 0. E TESTSIM-22927 Can't find pin %s that is to be held at\ constant 1. E TESTSIM-22995 Field '******' not recognized. Ignored. E TESTSIM-22997 Error in reading the input sif file. W TESTSIM-22998 Input port %s missing in the input vector file. \ Its value will stay at X. I TESTSIM-22999 Output port %s missing in the input vector file. Added to the output vector file. E TESTSIM-32351 Cannot successfully write to file %s. W TESTSIM-36029 Cannot map the fault %s to the testsim design. E TIM-001 There are no arcs from pin '%s' to pin '%s' on cell '%s'. I TIM-002 Timing loop detected.\ W TIM-003 Disabling timing arc between pins '%s' and '%s' on \ cell '%s'%s E TIM-004 The pin '%s' which is a derived clock pin is either \ in a loop or is in the fanout of two clock sources\ I TIM-005 Invalidating all auto-disabled timing arcs.\ E TIM-006 report_delay_calculation is not enabled for library '%s'. E TIM-007 The master clock %s has %d edges in a period. Cannot\n\ do frequency multiplication. E TIM-008 The generated clock '%s' is in the fanout of clock\n\ source %s. E TIM-009 Generated clock '%s' is not in the fanout of its \n\ master clock. W TIM-010 The generated clock '%s' has not been expanded,\n\ \tplease create its master clock. E TIM-011 The following generated clocks '%s' form a loop. E TIM-012 The master of the generated clock '%s' is not \n\ connected to any clock source. I TIM-013 Found %d generated clock master pins that are not \ connected to clock sources. I TIM-014 Found %d loops in the generated clock network. E TIM-015 The -edges spec of generated clock '%s' has edge number\n\ \tless than 1, the edge number should be from 1 up. E TIM-016 In the -edge specification of create_generated_clock\n\ \t'%s', the edge numbers must be in increasing order. E TIM-98 Minimum version must be a different library. E TIM-100 Unable to obtain a DesignTime or technology license. E TIM-101 The '%s' command is not supported in dt_shell. E TIM-102 Either DesignTime license or Ultra license is required for true path reporting. W TIM-103 Reference %s contains internal pins with clock attribute. W TIM-104 Worst timing paths might not be returned. I TIM-105 Converting time units for library '%s' since those in library '%s' differ. I TIM-106 Converting capacitance units for library '%s' since those in library '%s' differ. W TIM-107 Main library '%s' has no time units specified, but library '%s' does. W TIM-108 Main library '%s' has no capacitance units specified, but library '%s' does. W TIM-109 Cell '%s' cannot be optimized because it has \ conflicting timing exceptions on pins '%s' and '%s'. W TIM-110 Cell '%s' is being dont_touch'ed because of \ timing constraints on pin '%s'. W TIM-111 clock port '%s' cannot be assigned input delay relative \ to clock '%s'. Ignoring the value. I TIM-112 Input delay ('%s') on clock port '%s' will be added to the \ clock's propagated skew. I TIM-113 set_input_delay values are added to the\ propagated clock skew. W TIM-114 Cell '%s' is being set to size only because of \ timing constraints on cell or on pins of the cell. W TIM-115 Cell '%s' is being set to size only because \ it is used to break up a timing loop. W TIM-116 Cell '%s' is being set to size only because \ it has disabled timing arcs. E TIM-120 Cannot find library file named '%s'. E TPM-10 Test program '%s' does not match the design '%s'.\n\ \tTest program was not restored. E TPM-20 '%s' is not a valid name for the test program\n\ \tbecause it matches the name of one of the test programs\n\ \tin the current sequence. E TPM-30 '%s' %s. It cannot be restored. W TPM-31 File '%s' contains only fault information but no vectors. W TPM-40 Deleting current test program '%s' because it is not consistent with the current design. W TPM-41 Deleting current test program '%s' because it was generated\n\ \t for the design '%s' but the current design is '%s'. E TPM-50 Current design is '%s', but trying to restore a test program for design '%s'. I TPM-60 This %s run is an incremental run. It will target\n\ \t the faults left undetected by the preceding test program. E TPM-70 The dont_fault attribute '%s' on library cell '%s' is invalid.\n\ It will be ignored. Valid values (case-sensitive) are "sa0", "sa1", "sa01". E TPM-71 The dont_fault attribute '%s' on pin '%s' of library cell '%s' is invalid.\n\ It will be ignored. Valid values (case-sensitive) are "sa0", "sa1", "sa01". W TRANS-1 Cell '%s' (%s) not translated. W TRANS-2 Flip-flop '%s' (%s) cannot be translated exactly into '%s'. W TRANS-3 Flip-flop '%s' (%s) cannot be translated to requested type. W TRANS-4 Target library contains no replacement for register '%s' (%s). W TRANS-5 Unable to determine wired-logic type for multiple-driver net '%s'. I TRANS-6 Assuming multiple-driver net '%s' is a %s. W TRANS-7 Net '%s' is not a legal wired_logic net. However, it\n\ will not be replaced because this is an in-place optimization. W TRANS-8 Combinational cell '%s' (%s) cannot be translated exactly into '%s'. W TRANS-9 Cell '%s' (%s) cannot be exactly translated 1 for 1 into target library. Ignoring set_compile_directives. W TRANS-10 Cell '%s' (%s) has use_for_size_only attribute and cannot be translated 1 for 1 into target library . I TRANS-100 Translate terminated abnormally. E UI-1 Variable '%s' is undefined. E UI-2 No manual entry for '%s'. E UI-3 Number of commands to display must be an integer. E UI-4 Invalid alias list. W UI-5 Alias '%s' is not defined. E UI-6 Variable group '%s' is undefined. E UI-7 Could not change directory to '%s'. E UI-8 Cannot issue the 'ls' command. E UI-9 Cannot issue the '%s' command. E UI-10 '%s' not a valid type. E UI-11 Line %d: argument '%s' of command '%s' is the wrong type. E UI-12 Synopsys software was incorrectly installed. W UI-13 The variable '%s' must be defined before Design Compiler \ can be run. E UI-14 Argument '%s' of command '%s' is the wrong type. E UI-15 '%s' is expecting a %s, not a %s. E UI-16 Line %d: missing arguments to command '%s'. E UI-17 Missing arguments to command '%s'. W UI-18 Expecting '%s'. E UI-19 The name of a file to include was not specified. E UI-20 Include file '%s' could not be opened. E UI-21 Execution of include file '%s' was terminated because \ an error was generated. E UI-22 Log file '%s' could not be opened. E UI-23 Log file '%s' was not completely written due to an error. E UI-24 Aliases may contain only letters, digits or underscores. E UI-25 The 'alias' and 'unalias' commands may not be aliased. E UI-26 Log file '%s' can't be included. E UI-27 You need write permissions on the current or home directory to read an HDL file. E UI-30 Unrecognized feature name '%s'. I UI-31 You already have a '%s' license. E UI-32 You don't have a '%s' license to remove. E UI-33 List function '-%s' is not available. E UI-34 Invalid feature list. E UI-35 Bad value '%s' specified for compatibility_version. I UI-36 Acceptable values must look like 'v1.3', 'v2.0' (up to 'v3.5'),\n\t or '1997.01'... E UI-37 Value '%s' is greater than the current product_version. I UI-38 Value must be less than or equal to '%s'. E UI-39 Variable '%s' cannot be set; it is read-only. E UI-40 Cannot read include file '%s'; it's a directory. E UI-41 Previous error has stopped execution of %s. E UI-42 Can't find the %s '%s' in memory. E UI-43 No %s were specified to be deleted. E UI-44 You can't specify both a %s list and -all. E UI-45 No %s were specified to be reported on. E UI-46 Can't remove system variable '%s'. E UI-47 Value required for the '' argument. E UI-48 Unexpected arguments. E UI-49 Bad variable name specified. E UI-50 The '%s' command may not be aliased. E UI-51 License '%s' is required by design '%s'.\n\tYou must remove the design before you can remove the license. E UI-52 Design '%s' is a limited design and cannot be written out. E UI-53 Design '%s' has not been mapped yet\n\tand you can only write it out in db format. W UI-56 Illegal setting '%s' for the 'hdl_preferred_license' variable. W UI-57 The perferred license '%s' \ is already checked out, it will try to get other equivalent sets of licenses. I UI-58 Created bus '%s': \n\tStart index '%d' is connected to '%s'.\n\tEnd index '%d' is connected to '%s'. E UI-60 '%s' is an invalid value for the list variable '%s'. The variable value has not been changed. E UI-61 Cannot create temporary files in current working directory '%s'. I UI-62 You do not have %s permission on this directory. E UIAT-1 Cannot specify %s for '%s' type. E UIAT-2 Min of range (%s) cannot be greater than max (%s). W UIAT-3 Attribute class '%s' has not been defined. W UIAT-4 Attribute '%s' is already defined in class '%s' W UIAT-5 Cannot get attribute for more than one object. W UIAT-6 Cannot define attributes for %ss. W UIAT-7 Cannot import user attributes for %ss. W UIAT-8 Attribute '%s' is already defined as %s for another class. E UIBS-1 No valid objects specified. E UIBS-2 Objects must be either all ports or all nets. E UIBS-3 Only ports of the same direction can be grouped. E UIBS-4 Only port or net objects can be grouped. E UIBS-5 Bus name '%s' conflicts with existing names. E UIBS-6 All objects must be from the same design. E UIBS-7 Type name '%s' conflicts with existing type. E UIBS-8 No valid busses specified. E UIBS-9 '%s' isn't a bus. E UIBS-10 At least one of the port objects specified is already a member of a bus. E UIBS-11 Cannot use sort and no_sort options in the same command. E UIBS-12 Cell '%s' already belongs to a multibit component. E UIBS-13 Multibit component '%s' already exists. W UIBS-14 Set of cells specified have differing functionality. W UIBS-15 Duplicates in list of cells to create_multibit with no_sort option. E UIBS-16 The '%s' command was not executed because design '%s' could not be linked. E UIC-1 Cannot execute this command. E UIC-2 The design '%s' has no clusters. E UIC-3 The file '%s' cannot be opened for writing. I UIC-4 No new cells were written to the file '%s'. W UIC-5 You need a DC-Expert license to compile or create wire loads using clusters. W UIC-6 The leaf cell '%s' cannot be annotated with clusters. W UIC-7 The clusters associated with cell '%s' are not \n\ compatible with those associated with the current_design. W UIC-8 Writing LOC attribute to a PDEF 1.x file. W UIC-9 Can not find the reference design for cell '%s'. E UID-1 Link command is not available. E UID-2 There are no designs to be linked. W UID-3 Can't read link_library file '%s'. E UID-4 Current design is not defined. E UID-5 Current design '%s' has no schematic. E UID-6 Technology library has not been specified. E UID-7 Couldn't read technology library '%s'. E UID-8 Technology library '%s' is not a library. E UID-9 Can't read '%s' files '%s'. E UID-13 '%s' doesn't specify a unique design\n\ \tPlease use complete specification: full_file_name:design_name E UID-14 Design '%s' is not in the system. E UID-15 '%s' doesn't specify a unique library\n\ \tPlease use complete specification: full_file_name:library_name W UID-16 No input ports on design '%s'. W UID-17 No output ports on design '%s'. E UID-18 Invalid pin list. E UID-19 '%s' doesn't specify a unique instance\n E UID-20 Write command is not available. E UID-21 Invalid file or design list. E UID-22 No files or designs were specified. E UID-23 Only designs can be specified with \"-hierarchy\" \n\ File '%s' is ignored. E UID-24 No valid designs or design files were specified. E UID-25 Write command failed. W UID-26 Can't find in memory specified design or design file '%s'. E UID-27 '%s' doesn't specify a unique design file\n\ \tPlease use complete path name to specify this file. E UID-28 Can't write design '%s', to '%s'. E UID-29 Can't write file '%s'. E UID-30 Couldn't write specified designs to '%s'. E UID-31 Multiple designs per file are not permitted by '%s' format. E UID-32 Format '%s' is not a valid write format. E UID-33 LSI Netlist format is not enabled. E UID-34 TDL Netlist format is not enabled. E UID-36 Verilog netlist format is not enabled. E UID-37 Mentor format is not enabled. E UID-38 EDIF format is not enabled. E UID-39 Design '%s' isn't mapped. E UID-40 Wire load '%s' not found. E UID-41 No files are specified. E UID-42 Invalid file list. W UID-43 File '%s' was not found in the search_path. E UID-44 Either -all or cell_list must be specified. E UID-45 Invalid cell list. E UID-46 No valid cells are specified for ungrouping. W UID-47 Can't %s unmapped logic cell '%s'. W UID-48 Can't %s logic one cell '%s'. W UID-49 Can't %s logic zero cell '%s'. W UID-50 Can't %s cell '%s'; its reference is unresolved. W UID-51 Can't %s leaf cell '%s'. E UID-56 Read format '%s' is not supported. E UID-57 No design file specified to read. E UID-58 Cannot read file '%s'. E UID-59 Can't read '%s' file '%s'. E UID-60 Verilog HDL Compiler is not enabled. E UID-61 Invalid list of operating conditions. E UID-62 No operating conditions were found. W UID-63 Operating conditions '%s' not found. E UID-64 Only one of: cell list, -pla, -logic, -fsm, -hdl_all_blocks \ \n\tor -hdl_bussed can be specified. -hdl_block can only be used separately \ \n\tor with -hdl_all_blocks or -hdl_bussed. E UID-65 Either cell list or -pla or -logic must be specified. E UID-66 No valid cells are specified for grouping. E UID-67 A design with name '%s' already exists in the same\n\ \tdesign file as the given design: '%s'. E UID-68 A cell %s already exists in design '%s'. E UID-69 Except set option cannot be used with -hdl_block, \n-hdl_all, or -hdl_bussed option. E UID-70 Can't find HDL block %s. W UID-71 No designs or libraries are available to free. E UID-72 Only one type of object allowed. E UID-73 Invalid %s list. E UID-74 No valid %ss specified. E UID-75 Unknown port '%s'. W UID-79 Timing options specified without -timing. E UID-80 Illegal -path option of '%s'. E UID-81 Illegal -delay option of '%s'. E UID-82 -max_paths cannot be negative. I UID-83 Initializing incremental mode... W UID-84 Hierarchy options specified without -hierarchy. I UID-85 Updating design information... E UID-86 Could not update the design. E UID-87 Cannot read this library, it is old. E UID-88 Invalid port list. E UID-89 'set_unconnected' cannot be set on an input port '%s'. E UID-90 'set_unconnected' cannot be set on an unknown port '%s'. E UID-91 '%s' cannot be set on an output port '%s'. E UID-92 '%s' cannot be set on an unknown port '%s'. E UID-93 Invalid object list. E UID-94 '%s' is not a valid attribute type. W UID-95 Can't find %s '%s' in design '%s'. I UID-96 Creating new attribute '%s' on %s '%s'. E UID-97 '%s' doesn't have an attribute '%s' type '%s'. E UID-98 Invalid attribute type. E UID-99 Attribute '%s' on %s '%s' is type boolean;\n\ \tcannot be set to '%s'. W UID-100 '%s' is not a valid object type. W UID-101 Attribute '%s' does not exist on %s '%s'. W UID-102 Ignoring %s '%s' type. F UID-103 Synopsys database corrupted. E UID-104 Design '%s' not found in target library. E UID-105 Example design '%s' is not a flip-flop. E UID-106 Cannot determine flip-flop type of design '%s'. W UID-107 Multiple operating conditions specified;\n\ \tonly '%s' accepted. E UID-108 Can't find timing range '%s'. E UID-109 Can't find %s '%s'. E UID-110 VHDL HDL Compiler is not enabled. E UID-111 Can't check security for format '%s'. E UID-112 '%s' is an invalid %s. E UID-113 No report section specified. W UID-114 %s exists on port '%s'. Cannot %s. W UID-115 '%s' is not a library cell. W UID-117 Can't find %s '%s' in library '%s'. E UID-118 Port '%s' is in design '%s', but port '%s' is in design '%s'. W UID-119 %s '%s' is of the wrong type. E UID-120 The clock period value can't be negative. E UID-121 Invalid timing range list; specify one or two timing range names. E UID-122 The '-exact' option must be used when the example design is a latch. E UID-123 Can't set flip-flop type on non sequential cell '%s'. E UID-124 Design '%s' is of "unknown" flip-flop type. E UID-125 Attribute '%s' can't be %s on this %s with this command. W UID-126 Design '%s' is in state table format. Writing only port information. E UID-127 Can't find library pin '%s'. E UID-128 No drive specified on library pin '%s'. E UID-129 Either wire load model or mode has to be specified. E UID-130 Mode '%s' is not a legal mode. E UID-131 Can't find the specified library '%s' in memory. E UID-132 The write command cannot be used: \n\ \t\t-- with the "-format %s" option \n\ %s\t\t-- and with a design_file_list of more than one file. \n\ \tUse the "-hierarchy" option. E UID-133 Attribute flag value must be either true or false. E UID-134 Clock '%s' is undefined for design '%s'. E UID-135 No clock specified for remove_clock(). E UID-136 Non-boolean type in expression. E UID-137 Error in expression. '%c' must be followed by an attribute name. W UID-138 Attribute '%s' does not exist for %s '%s'. E UID-139 Invalid inferred bus naming style specification. E UID-140 You cannot set the '%s' variable. E UID-141 Can not set -min_block_size if mode is not "enclosed". W UID-142 Could not convert '%s' into a piece_index for library\n\ \tpin '%s. Using '%s' for index value instead. E UID-143 Cannot set a wire_load mode on a port.\n\ \tOnly a wire_load model can be set on a port. E UID-144 %s not allowed in object_list. I UID-145 Truncating parameter value '%f' to '%d'. E UID-146 Invalid combination of options enabled. E UID-147 Can not set a wire_load on a port\n\ and a cluster at the same time. E UID-148 Cannot set a wire_load mode on a cluster. E UID-149 The design '%s' does not have a cluster named '%s'. W UID-150 Duplicate signals ignored. E UID-151 Undeclared optional signals. E UID-152 You cannot set a selection group on a port.\n\ \tOnly a wire_load model can be set on a port. E UID-153 You cannot set a selection group if the mode is not "enclosed". E UID-154 Specified selection group '%s' not found. E UID-157 '-to' option must be specified for bidirectional \ pin. W UID-159 Predefined methodology selected, other options ignored. E UID-160 Pin %s is not a scan-out pin. E UID-161 Cell %s does not have a scan-out pin. E UID-162 Duplicate cell entries found in test routing order. E UID-163 Unrecognized test methodology %s. E UID-164 Test report options selected without -test. W UID-165 Unknown test fault class, all classes will be displayed. E UID-166 Fault report options selected without -fault. E UID-167 Scan-chain index must be positive. E UID-168 Non-sequential cell/reference %s can not be in a scan-chain. E UID-169 Non-sequential cell/reference/design %s can not be made scannable. W UID-170 '%s' cannot be interpreted as a list of local link library files. W UID-171 Design '%s' contains parameterized ECL components.\n\ Writing this design to the '%s' netlist format will\n\ cause a loss of parameterized information. I UID-172 Writing synthetic library implementations for design '%s'.\n\ \tUse "write -no_implicit" to get just the design. W UID-173 Can't %s an uncompiled synthetic cell '%s'. E UID-174 Syntax error in line '%s'. W UID-175 Warning: Design '%s' contains unmapped components.\n\ \tThe description may not simulate or be read back into Design Compiler. E UID-177 File '%s' is a directory name. E UID-178 The '%s' attribute of a %s cannot be set with this command. E UID-179 %s format is not enabled. W UID-181 Can't write sequential_type for %s '%s'.\n\ \tCannot find example design in target_library. E UID-183 Unrecognized scan style '%s'. E UID-184 Minimum fault coverage must be at least 80 percent. E UID-185 Minimum fault coverage cannot exceed 100 percent. E UID-190 The -design_name and -cell_name options are not used with the \n -hdl_all_blocks or -hdl_bussed options. E UID-191 The -design_name option is required unless you are using the \n -hdl_all_blocks, -hdl_bussed, or -hdl_block options. W UID-200 Signal index values can not be negative. E UID-202 Design contains only combinational cells but \ scan style is not set to "combinational"; test patterns cannot be \ saved. E UID-210 Proprietary design '%s' can't become the current design. W UID-211 Can't write proprietary design '%s'. E UID-220 Unrecognized test assert value '%s', (use one of "0","1"). E UID-221 Can't set assume value as direction of pin %s not out/inout. E UID-222 Can't set assume value as pin %s from a combinational cell. E UID-223 Can't set assume value on pin %s as not test isolated. E UID-224 Can't set hold value as port %s is not an input. E UID-225 Can't set require value as direction of pin %s not in/out. E UID-226 Can't set require value as pin %s is test isolated. E UID-227 Can't set require value as pin %s from an unknown cell. W UID-228 Design has no hierarchy. No cells can be ungrouped. W UID-229 All hierarchical cells are don't touched. No cells can be ungrouped. W UID-230 All specified hierarchical cells are don't touched. No cells can be ungrouped. W UID-231 All designs specified are un-changed and not written. I UID-232 Updating design information for flat timing report... W UID-233 Can't resolve reference '%s' for cell '%s' E UID-234 Invalid port direction '%s'. E UID-235 Port '%s' already exists. E UID-236 Cannot specify port_list with -unused. E UID-237 Unable to remove port '%s'. E UID-238 The '-associated_clock' switch can only be used with 'clocked_on_also' signal type. E UID-240 Either the '-flip_flop' or the '-latch' argument must be used. E UID-241 Unable to find example %s '%s'. E UID-242 Example design '%s' is not a %s. E UID-243 The %s design '%s' is of "unknown" sequential type. E UID-244 Cell '%s' is a latch. \n The latch type was NOT specified on the command line. E UID-245 Cell '%s' is a flip-flop. \n The flip-flop type was NOT specified on the command line. E UID-246 Cell '%s' is neither a latch nor a flip flop. E UID-247 Non-sequential cell/reference/design %s can not be made transparent. E UID-248 The %s design '%s' is of "unknown" combinational type. E UID-249 Cell '%s' is not a combinational gate. E UID-250 Cannot find %s '%s'. E UID-251 Cannot specify both %s and %s. E UID-252 '%s' is not an instance of design '%s'. E UID-253 Cannot specify %s without %s. E UID-254 Invalid delay direction for port '%s'. E UID-255 Value for %s cannot be negative. E UID-256 Either %s or %s must be specified. E UID-257 Invalid waveform. Edges must be an even number of monotonically\n increasing values less than one period in duration. E UID-258 Group weight must be between 0.0 and 100.0. E UID-259 Must specify one of %s, %s, or %s. E UID-260 The '%s' command is obsolete. It is ignored. E UID-261 Cannot set current instance to object '%s'. E UID-262 '%s' doesn't specify a unique object. E UID-263 Cannot specify multiple objects for command %s. E UID-264 Cannot specify multiple objects. E UID-265 Cannot specify library object '%s' for command %s. E UID-266 Cannot specify library object '%s'. E UID-267 Command %s cannot be performed on instance %s within a hierarchy.\n\ Please re-issue the command in the design referenced by the current instance. E UID-268 Cannot perform this command on instance %s within a hierarchy.\n\ Please re-issue the command in the design referenced by the current instance. E UID-269 Can't find design corresponding to instance '%s'. E UID-270 Can't write script file '%s'. E UID-271 Current instance is not defined. E UID-272 Cannot set current design to library design '%s'. E UID-273 Command '%s' cannot be performed within a hierarchy.\n\ Please re-issue the command in the design referenced by the current\n\ instance or the top-level of the current design. E UID-274 This command cannot be performed within a hierarchy. Please re-issue it\n\ in the design referenced by the current instance or the top-level of\n\ the current design. W UID-275 No %s to list. E UID-276 Can't set current instance to leaf cell '%s'. W UID-277 No library contain the wire load model '%s' set on design '%s'. E UID-278 No annotated timing check information was removed. E UID-279 Cannot have current_instance set for this command. E UID-280 Period value conflicts with waveform on clock '%s'. W UID-281 Path group '%s' has no paths; it will not affect optimization. I UID-282 Annotated '%s' delays are assumed to include load delay. E UID-283 Load delay location '%s' should be 'cell' or 'net'. W UID-285 '%f' value is negative. E UID-290 Can't set test assertion on hierarchical object %s. E UID-300 Cannot use hdl options with the soft option. E UID-301 'get_attribute' can't get value for unknown attribute type. W UID-302 Invalid value for link_force_case variable: default value check_reference will be used. E UID-303 Cannot set initial value on pin %s from a non-scan cell. E UID-304 Cannot set initial value on pin %s from an unknown cell. E UID-305 Period value unspecified. E UID-306 Waveform set unspecified. E UID-307 Waveform set must consist of two floating point values. E UID-308 Period value cannot be zero. E UID-309 Value for period is different from the default value specified by test_default_period/custom test protocol. E UID-310 Port '%s' is not an input port. E UID-311 Cannot set testsim_input_delay on port '%s'.\n\ It is not an input or bidirectional port. Command ignored. E UID-312 Cannot set testsim_output_strobe on port '%s'.\n\ It is not an output or bidirectional port. Command ignored. E UID-313 The specified input delay %5.2f is more than the period %5.2f. Command ignored. E UID-314 The specified output strobe %5.2f is more than the period %5.2f. Command ignored. E UID-315 The specified input delay %5.2f is negative. Command ignored. E UID-316 The specified output strobe %5.2f is negative. Command ignored. E UID-326 Can't find pin '%s' on cell '%s'. E UID-327 There are no arcs from pin '%s' to pin '%s' on cell '%s'. E UID-330 '%s' in command get_design_parameter is not a \ valid parameter name for the current design. Valid parameter names \ are '%s'. E UID-331 Parameter '%s' does not have a value. E UID-332 The -library option is only valid with the db format. E UID-333 The -out flag cannot be used with the -library flag. E UID-334 Tried to write the root object '%s' into a design library. W UID-335 \ The assignment operator "=" appears in the filter string. E UID-336 You cannot perform the command '%s' on design '%s'\n\ \tbecause it is a limited design. E UID-337 You cannot perform the command '%s' on design '%s'\n\ \tbecause it contains the limited design '%s'. E UID-338 Cannot access design parameters on object '%s'.\n\ \tDesign parameter values are only valid on designs and references. W UID-339 Can't remove attribute '%s' from object '%s'. E UID-340 The connection class attribute \ can be set only on design ports. W UID-341 Design '%s' has '%d' unresolved references. For more detailed information, use the "link" command. E UID-342 The cell '%s' is not a synthetic library module, \ so set_implementation was not applied to it. E UID-343 Invalid read_timing context. Valid contexts are vhdl, verilog. W UID-344 Can't %s synthetic operator '%s'. E UID-345 The value for the 'max_levels' argument should be\n\ \tbetween 1 and %d for design '%s'. W UID-346 The -max_levels argument is ignored when -hierarchy\n\ \toption is not given. W UID-347 Can't link reference '%s' to design '%s'. W UID-348 Creating virtual clock named '%s' with no sources. W UID-349 Could not read any link_library files. The link_library setting %s may be invalid. W UID-350 Could not infer bus %s for design %s, because its index range does not match its width. W UID-351 The variable '%s' is \n\ \tobsolete. Use %s. E UID-352 At least one argument must be specified with this command. E UID-353 Arguments '%s' and '%s' are mutually exclusive. E UID-354 '%s' is a bad option. Please specify '%s'. E UID-360 Options -transparent and -user only valid when setting scan FALSE. E UID-361 Options -transparent and -user can not both be specified. E UID-362 Option -transparent can not be specified with non-latch cell/design %s. W UID-363 Port information will be listed for the design of the current\n\tinstance. This information is not used for analysis or optimization\n\tunless current_design is set to '%s'. E UID-364 The current_instance is not a unique instantiation \n\t of design %s. Please rerun command %s after running uniquify. E UID-365 Cell %s is not owned by the current_instance. \n\tOnly cells in the current_instance can be specified. E UID-366 Cell %s is not owned by the current_design. \n\tOnly cells in the current_design can be specified. E UID-367 Design %s is not referenced by any cell in current_design. \n\tOnly designs referenced in current_design can be specified. E UID-368 \n\tOnly one design can be specified for top-down copying of attributes. W UID-369 \n\t The -all option to the link command is now obsolete.\n\t Please add "*" at the head of your link_library variable to get this functionality. E UID-370 The design '%s' has clusters and cannot be modified by\n\ the 'group' command. E UID-371 The '.' implementation can only be used with mapped synthetic modules. W UID-372 \n\t No cells found to copy attributes from. E UID-373 \n\t The specified range is different from the number of specified objects. E UID-374 \n\t No cells in design '%s' reference any of the specified designs. E UID-375 Cannot use '%s' clock skew option on object '%s' \nbecause the '%s' attribute is already set on that object. W UID-376 It is dangerous to create a clock source on inout port '%s'. E UID-377 Clock '%s' is not ideal. Cannot set clock transition. E UID-378 '%s' is not a valid format. E UID-380 Invalid minimum porosity constraint, must be between 0 and 90. E UID-381 You are not licensed to run routability optimization. W UID-382 Setting a minimum porosity constraint to less than the default %g in link libraries. E UID-383 The porosity constraint value is less than the default %g in target libraries. E UID-384 \n\t Invalid value specified for bus_naming_style : '%s'. E UID-385 \n\t Invalid value specified for bus_range_separator_style : '%s'. W UID-386 The variable '%s' is now\n\ \tobsolete. The following, equivalent variable is being set:\n\ \t\t%s = "%s"\t W UID-387 The variable '%s' is now\n\ \tobsolete. The following, equivalent variables are being set:\n\ \t\t%s = "%s", and,\n\ \t\t%s = "%s"\t E UID-388 Attribute '%s' does not exist on %s '%s'. W UID-389 Current operating conditions specify best_case_tree\n\ \tas the interconnect model. Annotated resistance will be ignored in\n\ \tthis case. W UID-390 All data in the names file '%s' is invalid. E UID-391 The 'create_clock' command cannot be used on output port '%s'. E UID-392 The object '%s' is a hierarchical object. You cannot set an\n\ IDDQ-invalid condition on a hierarchical object. E UID-393 No valid nodes specified for the set_iddq_invalid_state command. E UID-394 Error in command input : set_iddq_invalid_state command ignored. W UID-395 Could not link design '%s'.\n\ \tTherefore, the results of the filter command may be incorrect. E UID-396 The cell '%s' does not reference a synthetic library operator DW03_mult_n_stage, so set_pipeline_stages was not applied to it. E UID-397 You must chose one of {fixed min auto}. W UID-398 Pin '%s' does not belong to a cell in design '%s'. E UID-400 Design is already scan inserted, scan replaced or test ready. W UID-401 Design rule attributes from the driving cell will be\n\ \tset on the port. W UID-402 Specifying an input delay without an associated clock\n\ \tcan cause the port's timing to be analyzed incorrectly. E UID-403 Can't read in the DB file '%s'.\n\tFile '%s' is created using program version '%s'\n\twhich is newer than '%s'. E UID-404 No setup or hold margin was specified. E UID-410 Unable to find replacement gate '%s'. E UID-411 Replacement design '%s' is not a combinational gate. W UID-412 Overriding compile directives for cell %s. W UID-413 Overriding previous replacement cell for cell %s. E UID-414 Cannot set_compile_directives on cell %s because it already has set_combinational_type E UID-415 Cell list contains generic cell %s. W UID-416 The compile directive given by option %s had \ already been %s on all specified cells. E UID-417 Cell list contains synthetic operator cell %s. E UID-418 Cell list contains cell %s which is \ control logic of SELECT_OPs. E UID-420 %s cannot be used on port with clock specified. E UID-421 bc_dont_ungroup cannot be applied after the current design is \ scheduled.\ E UID-430 No object was specified for the \fBset_clock_uncertainty\fP comand. E UID-431 \fB-to\fP is missing. E UID-432 \fB-from\fP is missing. E UID-433 Too many objects for inter clock uncertainty. E UID-434 '%s' is not a name of a clock. E UID-435 Cannot set clock source latency on '%s' .This attribute can be set on a clock or a clock source pin. E UID-436 '-rise' and '-fall' options are valid only for inter-clock uncertainty W UID-437 '%s' option is obsoleted. Although it will still function normally now, please use '%s' command to replace this option in the future. W UID-438 Attribute '%s' is removed from from object '%s'. W UID-439 '%s' command is obsoleted. Although it will still function normally now, please use '%s' command to replace this command in the future. E UID-440 Can't write constraints file '%s'. E UID-444 '%s' is a PrimeTime option that is not supported by Design Compiler. W UID-445 Ignoring %s objects in collection '%s' because they are not of type %s. E UID-446 For pattern '%s', %s. W UID-447 Design has back annotation information, and the -load_annotation option \ was not used while entering incremental mode. I UID-448 Deleting the back-annotation information from Synopsys database. W UID-449 Even though without -connections, the command will\ still function, please use -connections option for a well defined semantics. W UID-450 Value for %s is negative. W UID-451 '%s' option is ignored when '%s' argument is present. E UID-455 The value %s is not a legal option for the\n\ \tset_transform_for_retiming command. E UID-456 The value %s is not a legal option for the\n\ \tset_state_for_retiming command. E UID-457 Cannot set size_only on cell '%s'. W UID-458 Cannot perform '%s' on object '%s' because it is not a port. W UID-459 Cannot perform '%s' on object '%s' because it is not a port. E UID-460 The command 'begin_incr_mode' is only available in dc_shell-t. E UID-461 Command 'begin_incr_mode' requires current_design to be set. E UID-462 Invalid implementation '%s' for cell '%s'. E UID-463 %s name is required to set implementation on operator '%s'. E UID-464 Invalid module '%s' or implementation '%s' for cell '%s'. E UID-485 Cannot specify %s without -source. E UID-900 The -type argument must provide at least one cell. E UID-901 The %s cell already has the set_register_type attribute set. E UID-902 The cell '%s' issued as an argument \ to set_scan_register_type -type is a non-scan cell. The -type switch requires \ a scan cell as an argument. E UID-903 The %s cell is not valid for methodology specified. E UID-904 Unable to find example %s '%s'. E UID-905 The %s design '%s' is of "unknown" sequential type. E UID-906 There are no valid cells specified\ on which to assert set_scan_register_type. W UID-907 Cell '%s' is not a sequential cell. W UID-908 Cell '%s' has the dont touch attribute set\ on it; cannot scan-replace. E UID-991 The driving cell %s has multiple inputs, and \ -from_pin is required when -input_transition_rise or -input_transition_fall is specified. W UID-992 Cannot find the top design for object %s. E UID-993 Cannot find the specified driving cell in memory. E UID-994 Cannot specify -connections with fanout number together. Please use -connections option for specifying the external fanout number. E UIDBG-1 The attach '%s' does not exist. E UIDBG-2 The object '%s' is not attached via the '%s' attach. E UIDBG-3 More than one object is attached via the '%s' attach. E UIDBG-4 No objects are attached via the '%s' attach. E UIDBG-5 It's illegal to specify both a library and a design. E UIDBG-6 You must specify either a library or a design. E UIDBG-7 You must invoke 'db_debug_start' before issuing this command. E UIDPCM-1 '%s' is not a valid calc_mode. E UIDPCM-2 One or more rail voltage names or values are invalid in library '%s' I UIDPCM-3 Library '%s' does not contain rail voltage information. W UIDPCM-4 '%s' is not a valid level.Setting level to default level, performance. The valid levels are accurate and performance. W UIDPCM-5 '%s' is not a valid mode.Setting level to default mode,global. The valid modes are global and instance. E UIDPCM-6 DPCM Library '%s' not loaded. E UIDPCM-7 '%s' is not a valid process factor. E UIDPCM-8 '%s' is not a valid voltage. E UIDPCM-9 '%s' is not a valid tree_type. W UIDPCM-10 Invalid value '%s' for dpcm_slewlimit. The valid values are either FALSE or TRUE.Setting default value as FALSE. W UIDPCM-11 Invalid value '%d' for dpcm_debuglevel. The valid values are greater than or equal to zero.Setting default value as '0'. W UIDPCM-12 DPCM operating condition '%s' not found. E UIDPCM-13 The command requires the -temp option when the -default or -current \ options are not used. E UIDPCM-14 The command requires a rail voltage list when the options -default \ or -current are not used. W UIDPCM-15 Invalid value '%s' for dpcm_arc_sense_mapping. The valid values are either FALSE or TRUE.Setting default value as FALSE. E UIED-1 Bad file '%s' specified. E UIED-2 Design '%s' already exists in file '%s'. E UIED-3 Bad value specified for the -logic option. E UIED-4 Must specify either reference name or -logic option. E UIED-5 Cell '%s' already exists in design '%s'. E UIED-6 Can't find reference design or library cell '%s'. E UIED-7 Reference '%s' is not unique. E UIED-8 Design '%s' can't refer to itself.\n\ \tThis would cause recursive hierarchy. E UIED-9 Can't reference design '%s' in design '%s'.\n\ \tThis would cause recursive hierarchy. E UIED-10 A reference named '%s' already exists in design '%s'. E UIED-11 Must specify either cell list or -all option. E UIED-12 Cell '%s' is not contained in design '%s'. E UIED-13 Net '%s' already exists in design '%s'. E UIED-14 Must specify either net list or -all option. E UIED-15 Can't remove net '%s'; it's part of a buss net. E UIED-16 Net '%s' is not contained in design '%s'. E UIED-17 Must specify only one net to connect. E UIED-18 The first argument '%s' is not a net. E UIED-19 Object '%s' is not a pin or port. E UIED-20 Object '%s' is not contained in design '%s'. E UIED-21 Object '%s' is already connected to net '%s'. E UIED-22 Must specify either object list or -all option. E UIED-23 Must specify only one net to disconnect. E UIED-24 Object '%s' is not connected to net '%s'. E UIED-25 Object '%s' is the wrong type.\n\ \tOnly nets, ports and pins are accepted. W UIED-26 Net '%s' is not connected to any objects. E UIED-27 Port '%s' already exists in design '%s'. E UIED-28 Can't remove port '%s'; it's part of a bus. E UIED-29 Port '%s' is not contained in design '%s'. E UIED-30 Must specify either port list or -all option. W UIED-31 The -logic option is ignored when explicit reference\n\ \tis given. E UIED-32 Can't %s for instance '%s' because design '%s'\n\ \tis instantiated %d times. E UIED-33 Can't %s for instance '%s' which is a leaf cell. E UIED-34 Conflicting options '%s' and '%s' for size_cell. E UIED-35 Local sizing was called with %d cells, which is more than the limit of %d. I UIL-0 Note that the ".synopsys_lc.setup" init file of\n\ \tlc_shell is a subset of the dc_shell ".synopsys_dc.setup" init file.\n\ \tIf a command other than an lc_shell command is encountered in the init file,\n\ \tan error message is issued and the processing might terminate.\n\ \tRefer to the Library Compiler manuals for supported commands. W UIL-1 Overwriting an old symbol library '%s' file with a new one. W UIL-2 Overwriting an old technology library '%s' file with a new one. W UIL-3 The '%s' library has not been read in yet. E UIL-4 The '%s' library source file is not found. E UIL-5 The read_lib command does not support '%s' as the\n\ \t'-format' switch value. The only format allowed is 'edif'. W UIL-6 The Library Compiler is not enabled. The cell\n\ \tfunctionality is ignored. E UIL-7 Cannot write the library to the '%s' file. E UIL-8 The '%s' pin of the '%s' cell in the '%s' technology library\n\ \tis not found in the same cell of the '%s' symbol library. E UIL-9 The '%s' cell does not exist in the '%s' symbol library. E UIL-10 Trying to compare a '%s' library with a '%s' library.\n\ \tcompare_lib compares a technology library and a symbol library. E UIL-12 Trying to compare a library with itself. compare_lib\n\ \tcompares a technology library and a symbol library. E UIL-13 The specified '%s' library cannot be found in memory. W UIL-15 No libraries in the '%s' library file. E UIL-16 Cannot find the '%s' library or library file in memory. E UIL-17 Could not open the '%s' file for reading. E UIL-18 Could not open the '%s' file for writing. E UIL-19 The '%s' cell does not exist in the '%s' technology library. E UIL-20 The '%s' symbol in the '%s' symbol library has an extra '%s' pin. E UIL-21 The '%s' synthetic module does not exist in the '%s' library. E UIL-23 Invalid output format '%s'. E UIL-24 Unacceptable VHDL library generation.\n\ \tYou must read in the `%s` library from a technology library source file. E UIL-25 The '-symbol' option can only be used with the '-format EDIF' option. E UIL-26 Unacceptable list of cells for the '%s' library. E UIL-27 Invalid technology library timing report.\n\ \tYou must read in the `%s` library from a technology library source file. W UIL-28 The '%s' vendor specific delay model is used in this library.\n\ \tThe library timing report might be incomplete. E UIL-29 The '%s' library is a synthetic library.\n\ \tUse the report_synlib command. E UIL-30 The '%s' library is not a synthetic library.\n\ \tUse report_lib command. W UIL-32 The '%s' model library is different from the current link library. E UIL-33 Invalid technology library state table report.\n\ \tYou must read in library `%s` from a technology library source file. I UIL-34 Updating technology library (please save) ... W UIL-35 operating conditions '%s' not overwritable in lib '%s' W UIL-36 operating condition already defined in lib '%s' I UIL-37 The DCM vendor specific delay model is used in this library.\n\ \tThe library report will not contain timing-related information. E UIM-1 State '%s' is not a state in the state machine. E UIM-2 Illegal list of states. E UIM-3 Design must be a state table inorder to set state order. E UIM-4 Design does not contain any states. E UIM-5 Illegal state vector list. E UIM-6 Non state table designs must have the complete \ encoding specified. E UIM-7 Illegal state encoding list. E UIM-8 Invalid encoding style '%s'. E UIM-9 Encoding '%s' used multiple times. E UIM-10 Encodings have inconsistent length. E UIM-11 Encoding '%s' has invalid characters. E UIM-12 Invalid flatten minimize value '%s'. E UIM-13 State '%s' used multiple times in encoding list. E UIMG-1 Cannot %s design over existing design '%s' E UIMG-2 Cannot %s a design to a file E UIMG-3 Cannot %s design; no access to path '%s' E UIMG-4 Cannot %s multiple designs to a single design E UIMG-5 The 'uniquify_naming_style' variable must be\n\ \tset to use this command. E UIMG-6 '%s' is not a valid setting for the\n\ \t'uniquify_naming_style' variable. E UIMG-7 The '-force' option cannot be used if the\n\ \t'-cell', '-reference' or '-new_name' options are used. E UIMG-8 The '-new_name' option can only be used\n\ \tif one cell is specified. E UIMG-9 The '-reference' option cannot be used if\n\ \tthe '-cell' or '-new_name' options are used. E UIMG-10 Could not find the specified cell(s). E UIMG-11 Cannot find design named '%s'. E UIMG-12 Cell '%s' is linked to design '%s', which\n\ \tis a library design, so it cannot be uniquified. W UIMG-13 No cells were uniquified. E UIMG-14 Rules '%s' are not defined. E UIMG-15 Bad -type option '%s' specified. E UIMG-16 Default rules '%s' are not defined. E UIMG-17 No name rules specified and no default.\n\ \tUse the -rules option or set the default_name_rules variable. E UIMG-18 Can't open names file '%s'. E UIMG-19 Too many errors in names file '%s'. W UIMG-20 No valid name changes found in names file '%s'. E UIMG-21 Invalid class string '%s'. W UIMG-22 Can't find %s '%s' in %s '%s'. I UIMG-23 Using name rules '%s'. I UIMG-24 No name changes to report in design '%s'. I UIMG-25 %d names changed using names file '%s'. W UIMG-26 File %s,\n\ line %d: unsupported class string '%s' in '%s'. W UIMG-27 File %s,\n\ line %d and\n\ File %s,\n\ line %d : duplicate change for %s '%s'. \n\ Previous change will be overwritten by the latest one. W UIMG-28 File %s,\n\ line %d: Can't find %s name '%s'. W UIMG-29 File %s,\n\ line %d and\n\ File %s,\n\ line %d : Unsupported multiple names files.\n\ %s '%s' was the new name of %s '%s' in %s '%s'. W UIMG-30 File %s,\n\ Line %d:A %s named '%s' already exists in design '%s'. W UIMG-31 File %s,\n\ Line %d: Can't find %s '%s' in %s '%s'. W UIMG-32 File %s,\n\ Line %d: ObjectType: %s\n\ BusMemberName: '%s' BusPortName: '%s'\n\ change_names can not be applied to individual BUS MEMBER.\n\ Please specify the BUS PORT NAME instead. E UIMG-33 File %s,Line %d:\n\ A DELIMITER '%s' is expected,which stops reading this names file.\ There are five fields separated by spaces in names_file formate.\n\ E UIMG-34 File %s,Line %d:\n\ A DELIMITER '%s' is not expected, which stops reading this names file. W UIMG-35 The variable "%s" has set to "%s" from "". W UIMG-36 In design %s, %s bus member '%s' changed to '%s'. I UIMG-40 Because you are in the simple compile mode, \ uniquifying the design will result in degradation of runtime. E UIO-1 Design Compiler is not enabled. E UIO-2 %s must be 'low', 'medium' or 'high'. E UIO-3 Could not read the following target libraries: E UIO-4 flatten_minimize strategy must be 'single_output', 'multiple_output' or 'none'. E UIO-5 The library %s already contains a design %s. E UIO-6 Background directory %s exists. E UIO-7 Could not create directory %s. Permission denied. E UIO-8 Could not read the following synthetic library: E UIO-9 Cannot use '%s' option with the '%s' option. W UIO-10 Overwriting the library '%s' with design '%s'.\n\ \tThe library already contained this design and is now modified. E UIO-11 None of the target libraries are enabled for in_place optimization. I UIO-12 Choosing a test methodology will restrict the optimization of sequential cells. E UIO-13 The design '%s' already exists in library '%s' and\n\ \tcannot be overwritten by the 'model' command. E UIO-14 Could not read generic technology library '%s' W UIO-15 No target library specified. E UIO-16 Design '%s' contains cluster information;\n\ \tthe compile cannot be run when clusters are present. E UIO-17 Design does not meet the requirements of the\n\ \treoptimize_design command. E UIO-18 The %s option can only be used in\n\ \tconjunction with the %s option(s). E UIO-19 No routability constraint on design. Use set_min_porosity. W UIO-20 Porosity constraint on design (%g) overwritten by default \n\ porosity constraint in target libraries (%g). Using the default porosity constraint. W UIO-21 No routability information in target library '%s'. E UIO-22 No target library has routability information.\n Design was \ not optimized. E UIO-23 Design '%s' contains cluster information;\n\ the %s command cannot be run when clusters are present. W UIO-24 Design '%s' does not contain back-annotated\n\ \tcapacitance and/or resistance values. E UIO-25 DC-Expert license is not enabled for '%s'. E UIO-26 Floorplan-Management license is not enabled for '%s'. W UIO-27 Must have a Behavioral Compiler license to use '%s'. E UIO-28 Design scan style is not supported by the -scan option. E UIO-29 You cannot specify polarity unless you use\ the async_reset option. E UIO-30 Cannot find reset_port %s on design %s. E UIO-31 You have to specify the polarity of the reset to\ be either active high or low. E UIO-32 Unexpected value for polarity.\ Accepted values are high and low. W UIO-33 optimize_registers no longer flattens the\ design hierarchy by default. Unless you specify the flatten option,\ the hierarchy of the design will be preserved. E UIO-34 You have to choose either the flatten\ or the dont_flatten option. E UIO-35 ECO-Compiler license is not enabled for '%s'. W UIO-36 You have chosen the 'no_incremental_map' option of\n\ \tthe '%s' command. The resulting circuit may NOT show the best possible\n\ \tarea and timing yet. You have to run an optimizing 'compile' command\n\ \tto achieve these. E UIO-37 insert_pads accepts design objects as arguments E UIO-38 The number of stages you have chosen is lower than two. E UIO-39 You have specified both a synchronous and and asynchronous\ reset port. E UIO-40 You have specified a reset polarity but no reset port. E UIO-41 The number of stall ports that you have specified does\n\ \tnot match the number of stages. E UIO-42 Two stall ports have the same name ('%s' and '%s'). E UIO-43 A stall port ('%s') has the same name as the clock port\ ('%s'). E UIO-44 A stall port ('%s') has the same name as the synchronous\n\ \treset port ('%s'). E UIO-45 A stall port ('%s') has the same name as the asynchronous\n\ \treset port ('%s'). E UIO-46 The clock port ('%s') has the same name as the\n\ \tsynchronous reset port ('%s'). E UIO-47 The clock port ('%s') has the same name as the\n\ \tasynchronous reset port ('%s'). E UIO-48 The reset polarity must be either 'high' or 'low'. '%s'\ has been specified. E UIO-49 The stall polarity must be either 'high' or 'low'. '%s'\ has been specified. E UIO-50 '%s' has been specified as the clock port, but there is\n\ \tno such external port in design '%s'. E UIO-51 '%s' has been specified as the reset port, but there is\n\ \tno such external port in design '%s'. E UIO-52 '%s' has been specified as a stall port, but there is no\n\ \tsuch external port in design '%s'. If you have a port of the correct name,\n\ \tit must be exactly one bit wide. E UIO-53 The stall port '%s' does not have direction 'in'. E UIO-54 The reset port '%s' does not have direction 'in'. E UIO-55 The clock port '%s' does not have direction 'in'. E UIO-56 The name '%s' is not a legal HDL identifier for \n\ \ta (non-vector) single bit port. E UIO-57 You have specified a stall polarity but no stall port. W UIO-58 As a result of -prioritize_min_path, min_delay \ is made a higher priority than max_delay. W UIO-59 Setting attribute 'fix_multiple_port_nets' on design '%s'. W UIO-60 Ignoring compile_fix_multiple_port_nets = %s. W UIO-61 Setting attribute 'critical_range' on design '%s'. W UIO-62 Ignoring compile_default_critical_range = %g. W UIO-63 Setting attribute 'cost_priority' on design '%s'. W UIO-64 Attribute 'cost_priority' overrides '%s'. E UIO-65 DC ultra license is required to use feature '%s'. E UIO-66 Command '%s' unable to acquire DC ultra license. I UIO-67 %s mode successfully set. W UIO-68 %s mode not set. E UIO-69 The async_reset option has been discontinued\n\ \tbecause of quality of results and correctness issues. If you need\n\ \tto retime registers with asynchronous clear or preset Please\n\ \tcontact the Synopsys Support Center or your Synopsys AC for\n\ \tfurther support. If you do not want to retime registers with\n\ \tasynchronous clear or preset, please remove the async_reset and\n\ \tthe polarity option from the command. W UIO-70 The 'verbose' options has been used without the\n\ \t'check_design' option and will be ignored. I UIO-71 %s mode successfully reset. E UIO-72 Option '%s' not recognized. I UIO-73 %s optimization mode successfully set. I UIO-74 %s optimization mode successfully reset. E UIO-75 Instances of design '%s' have inconsistent \fBdont_touch\fP\ attributes. I UIO-76 DC simple compile mode successfully set. I UIO-77 DC simple compile mode successfully reset. W UIO-78 Ignoring '%s' option. E UIO-80 The '-quickturn' option of compile cannot be used without a Quickturn supplied library. I UIO-81 Enabling special fast optimization for Quickturn libraries. W UIO-85 Ignoring design cell degradation information. W UIO-86 Ignoring library cell degradation information. W UIO-90 variable '%s' is obsolete; see the manual page. W UIO-91 Multiple designs named '%s' occur in the link_library. \n\ \tNone of these designs will be used during link.\n\ \tDesign '%s' ignored. W UIO-92 Design '%s' comes before design '%s' in the \ link_library; '%s' will be ignored. I UIO-93 Design '%s' is referenced in design '%s'. E UIO-94 Current design is not defined. E UIO-95 %s must be 'none', 'low', 'medium' or 'high'. E UIO-96 Doing reoptimize_design without back-annotation E UIO-97 Cannot estimate load or delay without RC coefficients E UIO-98 Illegal combination of reoptimize_design options W UIO-99 options '%s' is obsolete; see the manual page. W UIO-100 Doing compile -in_place without back-annotation E UIO-101 Doing reoptimize_design without delay back-annotation E UIO-102 Doing reoptimize_design without load back-annotation E UIO-103 Command '%s' is enabled only in the incremental mode. E UIO-104 You have optimized your design but have not saved your timing\n\ \tresults. Please either save your results or use the -no_sdf\n\ \toption. E UIO-105 You have optimized your design but have not saved your pdef\n\ \tplacement results. Please either save your results or use the\n\ \t-no_pdef option. E UIO-106 You have read pdef information for your design but have not saved\n\ \tit. Please either save your results or use the -no_pdef option. I UIO-107 The current design remains unchanged since entering \ the incremental mode. I UIO-108 Back-annotation data was not saved within the current design. E UIO-109 Doing reoptimize_design without delay back-annotation and cell locations E UIO-110 Doing reoptimize_design without net load back-annotation and cell locations W UIO-111 Doing reoptimize_design without cell location W UIO-112 The -verify option of this command\ is not supported in the incremental mode. Use the -verify option of \ the begin_incr_mode command. E UIO-130 Directory '%s' is not a valid script directory. E UIO-131 The option \fBsync_transform\fP requires\n\ \tone of the values \fBdecompose\fP, \fBmulticlass\fP or\n\ \t\fBdont_retime\fP. E UIO-132 The option \fBasync_transform\fP\n\ \trequires one of the values \fBdecompose\fP, \fBmulticlass\fP\n\ \tor \fBdont_retime\fP. E UIO-133 The options \fBsync_state\fP and\n\ \t\fBasync_state\fP require one of the values \fBpreserve\fP\n\ \tor \fBdont_care\fP. E UIP-1 The module '%s' could not be found in the library '%s'. E UIP-2 The design '%s' could not be found. E UIP-3 The library '%s' could not be found. E UIP-4 A design named '%s' has already been associated with module '%s'. W UIP-5 No designs in the library '%s' have been prebuilt using the technology '%s'. E UIP-6 Could not build the synthetic design '%s'. E UIP-7 The library '%s' is not a valid synthetic library. E UIP-8 The library '%s' is not a valid technology library. E UIP-9 The cell '%s' cannot have its implementation set. E UIP-10 The wire_load model '%s' could not be found in library '%s'. E UIP-11 '%s' is not a valid argument for set_resource_allocation.\n\ \tIt should be one of 'none', 'area_only', or 'constraint_driven'. E UIP-12 '%s' is not a valid argument for set_resource_implementation.\n\ \tIt shoule be either 'area_only', or 'constraint_driven'. E UIP-101 Cannot find "example" %s '%s'. E UIP-102 Cannot find "exact" %s '%s' E UIP-103 "example" or "exact" cell '%s' is not an I/O pad. E UIP-107 No port '%s' in design. E UIP-108 Cannot set pad attributes on '%s'. W UIP-109 Both "exact" and "example" options used. No attributes set. E UIPD-1 Can't open update file '%s'. E UIPD-2 Can't write update output file '%s'. E UIPD-3 Output file has to be different than the script file '%s' being updated. E UIS-1 Create_schematic command is not available. E UIS-2 Invalid output order. W UIS-3 Design '%s' isn't mapped. E UIS-4 Design '%s' could not be linked. E UIS-5 Plot command is not available. E UIS-6 Design %s has no schematic. E UIS-7 Design Compiler is not enabled. E UIS-8 Design '%s' could not be timed. E UIS-9 Invalid pin list. E UIS-10 No valid pins/ports specified. E UIS-11 Bad sheet type '%s' specified. W UIS-12 Design '%s' has no cells! E UIS-13 X Interface is not enabled. E UIS-14 X has to be running to view a schematic. E UIS-15 No minx device coordinate specified. E UIS-16 No miny device coordinate specified. E UIS-17 No maxx device coordinate specified. E UIS-18 No maxy device coordinate specified. E UIS-19 There is no sheet named '%s'. E UIS-20 No plot command is specified. E UIS-21 The plot operation did not work. Is the plot_command variable set correctly? E UIS-22 Invalid layer characteristic name. E UIS-23 Wrong type value: '%s' for characteristic name: '%s'.\n\ \tExpecting an integer. E UIS-24 Wrong type value: '%s' for characteristic name: '%s'.\n\ \tExpecting a floating point number. E UIS-25 Wrong type value: '%s' for characteristic name: '%s'.\n\ \tExpecting 'true' or 'false'. E UIS-26 Generic schematic library not specified. E UIS-27 Couldn't read schematic library '%s'. W UIS-28 Font library not specified. W UIS-29 Couldn't read font library '%s'. E UIS-30 Can't generate schematic - options are bad. E UIS-31 Bad sheet fill '%d' specified. E UIS-32 Couldn't read generic symbol library '%s'. W UIS-33 Couldn't read symbol library '%s'. E UIS-34 'gen_max_ports_on_symbol_side' value must be positive. E UIS-35 The -critical_path option must not be\n\ specified if other options are specified. E UIS-36 Either -critical_path or some ports and pins must be specified. E UIS-37 No sheets were specified with the -sheet_list option. E UIS-38 Couldn't find a ripper for bussing in gen. W UIS-39 The value of variable 'gen_bus_%s_naming_style'\n\ \tcontains the invalid conversion string '%%%c'. W UIS-40 The value of variable 'gen_bus_%s_naming_style'\n\ \tcontains no occurrences of '%%%s'. W UIS-41 The value of variable 'gen_bus_%s_naming_style'\n\ \tcontains %d occurrences of '%%%s'. W UIS-43 The value of variable '%s' isn't valid--using '%s'. W UIS-44 The variable '%s' isn't defined--using '%s'. W UIS-45 The order of '%%d' and '%%s' in the variable \n\ \t'gen_bus_%s_naming_style' is not correct. E UIS-46 You cannot specify both the 'object_list' and \n\ \tthe 'object_type' arguments. E UIS-47 The '%s' argument must be a list of equations (strings). W UIS-48 Schematic for proprietary design '%s' not generated. E UIS-49 The format string must not have more than %d %%s specifications. E UIS-50 The format string contains %d %%s specification(s),\n\ \tbut the value list has %d equation(s). E UIS-51 Could not read either the generic symbol library: '%s',\n\ \tor the default library: '%s'.\n\ \tYour software is probably installed incorrectly. W UIS-52 Could not read the specified generic symbol library: '%s'.\n\ \tHad to read the default generic symbol library instead.\n\ \tYour search_path is probably incorrect or pointing to\n\ \tan older version of Synopsys software. E UIS-53 Current design '%s' has no symbol view. E UIS-54 Target system does not allow mixed bus ports. E UIS-55 Target system does not allow compound names. E UIS-56 Target system does not allow rippers. E UIS-57 Unknown target system specified for schematics. E UIS-58 More than one bussing style specified: using default. W UIS-59 Net '%s' has no drivers. W UIS-60 Cell '%s' has no output or bidirect pins. E UIS-61 You cannot use '%s' to highlight schematics. E UIS-62 current_highlight_layer is only defined if the current_design is defined. E UIS-63 There is no layer named \"%s\". E UIS-64 Highlight layer name \"%s\" is invalid.\n\ \tIt should be of the form \"highlight_layerN\", where N\n\ \tis a positive integer. W UIS_42 The value of variable 'gen_bus_%s_naming_style'\n\ \tends with the invalid '%%' (single percent sign). E UISN-1 No valid synthetic library specified. E UISN-2 Module '%s' not found. E UISN-3 Verification implementation not found for module '%s'. W UISN-4 Implementation '%s' not found. E UISN-5 No default check_parameters for module '%s'. W UISN-6 Binding '%s' not found. E UISN-7 Parameters may only be specified if all specified bindings\n\tare for a single operator. E UISN-8 No %s for operator '%s'. E UISN-9 Invalid parameter \"%s\" for operator '%s'. E UISN-10 Wrong number of pin_widths specified in '%s' for operator '%s'. E UISN-11 No such pin '%s' in pin_width '%s' for operator '%s'. E UISN-12 Pin '%s' in pin_width '%s' for operator '%s' specified twice. E UISN-13 at least one option (-priority or -set_id) must be specified. E UISN-14 set_id cannot be negative. E UISN-15 You can set priority of implementations only. E UISN-16 Environment variable '%s' is an unsupported type. W UISN-17 Unable to access read cache directory '%s'. It will be ignored. W UISN-18 Unrecognized key '%s' found in 'synlib_dont_get_license' variable. W UISN-19 Library '%s' in 'synlib_preferred_library' variable is not in the synthetic library list.\n\ \tThis name is deleted from the preferred library list. E UISN-20 The dynamic module '%s' does not exist in the dynamic synthetic library.\ W UISN-21 The module '%s' is not a dynamic synthetic module, it is ignored. E UISN-22 Unacceptable list of modules for dynamic synthetic library.\ E UISN-23 Unknown synthetic library check '%s'.\n\ \tValid checks are '%s'.\ W UISN-24 Skipping check of implementation '%s' for module '%s'.\ W UISN-25 No implementations to check for module '%s'.\ W UISN-26 The following synthetic libraries should be added to\n\ \tthe list of link libraries:\n\ \t'%s'.\ I UISN-27 Evaluating DesignWare library utilization.\ E UISN-28 %s key is required to enable this feature. E UISN-29 Unable to check out DC Ultra keys. W UIT-2 Unrecognized compaction mode ignored. E UIT-3 Unrecognized test program format or missing license key. W UIT-4 You have asked for scan replacement, but attributes show that the design already has scan circuitry. Your request is ignored. W UIT-5 No existing test circuitry to route, scan will be inserted.\ E UIT-6 Cannot load test vector database file. W UIT-8 Design has no scan path. Generated vectors will not be saved. E UIT-9 Test clock period of %.2f on port '%s' is inconsistent with period of %.2f specified in the test protocol. E UIT-10 internal failure, write_test vector formatter (stran) failed. E UIT-11 internal failure, write_test vector formatter (stran) failed. (%d). W UIT-12 Invalid input dont-care value '%s'. Must be one of 0, 1, X. I UIT-13 The variable atpg_test_asynchronous_pins is obsolete. It has no effect. E UIT-14 internal error, key error for write_test formatter (stran). E UIT-15 internal error, write_test formatter (stran) can not generate '%s' format. E UIT-16 No scan chains extracted for design - patterns cannot be formatted. W UIT-18 ATPG will not check for bus %s. E UIT-19 No test protocol exists for design '%s'. E UIT-20 Cannot open output test protocol file '%s'. W UIT-21 Unrecognized backtrack effort '%s' ignored. W UIT-22 Only %d%% of faults were considered in ATPG run. E UIT-23 No test protocol defined for design - patterns cannot be formatted. W UIT-24 vhdlout_single_bit="%s" not supported; assuming vhdlout_single_bit="VECTOR". E UIT-25 Specified value for %s differs from value in test protocol for design. E UIT-26 Strobe value is required to be less than period value. E UIT-27 %s is a serial-only vector format. E UIT-28 Current test protocol cannot be used with a parallel load format. E UIT-29 No nets have global tracing enabled in design '%s'. E UIT-30 Global tracing not enabled for net '%s' in design '%s'. E UIT-31 Cannot find vector file '%s' written by TestSim. E UIT-32 Bad protocol format '%s'. W UIT-34 Redundant TCK period specification `%f' ignored.\n\ \tExisting TCK period `%f' (frequency `%e') retained. E UIT-39 The test_require attribute cannot be set on the three-state driver '%s'. E UIT-41 No implementation for component "%s" supplied. E UIT-42 '%s' is not a valid value for %s option of the check_test command. I UIT-43 %s won't force conditioned bidirectionals. I UIT-44 Assuming %s for combinational methodology. I UIT-45 %s won't find the best scan-out pins. I UIT-46 %s will create dedicated subdesign scan-out ports. W UIT-47 Ignoring the request for dedicated subdesign scan-out ports.\n\tHierarchical isolation was also requested. W UIT-48 Scan insertion will not add clock gating logic. W UIT-49 Scan style '%s' does not implement scan clock gating. Ignoring the set_scan_configuration -clock_gating command. W UIT-50 Test methodology '%s' does not implement scan clock gating. Ignoring the set_scan_configuration -clock_gating command. W UIT-51 Area-critical partial scan is not enabled. Ignoring the set_scan_configuration -area_critical true command. W UIT-52 Test methodology '%s' cannot not scan cells on timing critical paths. Ignoring the set_scan_configuration -area_critical command. I UIT-53 Enabling area critical partial scan. W UIT-87 Assignment of %s-only BSR cells to port `%s`\n\ \tis not compliant with the IEEE 1149.1 JTAG standard. E UIT-88 Data register `%s` pin of type `%s` not found. E UIT-89 An illegal implementation `%s`\n\ \thas been specified for JTAG component type `%s`. E UIT-90 set_jtag_implementation must be invoked with a legal\n\ \tcomponent type. `%s` is not a recognized component type. W UIT-91 Illegal JTAG ground_bounce value `%d` replaced by `%d`. I UIT-92 User defined instruction '%s' not associated with\n\ \tidentifiable data register. Dangling signals will be synthesized. W UIT-93 One or more ports have been excluded from the JTAG\n\ \tBoundary Scan Register (BSR). JTAG logic synthesized based on this\n\ \tconfiguration will not be compliant with the IEEE 1149.1 JTAG standard. E UIT-94 Erroneous JTAG data register '%s' associated with JTAG\n\ \tinstruction '%s'. E UIT-95 JTAG logic already inserted into this design.\n\ \tinsert_jtag not invoked. E UIT-96 Port '%s' excluded from the JTAG Boundary Scan Register (BSR).\n\ \tNo BSR cells can be associated with it. E UIT-97 '%s' not an input or output port.\n\ \t(You must specify '/out', '/in' or '/ctl'.) E UIT-98 '%s' not a port of the current design. E UIT-99 Unrecognized BSR cell specifier '%s'.\n\ \t(Must be '/out', '/in' or '/ctl'.) E UIT-100 Instruction Register (IR) too small.\n\ \tThis design requires an %d-bit register. E UIT-101 JTAG Test Access Port (TAP) I/O port '%s' may not be included\n\ \tin the boundary scan register (BSR). E UIT-102 Illegal JTAG boundary scan port mode '%s' specified. E UIT-103 Illegal JTAG boundary scan port signal type '%s' specified. E UIT-104 Requested Instruction Register size '%d' is less than\n\ \tpreviously specified Instruction code size '%d'. E UIT-105 Instruction '%s' has code fixed by the 1149.1 JTAG standard.\n\ \tIt may not be replaced by code '%s'. W UIT-106 The 1149.1 JTAG standard instruction '%s' does not\n\ \tsupport register coordinate specification.\n\ \t(Specifications ignored.) E UIT-107 Code length '%d' of instruction '%s' conflicts with a\n\ \tpreviously specified instruction code length '%d'. E UIT-108 The code '%s' for instruction '%s' conflicts with the\n\ \tcode for instruction '%s'. E UIT-109 BSR cell '%s' has been assigned multiple routing positions. W UIT-110 Compliance with the IEEE's 1149.1 JTAG Standard requires\n\ \ta BYPASS Register. This implementation is non-compliant. W UIT-111 JTAG component implementation '%s' not found.\n\ \tThe default implementation will be used instead. E UIT-112 Target core register '%s' not found. I UIT-113 Creating user defined instruction '%s'.\n\ \t(not a 1149.1 JTAG standard instruction) I UIT-114 Creating 1149.1 JTAG standard instruction '%s'. E UIT-115 Illegal joint specification of -no_internal scan and\n\ \t-daisy_chained internal scan. (Specify only one of these options.) I UIT-116 Instruction '%s' has been cancelled. E UIT-117 Mandatory instruction '%s' may not be cancelled. E UIT-118 JTAG insertion terminated abnormally. E UIT-119 Three-state cell `%s` controlling port(s)\n\ \tin the JTAG Boundary Scan Register not at the top level of the design. W UIT-120 -no_asynchronous_reset option invoked\n\ \tbut port '%s' with jtag_trst attribute found.\n\ \tPort '%s' will NOT be included in the JTAG Boundary Scan\n\ \tRegister (BSR).\n E UIT-121 Erroneous JTAG Manufacturer ID Number '%d'. E UIT-122 Erroneous JTAG Part Number '%d'. E UIT-123 Erroneous JTAG Version Number '%d'. I UIT-124 \tNumber out of legal range.\n\ \t(Must be between %d and %d inclusively.) W UIT-125 -cancel mode should be invoked with instruction name only.\n\ \t(Other arguments will be ignored.) E UIT-126 `00001111111' (127) is an illegal Manufacturer ID when\n\ \tused in JTAG ID registers. E UIT-127 Direction of pin '%s' is erroneous. E UIT-128 Port '%s' must have pad attribute set. W UIT-129 -default should be invoked alone.\n\ \t(Other arguments will be ignored.) E UIT-130 No options specified for the "%s" command.\n\ \tFor available options, execute "%s -help". E UIT-131 JTAG Port '%s' is not an input or bidirectional port. E UIT-132 JTAG Port '%s' is not an output or bidirectional port. E UIT-133 JTAG Port '%s' is not three-stated. E UIT-134 Insufficient information included with user-specified\n\ \tinstruction '%s'. You must include either a register name or both\n\ \treg_coordinate(s) and reg_enable specifications. E UIT-135 Instruction '%s' has illegal JTAG instruction\n\ \tcode string '%s'.\n\ \t(The code string must contain only '0's and '1's.) E UIT-136 Incompatible arguments. Specify either a register name or\n\ \tboth register coordinate(s) and register enable. E UIT-137 Instruction Register (IR) must be between 2 and 32 bits wide. E UIT-138 Non-existent BSR '%s' cell with routing\n\ \tposition '%d' associated with port '%s'. E UIT-139 -no_internal_scan invoked but instruction '%s' specifies\ core scan chain '%s'. W UIT-140 The Test Compiler specific JTAG instruction '%s'\n\ \tdoes not support register name or coordinate specification.\n\ \tSpecifications ignored. E UIT-141 Bad model scale factor, must be positive. E UIT-142 Bad model load value, should not be negative. E UIT-143 Bad model drive value, should not be negative. W UIT-144 Port '%s/%s' is not an input or inout port; model_drive not set. E UIT-145 Erroneous specification of a list of ports since\n\ \tset_jtag_implementation has not been invoked with a Boundary Scan\n\ \tRegister (BSR) component. E UIT-146 Three-state cell `%s`\n\ \t(technology library cell `%s`) is dont_touch. E UIT-147 Invalid sample percentage value '%d'. W UIT-148 All memory elements are assumed scannable for test generation of partial scan design. I UIT-149 The set_jtag_part_number command is overriding the\n\ \tenvironmental variable "jtag_part_number" value `%d'\n\ \tby `%d'. I UIT-150 The set_jtag_manufacturer_id command is overriding the\n\ \tenvironmental variable "jtag_manufacturer_id_number" value `%d'\n\ \tby `%d'. I UIT-151 The set_jtag_version_number command is overriding the\n\ \tenvironmental variable "jtag_version_number" value `%d'\n\ \tby `%d'. W UIT-152 The '%s' command is ignored. A '%s' license\n\t is required for this command. E UIT-153 The sum of strobe time (%10.2f) and strobe width value (%10.2f) is required to be less than period value (%10.2f). E UIT-154 Unable to fault-simulate vectors because %s. E UIT-155 write_test could not find the intermediate (SIF) file to be formatted. E UIT-156 write_test failed to open temporary file to be used during vector formatting. E UIT-157 Insufficient memory, write_test failed to format vectors. E UIT-158 internal error, write_test formatter executable (stran)\ failed due to syntax error in input (SIF) file. E UIT-159 internal error, unexpected end-of-file found in input file to the write_test formatter executable (stran). E UIT-160 Unsupported vector format '%s' specified in the -format option. E UIT-161 %s . Vector translation terminated prematurely. W UIT-162 IDDQ simulation disabled. IDDQ defects will not be simulated. E UIT-163 JTAG Port '%s' is not an input port. E UIT-164 JTAG Port '%s' is not a two-state output port. E UIT-165 %s time (%10.2f) must be less than strobe time (%10.2f). E UIT-166 The output test program name must be different from the input vector file name, '%s'. E UIT-167 Test program '%s' does not match the design '%s'.\n. E UIT-168 Test program '%s' does not match the design '%s'.\ Could not get value for port '%s' in test program. This port is present \ in the design. E UIT-169 The '-use_testsim_model' and '-save_testsim_model' options cannot be used together. E UIT-170 Value '%s' is not supported for the clock_gating option.\n\ \tUse either 'entire_design' or 'leaf_cell' as values. E UIT-171 The test program sequence contained in the test program '%s'\n\ \tdoes not match the expected test program sequence. I UIT-172 Formatting of test vectors was successful for test program '%s'. W UIT-173 Formatting of test vectors failed for test program '%s'. W UIT-174 You cannot use the -output option with the -cumulative option.\n\ \t The -output option will be ignored. E UIT-175 Could not mask/unmask the object '%s'. E UIT-176 The object '%s' specified with the -except option is not a subset\n\ \tof anything in the primary object list. Command ignored. W UIT-177 You cannot use the -all option as well as specify the object list with the set_test_unmask_fault command.\n\ \t The -all option wins. All faults in the entire design will be unmasked. E UIT-178 You must either use the -all option or specify the object list with the set_test_unmask_fault command. E UIT-179 The -sample option should be given an integer between 1 and 100. E UIT-180 You cannot use fault masking when the multi_pass_test_generation variable is off. E UIT-181 You cannot use fault masking when the TestManager license is not available. W UIT-182 You cannot perform multi-pass test generation when the TestManager license\n\ \t is not available. This %s run will target the entire fault list. E UIT-183 Invalid string '%s' specified in the -eval_probables option. E UIT-184 JTAG instruction '%s' not yet declared, so it cannot be cancelled. E UIT-185 LSSD designs are not currently supported by TestSim. E UIT-186 Illegal IDDQ fault model '%s'. Choose between 'shorts' and 'toggle'. E UIT-187 Either a TestSim or an IDDQSim license is required for this function. W UIT-188 Stuck-at fault simulation disabled. Stuck-at faults will not be simulated. E UIT-189 Can't write output vdb file '%s'. I UIT-190 Using TC-DFT license only. Generated vectors will not be saved. E UIT-191 '%s' is not a known clock domain restriction. E UIT-192 '%s' is not a known clock gating technique. E UIT-193 Can not insert '%s' scan chains. E UIT-194 '%s' is not a known bidirectional mode. W UIT-195 Arguments override the default script file name, but do not ask for a script. None will be generated. W UIT-196 '%s' is a %s and can not be used to specify a scan signal port. W UIT-197 '%s' is a %s and can not be used to specify a scan signal pin. E UIT-198 '%s' is not a scan signal type. E UIT-199 '%s' is not a signal type for the '%s' scan style. W UIT-200 %s port '%s' can not be a %s. W UIT-201 did not complete set_signal_type. '%s' is a %s, not a design port. W UIT-202 did not complete set_signal_type. %s port '%s' can not be a %s. W UIT-203 %s pin '%s' can not be a %s. E UIT-204 There is no valid scan port. E UIT-205 No specified hookup pin is valid. W UIT-206 %d scan ports have been specified. Only the first will be processed. W UIT-207 %d hookup pins have been specified. Only the first will be processed. W UIT-208 There is no scan chain called '%s'. Specification is ignored. W UIT-209 %d scan ports have been specified, but access pins or scan chains have been specified also. Only the first scan port will be processed. E UIT-210 '%s' is not a known scan link type. W UIT-211 '%s' is not a scan signal type. Discarding specified access point. W UIT-212 '%s' does not identify a design pin. Discarding specified access point. W UIT-213 Access point specification is not paired. Last specification is incomplete and is discarded. E UIT-214 Link name '%s' identifies a design cell. Link specification creates ambiguity and is discarded. E UIT-215 Segment name '%s' identifies a design cell. Specification creates ambiguity and is discarded. W UIT-216 %s pin '%s' can not be a %s. E UIT-217 '%s' is not a signal type for the '%s' scan style. W UIT-218 Segment access list has multiple hookup points for signal type '%s'. All but the first is discarded. W UIT-219 Segment access list has multiple signal types for hookup point '%s'. All but the first is discarded. W UIT-220 Scan chain '%s' has scan style '%s' that differs from design scan style '%s'. Specification is ignored. W UIT-221 '%s' identifies multiple pins. Discarding specified access point. W UIT-222 Segment '%s' does not have scan style '%s' and is not being added to the scan chain. W UIT-223 '%s' is not a cell, instance, scan segment, or scan link, and is not being added to the scan chain. W UIT-224 write_test_max_scan_patterns value specified (%d) ignored. W UIT-225 write_test_max_cycles value specified (%d) ignored. W UIT-226 Scan chain element '%s' is a scan link\n\tand is not being added to the scan chain. W UIT-227 Scan style '%s' does not add lockup latches to the scan chain.\n\ \tIgnoring the set_scan_configuration -add_lockup command. W UIT-228 Ignoring preview_scan -show option argument '%s'. W UIT-229 Scan style '%s' does not need scan clock domain constraints. Ignoring the set_scan_configuration -clock_mixing command. I UIT-230 To support new scan insertion capabilities, this command is being replaced by the set_scan_path command, which is used with the insert_scan command. Please see the Test Compiler Reference Manual for more information about set_scan_path and insert_scan. E UIT-231 Can't find vector file '%s'. W UIT-232 Coverage threshold option ignored. Coverage threshold must be greater than 0%%. W UIT-233 Coverage threshold option ignored. Coverage threshold must be less than or equal to 100%%. W UIT-234 Coverage threshold option ignored because -no_stuck_at option has been used. E UIT-235 cannot generate TSTL2 format, too many timing types. W UIT-236 You have invoked preview_scan with both -script and -show options. The -show option is ignored. I UIT-237 You have invoked remove_scan_configuration with no options. The command is ignored. I UIT-238 To support new scan insertion capabilities, this command is being replaced by the insert_scan command. Please see the Test Compiler Reference Manual for more information about insert_scan. I UIT-239 To support new scan insertion capabilities, this command is being replaced by the set_scan_path command, which is used with the insert_scan command. Please see the Test Compiler Reference Manual for more information about set_scan_path and insert_scan. I UIT-240 Some design changes may have occurred after "create_test_patterns" or "create_test_patterns" was run in a different dc_shell session. W UIT-241 Ignoring the -complete true option because scan chain '%s' is empty. I UIT-242 The %s attribute on the library cell %s now has priority over this attribute on an instance, reference or design. W UIT-243 The design %s corresponding to the object %s has the %s\n\ attribute set to true. This specification will not have any effect. W UIT-244 The design %s corresponding to the object %s has the %s\n\ attribute set to true. This specification will not have any effect for the level-\n\ sensitive elements inside %s. W UIT-245 Deleting the scan transparent attribute on object %s. E UIT-246 Compliance enable specification is not paired. E UIT-247 '%s' is not a port of the design. E UIT-248 Multiple design objects found with name '%s'. E UIT-249 The value specified at a compliance enable port must be either a '0' or a '1'. E UIT-250 The following compliance enable port is not an input port: %s. E UIT-251 The following compliance enable port is a TAP port: %s. W UIT-252 No TAP ports were found for the design. E UIT-253 The following port appears more than once in a\n\ \tcompliance enable pattern: '%s'. I UIT-254 Writing '%s' package description. I UIT-255 Overwriting '%s' package description. I UIT-256 Deleting '%s' package description. E UIT-257 Could not find package '%s'. E UIT-258 Naming check must be one of 'VHDL', 'BSDL' or 'none'. E UIT-259 Unable to open output file '%s' for writing. I UIT-260 Opened BSDL file '%s' for writing. E UIT-261 Cannot read file '%s'. E UIT-262 File '%s' is a directory name. W UIT-263 %d ports have been specified. Only the first will be processed. W UIT-264 %s port '%s' can not be a %s. E UIT-265 There is no valid test mode port. E UIT-266 '%s' is not a test mode signal type. W UIT-267 Port '%s' has a '%s' signal_type attribute. This may conflict with '%s' signal semantics. W UIT-268 Port '%s' has a test_hold '%s' attribute. This conflicts with '%s' signal semantics. E UIT-269 The type of a Test Access Port must be one\n\ \tof %s, %s, %s, %s, or %s. E UIT-270 More than one port specified with the set_1149.1_port command. E UIT-271 Did not complete set_bsd_port. '%s' is a %s, not a design port. E UIT-272 Did not complete set_bsd_port. %s port '%s' can not be a %s. E UIT-273 A port, '%s', with a signal type of '%s' already exists in the design. E UIT-274 The '%s' port is a system clock. E UIT-275 The '%s' port is a test clock. W UIT-276 Overwriting the signal type attribute for the port '%s'. E UIT-277 The '' list has no members. I UIT-278 You invoked remove_bsd_specification with no\n\ \toptions. The command is ignored. W UIT-279 The sense value '%s' is ignored. E UIT-280 '%s' is not a correct hookup sense type. I UIT-281 Setting the default package for the design '%s'. I UIT-282 Overwriting the default package for the design '%s'. E UIT-283 The signature for the RUNBIST instruction is empty. E UIT-284 The signature for the RUNBIST instruction is invalid. E UIT-285 The wait specification for the RUNBIST/INTEST instruction is missing. E UIT-286 The time specified for RUNBIST/INTEST\n\ \tto complete must be a positive real number. E UIT-287 The clock_port-num_cycles list in the wait specification\n\ \tfor the RUNBIST/INTEST instruction is empty. E UIT-288 The RUNBIST/INTEST execution time\n\ \tspecification is not paired. E UIT-289 The number of clock cycles in the RUNBIST/INTEST wait specification must be a positive integer. E UIT-290 Could not find port '%s' in the design '%s'. E UIT-291 The '%s' port in the wait specification is not an input port. E UIT-292 The '%s' port in the RUNBIST/INTEST duration specification is not a system or test clock. E UIT-293 The '%s' port appears more than once in the RUNBIST/INTEST wait specification. I UIT-294 Writing the parameters for the INTEST instruction. I UIT-295 Overwriting the parameters for the INTEST instruction. I UIT-296 Writing the parameters for the RUNBIST instruction. I UIT-297 Overwriting the parameters for the RUNBIST instruction. E UIT-298 The '%s' port is not an IEEE 1149.1 Test Access Port. E UIT-299 Could not remove the '%s' IEEE 1149.1 test access port. W UIT-300 The specified routing signals are ignored because \ the -route option is set to false. E UIT-301 The specified routing signal type '%s' is incorrect. W UIT-302 The specified routing signal type '%s' is not valid for the scan style '%s'. W UIT-303 The -internal_clocks option will be ignored. \ It only applies to multiplexed-Flip-Flop scan style. W UIT-304 Restoring Constrained value for port '%s'. E UIT-305 '%s' is not a DFT signal type. W UIT-306 %d DFT ports have been specified, but access pins have been specified also. Only the first port will be processed. W UIT-307 '%s' is a %s and cannot be used to specify a DFT signal port. W UIT-308 '%s' is a %s and cannot be used to specify a DFT signal pin. W UIT-309 %s port '%s' cannot be a %s. E UIT-310 There is no valid DFT port. E UIT-311 No specified hookup pin is valid. W UIT-312 %s pin '%s' cannot be a %s. W UIT-313 %d DFT ports have been specified. Only the first will be processed. W UIT-314 %d hookup pins have been specified. Only the first will be processed. I UIT-315 The list of ports from which the DFT signals are to be removed is empty. E UIT-316 At present, the '%s' command only supports the full scan test methodology. E UIT-317 At present, the '%s' command supports only the multiplexed flip-flop scan style. I UIT-318 The '%s' command will become obsolete in the 2000.04 release. Please use '%s' instead. E UIT-319 Cannot change the scan style for a '%s' design.\ W UIT-320 You have asked for no optimization. The map effort argument is ignored. E UIT-350 '%s' is not a standard instruction. E UIT-351 The '%s' instruction is not supported. I UIT-352 Writing boundary-scan instruction '%s'. W UIT-353 Overwriting boundary-scan instruction '%s'. W UIT-354 %d boundary scan TAP ports have been specified. Only\n\ \tthe first boundary scan port will be processed. E UIT-355 There is no valid boundary scan TAP port. W UIT-356 %d boundary scan ports are specified. Only the\n\ \tfirst will be processed. E UIT-357 Instruction encoding must be one of 'default' or 'one_hot'. I UIT-358 You must specify at least one of the following switches:\n \ -asynchronous_reset \n \ -default_package \n \ -instruction_encoding . I UIT-359 The set of boundary scan instructions to be removed is empty. I UIT-360 Removing boundary scan instruction '%s'. W UIT-361 Could not remove boundary scan instruction '%s'. W UIT-362 Could not find boundary scan instruction '%s'. I UIT-363 The list of ports from which the boundary scan signals are to be removed is empty. W UIT-365 The direction switch may only be used with bidirectional ports. W UIT-366 Ignoring the command for the %s ports. W UIT-367 Observe-only is not a valid boundary scan cell type for %s port. E UIT-368 Invalid boundary scan cell type '%s'. Boundary scan cell type must be one of 'none', 'observe_only' or 'control_observe'. E UIT-369 Invalid direction argument '%s'. The direction must be one of 'in' or 'out'. E UIT-370 Scan specification on cell '%s' would make multibit '%s' in design '%s' non-homogeneous. W UIT-371 Multibit '%s' in design '%s' is not a scan segment. W UIT-372 The '%s' option of the set_scan_segment command does not apply to synthesizable segments; the option is ignored. W UIT-373 The '%s' option of the set_scan_segment command does not apply to user segments; the option is ignored. W UIT-374 Multibit '%s' is already a synthesizable segment. W UIT-375 '%s' is already a segment. I UIT-376 There is no explicit synthesizable segment specification for multibit '%s'; it remains%s a synthesizable segment, as specified in the scan configuration. I UIT-377 The explicit synthesizable segment specification for multibit '%s' is removed; now, it is%s a synthesizable segment, as specified in the scan configuration. E UIT-378 Instance '%s' is not in the system. E UIT-379 Incorrect value of -clock option argument. Allowed values\ are true, TRUE, on, and ON; or false, FALSE, off, and OFF. E UIT-380 Incorrect value of -async option argument. Allowed values\ are true, TRUE, on, and ON; or false, FALSE, off, and OFF. E UIT-381 Incorrect value of -fix_protocol option argument. \ Allowed values are true, TRUE, on, and ON; or false, FALSE, off, and OFF. E UIT-382 Incorrect value of -string option argument. \ Allowed values are true, TRUE, false, or FALSE. E UIT-383 No port of name %s was found in design %s. E UIT-384 Port %s is not a test clock. E UIT-385 Port %s is not of type input. W UIT-386 Cannot find cell %s in design %s. W UIT-387 Cell %s is combinational; you must\ use a sequential cell or a hierarchical cell with sequential \ elements. E UIT-388 You cannot specify more than one clock. E UIT-390 Clock port %s has a hold value of %s. You cannot\n\ \tspecify a clock port that has a hold value set on it. I UIT-391 Performing set_autofix_clock of\n\ \tclock "%s" on cell/instance "%s". E UIT-400 internal error, write_test vector formatter (stran) is unable\n to write out status.\ E UIT-401 Unknown -command option argument '%s' for preview_scan, assuming 'insert_scan' (default). E UIT-402 BSD config style must be one of 'synchronous' or 'asynchronous'. E UIT-403 BSD instruction width must be in the range of 2 to 16. E UIT-404 Boundary scan register type for a bidirectional port must be one of 'BC_7' or 'none' E UIT-405 Boundary scan register type for an input port must be one of 'BC_1' or 'BC_2' or 'BC_4' or 'none' E UIT-406 Boundary scan register type for an output port must be one of 'BC_1' or 'none' E UIT-407 Invalid port type is specified for the user defined BSR/TAP/Boundary Scan Data Register E UIT-408 Invalid port or control BSR name E UIT-409 Port direction must be one of 'in' or 'out'. E UIT-410 Invalid bidirectional port is specified E UIT-411 Specified pin doesn't exisits E UIT-412 Control BSR cell can be specified only for ports attached to tristate pads. E UIT-413 Specified port doesn't exists on the design or instance. E UIT-414 Specified instance doesn't exsists in the current design. E UIT-415 Boundary scan register element type must be one of 'BC_1' or 'BC_2' or 'BC_4' or 'BC_7' E UIT-416 Control Boundary Scan Register type must be one of 'BC_1' or 'BC_2' E UIT-417 Boundary scan register type must be one of 'BC_1' or 'BC_2' or 'BC_4' or 'BC_7' or 'none' E UIT-418 Specified design doesn't exsists. E UIT-419 Boundary Scan Data Register name can not be 'BOUNDARY' or 'BYPASS' . E UIT-420 Invalid bidirectional port is specified E UIT-421 Invalid bidirectional port is specified E UIT-422 Invalid bidirectional port is specified E UIT-423 Invalid bidirectional port is specified E UIT-444 '%s' is a PrimeTime command that is not supported by Design Compiler. E UIT-580 The test_modes value, %s, specified is not a valid value. E UIT-581 The client %s specified is not a valid dft client. E UIT-590 A configuration for port %s already exits. E UIT-591 Duplicate control specification for %s data port of %s. E UIT-592 %s has a clock port specified for it that is \ different from the port specified in the command. E UIT-593 %s specified as clock port in the command does not exist on the cell E UIT-594 Multiple ports named %s on Object %s E UIT-595 The read control pattern is not paired (port value) E UIT-596 port %s not found on %s E UIT-597 Illegal value %s speicified in the read control for port %s E UIT-598 Illegal direction for port %s E UIT-599 port %s has already been specified in the read control pattern E UIT-600 %s, %s specification conflicts with previous value specified on %s E UIT-601 cound not find object named %s E UIT-602 %s is an output port. It can't have an write control. E UIT-603 The read control pattern is missing or empty E UIT-604 The current design does not exist E UIT-605 The direction of port %s is missing E UIT-606 The port configuration information is missing for %s E UIT-607 No objects specified in the command E UIT-608 attribute not found on %s E UIT-609 %s is an output port; can't have a write control E UIT-610 Illegal object type. Need reference or design E UIT-611 Black_boxes are not supported. E UIT-612 Port %s not found on %s E UIT-613 Object %s not found in %s E UIT-614 Wrapping a constant is not supported W UIT-615 %s has already been specified for wrapping W UIT-616 %s has already been wrapped W UIT-617 %s has already been specified as clock port for %s port E UIT-618 '%d' is not a valid value for %s option of the rtldrc command. E UIT-619 '%s' is not a valid disabling option for a tristate net. I UIT-620 Writing the disable option for the tristate net '%s'. W UIT-621 Overwriting the disable option for the tristate net '%s'. E UIT-622 The '%s' object is a '%s'. E UIT-623 '%s' is not a bidirectional port. I UIT-624 Writing the mode in scan shift for the bidirectional port '%s'. W UIT-625 Overwriting the mode in scan shift for the bidirectional port '%s'. E UIT-626 '%s' is not a valid disabling option for internal tristate nets. E UIT-627 '%s' is not a valid value for the \fB-prtool\fP option\ argument. W UIT-628 The design '%s' is not scan completed and cannot be represented with a test model. E UIT-630 Pin '%s' is not sticky. E UIT-631 Net '%s' has no sticky pins. E UIT-632 You must specify at least a capacitance or resistance value. E UIT-633 You must specify a net or pin object or -all. E UIT-634 You must -capacitance and/or -delay E UIT-635 Net '%s' must have a set_load value. W UIT-650 a test point in pin %s of type %s already exist.\n\ \tIt will be deleted and replaced with the new new one. I UIT-651 Test point in location %s of type %s \n\ \tis being deleted. E UITCL-100 Can't get object name of multiple objects;\n\ \tOnly a single object collection accepted. E UITCL-101 Cannot split list elements of value '%s' for variable '%s'. W UITCL-102 The update_script command is not supported in Tcl mode;\n\ \tUpdate_script is available in dcsh only.\n\ \tTo translate dcsh to tcl format, use the dc-transcript program. E UITE-100 Design mode configuration '%s' is not defined. E UITE-101 Design mode '%s' is not defined in mode configuration '%s'. E UITE-102 No design modes have been defined. E UITE-103 Design mode group '%s' is already defined. E UITE-104 Input port '%s' not found. E UITE-105 Port '%s' must be an input or inout port. E UITE-120 Invalid waveform. Edges must be an even number of monotonically\n increasing values less than one period in duration. W UITE-121 Creating virtual clock named '%s' with no sources. E UITE-122 The 'create_clock' command cannot be used on output port '%s'. W UITE-123 Creating a clock source on inout port '%s'. E UITE-124 Cannot remove internal path group '%s'. E UITE-125 Invalid delay direction for port '%s'. E UITE-126 Unable to %s on path from '%s' to '%s'. I UITE-127 Found a design with sdf backannotation:\n\t(design '%s', file '%s').\n\tPerformance will be better by reading the db with -netlist_only and\n\tthen reading the sdf file with read_sdf. E UITE-128 Unable to set %s on '%s'. E UITE-129 Unable to remove %s on '%s'. E UITE-131 Design mode '%s' is already defined. E UITE-132 Mode '%s' does not exist on cell '%s'. E UITE-133 Pin '%s' is not a valid %s. W UITE-150 Negative clock latency specified: %g E UITE-200 Must specify %s option along with %s option.\ W UITE-201 Option '%s' is valid only with option '%s'.\ E UITE-202 The factor for -MULTIPLY_BY/-DIVIDE_BY '%d' is \ not a power of two.\ E UITE-203 The number of edges specified '%d' is not an \ odd number > 3.\ E UITE-204 The number of edge_shifts specified '%d' \n\ \tusing '-EDGE_SHIFT' option is not equal to the number of edges specifed '%d' \ using '-EDGES' option.\ E UITE-205 Expected to find, at most, two numbers along with \ the option '%s', but found %d.\ E UITE-206 The clock %s is a generated clock.\ E UITE-207 A generated clock has already been defined\ with the name %s.\ E UITE-208 You can specify only a single object for master \ clock source.\ E UITE-209 You cannot specify an output port '%s' to be a \ generated clock master source.\ E UITE-210 You cannot create generated clock on '%s' port. E UITE-211 The -edges spec of generated clock '%s' has edge number\n\ \tless than 1, the edge number should be from 1 up. E UITE-212 In the -edge specification of create_generated_clock\n\ \t'%s', the edge numbers must be in increasing order. E UIV-1 Specify one of the following: -list, -resize, -scroll, -enter,\n\t -motion, -button, -key. E UIV-2 If -scroll is specified, -value must also be specified. E UIV-3 If -list, -resize and -scroll are not specified, -type must be specified. E UIV-4 '%s' is not a valid selection for '%s'. E UIV-5 View object '%s' does not exist. E UIV-6 If -resize is not specified, widget_name must be specified. E UIV-7 If resize is specified, the width and height must be specified. E UIV-8 If -list is specified, -value must also be specified. E UIV-9 Window number '%d' does not exist. E UIV-10 One of the -settings, -value arguments must be used. E UIV-11 Parameters to the -settings argument must be strings. E VAL-1 Parsing error in the association list '%s'. W VAL-2 The value '%s' from parameter '%s' is being omitted. W VAL-3 The parameter/generic value '%s'\n\ \t in design '%s' exceeds the threshold length %d. Excluding\ the parameter from the design name. E VAL-4 Internal parameter parser error, unrecognized token "%s". E VAL-5 Array members must be of the same type.\n\t%s E VAL-6 Illegal value for aggregrate member "%s". E VAL-7 Aggregrate elements must be separated by commas:\n\t%s E VAL-8 Arrays can only be concatenated with arrays:\n\t%s E VAL-9 Strings can only be concatenated with strings:\n\t%s E VAL-10 Parameter name must be followed by a legal value:\n\t%s E VAL-11 Illegal parameter name "%s". E VAL-12 Unexpected end of parameter specification:\n\t%s E VAL-13 "%s" is not a valid parameter value. E VAL-14 Parameter specifications must be separated by commas:\n\t%s E VAL-15 Negative integers with radix not supported: "%s". E VAL-16 This form of Verilog integer syntax not supported: "%s". E VAL-17 Parameter value, '%s', must have 32 bits or fewer. E VE-0 %s E VE-1 Unable to open file '%s' W VE-2 Unsized number %s is too big. It will be truncated to 32 bits %s E VE-3 Undefined variable '%s' used %s E VE-4 Variable '%s' defined more than once %s E VE-5 Cannot assign to constant '%s' %s E VE-6 Illegal assignment to reg '%s' %s E VE-7 Illegal assignment to wire '%s' %s. E VE-8 Module/Function name '%s' defined more than once\n\ \t%s E VE-9 Component '%s' instantiated more than once %s E VE-10 Ambiguous direction declaration for port '%s'\n\ \t%s E VE-11 Port '%s' defined more than once %s E VE-12 Port '%s' used before being assigned a direction\n\ \t%s E VE-13 Port '%s' not defined in module terminal list but defined\n\ \tin an input/output/inout statement %s E VE-14 Port '%s' has no defined direction (input/output/inout)\n\ \t%s E VE-15 Attempt to disable block/function '%s' which is not active\n\ \t%s E VE-17 Continuous Assignment made to reg '%s' %s. W VE-18 Wand and Wor declarations treated as Wire declaration\n\ \t%s E VE-19 Initial statement not supported %s E VE-20 Task statement not supported %s E VE-21 Depending on edge and non-edge expression not supported %s. E VE-22 Depending on 2 edges of same variable '%s' not supported\n\ \t%s E VE-23 All asynchronous conditions must be tested in an "if" statement\n\ \t%s E VE-24 You must specify an "else" clause for the clocked logic\n\ \t%s E VE-25 Can't test variable '%s' because it wasn't in the event expression\n\ \t%s E VE-26 Testing wrong polarity of variable '%s'\n\ \t%s E VE-27 Delay/Event control not allowed in continuous assignment statement\n\ \t%s E VE-28 Resource '%s' defined more than once %s E VE-29 Resource '%s' not defined %s E VE-30 Expected semicolon (;) at end of statement %s W VE-31 Resource declaration legal only in functions and blocks\n\ \t%s W VE-32 Attributes for resources can be assigned only in functions\n\ \tand blocks %s W VE-33 Directive '%s' must be scoped inside a function\n\ \t%s W VE-34 Illegal directive '%s' ignored %s W VE-35 Directive '%s' must be scoped inside a module\n\ \t%s W VE-36 Directive '%s' declared more than once %s E VE-37 Unknown enumerated type '%s' %s E VE-38 Declaration of enumeration type requires range specification\n\ \t%s E VE-39 Enumerated type '%s' declared more than once %s W VE-40 Value assignment to parameters of instantiated modules is not supported. It is ignored %s W VE-41 Port number %d of module '%s' was renamed to '%s'. W VE-42 TIME declarations are not supported %s W VE-43 EVENT declarations are not supported %s W VE-44 DEFPARAM is not supported %s E VE-45 Resource declarations are not allowed in unnamed blocks\n\ \t%s E VE-46 Attribute declarations are not allowed in unnamed blocks\n\ \t%s W VE-47 Width specified for number %s is too small.\n\ \tHigher order bits will be truncated %s E VE-48 Incorrect number of terminals for bufif/notif %s E VE-49 Expected identifier to label resource %s E VE-50 End of file seen before %s block begun at line %d was ended E VE-51 Illegal use of array of register '%s' %s E VE-52 'include' directive requires a filename enclosed in double quotes\n\ \t%s E VE-53 Recursive file inclusion detected for file "%s" E VE-54 RTL assignments are allowed only when no blocking delays are used\n\ \t%s E VE-55 Blocking delays are allowed only when no RTL assignments are used\n\ \t%s E VE-56 RTL assignments are not allowed for wires\n\ \t%s E VE-57 A reg can only be assigned with all RTL assignments or\n\ \tall procedural assignments %s. E VE-58 Identifier '%s' previously declared %s E VE-60 Unable to open file '%s' included by the 'include'\n\ \tdirective %s W VE-61 Assignments to supply nets are ignored %s W VE-62 'use_mux' directive is not supported %s E VE-70 Access to variables external to a module is not allowed from\n\ \tinside functions and tasks %s E VE-71 Assignment to external variables is not supported\n\ \t'%s' E VE-72 %s is not a construct in up or down path of module\n\ \t'%s' E VE-73 Component %s has not been instantiated in module\n\ \t'%s' E VE-74 Module %s not defined E VE-75 Intra module hierarchical name (%s) not supported in module '%s' E VE-76 Cannot find symbol '%s' in module '%s' E VE-77 Nested module names and intra-module hierarchical names not supported\n\ \t in module '%s' E VE-78 Cannot find variable %s in module '%s' E VE-79 Module %s defined more than once E VE-80 (Internal error) Unable to add extra port to contained design E VE-81 (Internal error) Unable to create connection for new port E VE-91 In an event expression with 'posedge' and 'negedge' qualifiers, only\n\ \tsimple identifiers are allowed %s E VE-92 The expression in the reset condition of the 'if' statement in this\n\ \t'always' block can only be a simple identifer or its negation\n\ \t(%s) E VE-93 The statements in this 'always' block are outside the scope of the\n\ \tsynthesis policy (%s).\n\ \tOnly an 'if' statement is allowed at the top level in this 'always'\n\ \tblock. Please refer to the HDL Compiler reference manual for ways\n\ \tto infer flip-flops and latches from 'always' blocks. E VE-94 Asynchronous conditions for an 'always' block can only be compared\n\ \tto 0 or 1 %s E VE-95 Unsupported global reference %s E VE-96 Redefinition of Object %s %s E VE-97 Mismatched directive %s W VE-98 Macro %s is redefined %s W VE-100 No arguments specified for pragma '%s' %s W VE-101 Pragma '%s' requires two arguments. The second argument must be a string enclosed in double quotes %s W VE-102 Pragma '%s' accepts only one argument %s W VE-103 More than one %s pragma specified for %s %s W VE-104 The pragma '%s' for object %s will be ignored because the object could not be accessed. E VE-105 %s has already been specified as a master process for a slave process %s E VE-106 %s has already been specified as a slave process for a master process %s W VE-107 The "master_process_is/slave_process_is" pragma has been ignored because the %s process'%s' could not be found. E VE-108 For loop termination condition does not match index direction %s I VE-109 Make sure there is an assertion block in the design\n\ \tfor directive '%s' %s. W VE-110 The directive '%s' for the group containing object '%s'\n\ \tis ignored because the object is not defined %s. W VE-111 The directive '%s' requires an argument containing\n\ \tmore than one object %s. E VE-112 The directive '%s' must be scoped inside a named block %s. W VE-120 This design contains multiple nets of type 'wired_and' or 'wired_or'. Please see the extended message for this warning for more information. W VE-121 This design contains event in verilog assignment. Please see the extended message for this warning for more information. W VE-122 Parameter range specification is only meaningful to \ synthesis. Different result may exist from simulations %s. W VE-123 This design contains assignment from wire to reg. Please see the extended message for this warning for more information. E VE-124 Constant at RHS can not fit into LHS %s. W VE-125 The '%s' '%s' is not a legal verilog identifier.\n\ \tIt has been renamed to '%s'. W VER-1 Redundant digits given in number %s W VER-2 Unknown debug option %s W VER-4 Incompatible port connection, port %d of instance %s in module %s W VER-5 Mismatch in number of ports for instance %s W VER-8 Hierarical component name %s is a macromodule - not expandable. E VER-12 Hierarical component name %s is not a module, task, function, or block E VER-15 The call to '$display' does not have enough arguments to satisfy all format specifiers. E VER-16 First parameter of $dumpvars must be an integer E VER-17 Incompatiable number of arguments, usage versus declaration E VER-18 Bounds %s for vector %s must be integer. E VER-19 +liborder and +librescan conflict; only one can be specified E VER-20 %s is not a directory E VER-21 Unable to open file %s for %s E VER-22 Too many parameters found on task %s E VER-23 The %s parameter is not completely writable and it is being passed to an OUTPUT or INOUT formal parameter E VER-24 Expression involving %s operator has a real operand E VER-25 %s %s redefined E VER-27 Unable to interrogate %s: %s E VER-28 %s is a function and not a task E VER-33 Incompatible versions between data base and compiler. W VER-35 Register (%s) is the target of both blocking and non blocking assignment in the same process. F VER-36 Internal error: %s, in %s at line %d F VER-37 Internal error <%08x> F VER-38 Internal error <%08x>: %s F VER-39 Attempt to access field %s of a node of type %s F VER-40 Too many errors; compilation aborted F VER-41 Unable to open file `%s': %s F VER-43 Out of memory W VER-44 Little argument or return value checking implemented for system task or function %s F VER-45 %s is not a module data file F VER-50 %s is a function and not a task F VER-51 internal error: %s E VER-59 Array index out of bounds %s. E VER-60 Array index out of bounds %s. W VER-61 Statement unreachable %s. E VER-64 Option '%s' must be non-negative. E VER-65 Option 'hdlin_decoder_min_use_percentage' must be in the range 0..100 (currently %d). W VER-66 Won't infer decoders with input width > %d; option '%s' set too large. E VER-83 Divide by zero detected in expression. W VER-86 Comparison against 'x' values not inside a casex is always false. W VER-91 Module '%s' contains a supply1 variable '%s'. Replacing with wire driven by a continuous assignment to 1. E VER-96 Incorrect argument to %s. E VER-97 No input files specified. E VER-98 HDL format must be either Verilog or VHDL E VER-99 HDL format not specified. W VER-100 Floating pin %s connected to ground W VER-103 Pragma is obselete or not implemented. It will be ignored. W VER-104 The '%s' construct is not supported. It will be ignored. E VER-105 Parameterless call to function '%s' should not have parenthesis. E VER-106 Function declaration redeclares symbol '%s'. E VER-107 Functions cannot contain blocking delays. E VER-108 Functions cannot contain event control statements. E VER-109 Function arguments cannot be decalared as 'inout'. E VER-110 Function '%s' not defined. E VER-111 Function arguments cannot be decalared as 'output'. E VER-112 Illegal function declaration using C-style parameter list. E VER-113 Functions cannot enable tasks. E VER-114 Functions cannot contain 'wait' statements. E VER-115 Redefinition of compiler directive '%s' not supported. E VER-116 Redeclaration of symbol '%s' as parameter. E VER-117 Unwritable parameter '%s' passed to 'inout' or 'output' parameter of a task. E VER-118 A constant cannot be passed to an 'output' or 'inout' parameter of a task. E VER-119 Wrong number of arguments in call to function or task '%s'. E VER-120 Port '%s' not declared as 'input', 'output' or 'inout'. E VER-121 Redeclaration of port '%s'. E VER-122 Redeclaration of symbol '%s' as real. E VER-123 Redeclaration of symbol '%s'. E VER-124 Task argument must be specified. E VER-125 Called task '%s' not defined as a task. E VER-126 Called task '%s' not defined as a task. E VER-127 Task '%s' is not defined. E VER-128 Parameterless task call to task '%s' should not have parenthesis. W VER-129 Intraassignment delays for blocking assignments are ignored. W VER-130 Intraassignment delays for non-blocking assignments are ignored. E VER-131 Intraassignment events for blocking assignments are ignored. E VER-132 Intraassignment events for non-blocking assignments are not currently supported. W VER-133 Intraassignment repeat event controls for blocking assignments are ignored. E VER-134 Register '%s' is the target of both blocking and non blocking assignment in the same process. W VER-135 Intraassignment repeat event controls for non-blocking assignment are ignored. W VER-136 Function '%s' with non-empty body is mapped to module '%s'; body will be ignored. E VER-137 Return port name '%s' conflicts with names of function input parameters. W VER-138 Extraneous argument for system function or task '%s' ignored. W VER-139 Parameterless call to function '%s' should not have parenthesis. W VER-140 Nonblocking assignments and blocking delays are not allowed in the same process. W VER-141 Blocking delays and nonblocking assignments are not allowed in the same process. E VER-142 Nonblocking assignments and blocking delays are not allowed in the same process. E VER-143 Blocking delays and nonblocking assignments are not allowed in the same process. E VER-144 Bad named portname found E VER-145 Declarations are supported in named blocks only W VER-146 Time precision is less precise than the time unit. E VER-147 Instantiation %s has mixed ordered and named port connections E VER-148 Gate output %s must be a net E VER-149 Symbol %s not included in portlist E VER-150 Net assignment %s found in net declaration list E VER-151 Named port %s must have a binding. E VER-152 Vector or memory size mismatch on port %s using last declaration E VER-153 Port %s occurs more than once in instance %s of module %s E VER-154 Gate instance with too few ports W VER-155 Non constant assignment to specparm %s E VER-156 Udp initialization value %s is not 0, 1, or X E VER-157 Udp initialization variable %s must be output E VER-158 Too few input entries in table specification E VER-159 Too many input entries in table specification E VER-160 Vector declaration %s not supported in UDPs E VER-161 path element %s should be wire E VER-162 module path source %s not port E VER-163 module path destination %s not port E VER-164 path pulse source %s not defined E VER-165 path pulse destination %s not defined E VER-166 path pulse source %s not port E VER-167 path pulse destination %s not port E VER-168 timing notifier malformed E VER-169 Illegal reference event: expressions not allowed. E VER-170 timing notifier %s should be reg E VER-171 timing function %s has incorrect number of parameters E VER-172 Wire (%s) is connected to both the input and output of the builtin gate. W VER-173 Delays for procedural continuous assignment are ignored. E VER-174 '%s' is listed more than once in port list. W VER-175 IEEE requires input declaration for function %s W VER-176 Delay statements are ignored for synthesis. E VER-177 REAL declarations are not supported by synthesis. E VER-178 REALTIME declarations are not supported by synthesis. E VER-179 TRIAND declarations are not supported by synthesis. E VER-180 TRIOR declarations are not supported by synthesis. E VER-181 TRI0 declarations are not supported by synthesis. E VER-182 TRI1 declarations are not supported by synthesis. E VER-183 TRIREG declarations are not supported by synthesis. E VER-184 PULLDOWN declarations are not supported by synthesis. E VER-185 PULLUP declarations are not supported by synthesis. E VER-186 User-defined primitives (UDP's) are not supported by synthesis. E VER-187 FORK and JOIN constructs are not supported by synthesis. E VER-188 WAIT statements are not supported by synthesis. E VER-189 CASE EQUALITY (===) is not supported by synthesis. E VER-190 CASE INEQUALITY (!==) is not supported by synthesis. E VER-191 TIME declarations are not supported by synthesis. E VER-192 INITIAL statements are not supported by synthesis. E VER-193 Event triggers are not supported. E VER-194 Base of subscript operator %s must be a vector E VER-195 Illegal digit %c in based number F VER-196 Unable to open modfile %s for writing: %s I VER-197 Writing module %s to file %s. E VER-198 Mixed direction ports %s must be nets E VER-199 Udp table has invalid edge specification E VER-200 Port %s must be declared as input E VER-201 Port %s must be declared as output E VER-202 path element %s should be reg or wire E VER-203 pulse limit for path not defined E VER-204 timing reference event %s not port E VER-205 timing reference event %s should have edge identifier E VER-206 Too many parameters passed to system task '%s'. E VER-207 The %s systask parameter must be writable. W VER-208 Register '%s' is the target of both blocking and non-blocking assignments in the same process. W VER-209 Little argument or return value checking implemented for system task or function '%s'. E VER-210 timing reference event %s has wrong edge E VER-211 timing limit malformed E VER-212 timing limit should be positive E VER-213 timing event malforned E VER-214 timing notifier %s malformed E VER-215 timing reference event %s is not IN or INOUT port E VER-216 DEFPARAM assigns to non-parameter %s in module %s E VER-217 Wrong number of ports in UDP instantiation, not the same as declaration F VER-218 Unable to write to modfile %s: %s E VER-219 REPEAT constructs are not supported by synthesis. E VER-220 Unresolved hierarchical name %s in module %s E VER-221 Module %s to be elaborated is not defined in analyzed source files W VER-222 Assignment output %s should be a register W VER-223 Task %s is not implemented; statement skipped. W VER-225 Recommend parentheses when a reduction-or follows bitwise-or. W VER-226 Single element concatenation has unsized number. E VER-229 Value 's' for enumerated type '%s' should be an integer or sized constant. W VER-230 Recommend parentheses when a reduction-and follows bitwise-and. W VER-231 Future releases will not support bit ranges on integers. W VER-232 Specifying strengths with the 'strength' keyword is archaic. E VER-233 Symbol '%s' cannot be used as an argument to the 'disable' statement because it is not a task or named block identifier. E VER-234 Strengths highz0 and highz1 may not be paired together in a strength specification. E VER-235 Strength %s for pullup/pulldown must be a strength0. E VER-236 Strength %s for pullup/pulldown must be a strength1 E VER-237 Strength specifications must have strength0 and strength1 components. E VER-238 Strength declaration in incorrect place. E VER-239 A wire declaration cannot have a drive strength, at symbol '%s'. W VER-240 Strength %s for pullup is redundant. W VER-241 Strength %s for pulldown is redundant. 0-strength defaulting to strong0. E VER-242 Enumerated type '%s' needs a size specification. E VER-244 Enumerated type '%s' has not been declared. E VER-245 Enumerated type '%s' is not compatible with this declaration. E VER-246 Port %s declared as being two different enums. E VER-247 Enumerated type '%s' has multiple declarations. E VER-248 Encoding '%s' for '%s' is the wrong size for this enumerated type. E VER-249 Force output %s must be a register or a net E VER-250 Called function %s not defined as a function E VER-251 Declaration of [] requires msb and lsb (e.g. reg[m:l]). E VER-252 Illegal use of identifier %s E VER-253 Illegal reference to memory %s. E VER-254 Invalid symbol %s found in activation expression E VER-255 Invalid symbol %s found in expression E VER-256 Illegal part selection E VER-257 Invalid symbol %s found as system task argument E VER-258 No semi-colon at end of module name E VER-259 Multiple delays found E VER-260 Symbol %s must be a constant or parameter E VER-261 Continuous assignment output %s must be a net E VER-262 Net symbol %s already defined E VER-263 Bit- or part-selected destination of a force %s must be a net E VER-264 Hierarchical references are not supported for synthesis (%s). E VER-265 RCMOS switches are not supported. E VER-266 RNMOS switches are not supported. E VER-267 RPMOS switches are not supported. E VER-268 RTRAN switches are not supported. E VER-269 RTRANIF0 switches are not supported. E VER-270 RTRANIF1 switches are not supported. E VER-271 TRAN switches are not supported. E VER-272 TRANIF0 switches are not supported. E VER-273 TRANIF1 switches are not supported. E VER-274 Verilog system task %s is not supported. E VER-275 User-defined primitives (UDP's) are not supported. E VER-276 SPECIFY BLOCKS are not supported. W VER-277 Charge strengths are ignored. E VER-500 %s W VER-700 %s W VER-701 Variable index not supported '%s' W VER-702 Unknown wire type '%s' W VER-703 Unknown constant value '%d' E VER-704 Constant width not matched '%d' vs '%d' E VER-705 Constant signal '%s'cannot be at the left hand side. E VER-900 The 'defparam' construct is not supported. E VER-901 The '`define' directive requires commas to be used when separating arguments. E VER-902 The '`define' directive requires arguments to be supplied when parentheses are present. E VER-903 The '`default_nettype' directive cannot occur inside a module. E VER-904 The '`ifdef' directive must have an identifier name after it. E VER-905 The '`else' directive was found without a corresponding '`ifdef' directive. E VER-906 The '`endif' was found without a corresponding '`ifdef' directive. E VER-907 The '`timescale' directive was incorrectly used. F VER-908 The '`unconnected_drive' directive requires 'pull1' or 'pull0' to be used. F VER-909 The '`default_nettype' directive requires a valid wire type. F VER-910 Macro calls are nested too deeply. F VER-911 The '`define' directive must have an identifier name after it. F VER-912 The macro specified with the '`define' directive has a bad parameter list. F VER-913 The macro '%s' has not been defined. F VER-914 End-of-file found before `endif found. F VER-915 The system task/function '%s' is not defined. F VER-916 '%s' is a system function and not a system task. E VER-917 The 'inout' port '%s' is incompatibly declared as 'real'. E VER-918 The 'inout' port '%s' is incompatibly declared as 'reg'. E VER-919 The 'input' port '%s' is incompatibly declared as 'real'. E VER-920 The 'input' port '%s' is incompatibly declared as 'reg'. W VER-921 The macro '%s' you are attempting to undefine with the '`undef' directive is not defined. W VER-922 `macro expansion not support in CLI E VER-923 A valid identifier must follow the '`undef' directive. F VER-924 newline in `%s list in a `define F VER-925 Input files nested too deep '%s'. F VER-926 The '`include' directive requires a filename enclosed in double quotes. F VER-927 The number of parameters for the '%s' macro doesn't match its definition. F VER-928 Severe syntax errors. Compilation aborted F VER-929 The input file specified by the '`include' directive cannot be recursive. E VER-930 System function %s has been defined E VER-931 System task %s has been defined E VER-932 '%s' is a system task and not a system function. E VER-933 The '%s' system call should not have parentheses unless it has at least one parameter. E VER-934 Identifier name '%s' has not been declared. E VER-935 Identifier name '%s' has not been declared. W VER-936 We will assume the undeclared symbol '%s' is a wire. W VER-937 Invalid argument for system function/task %s ignored. W VER-938 Missing expected argument for system function/task %s. W VER-939 The '%s' directive is not supported and will be ignored. W VER-940 Compiler Directive %s is not supported in the CLI W VER-941 Invalid escape sequence '\\%c' in call to '$display'. W VERIL-0 %s E VERIL-1 %s F VERIL-2 %s F VERIL-3 %s E VHD-200 Unexpected %s\n\t %s. Analysis Failed. W VHDL-1 Can't find types for all ports on design '%s'.\n\ \tIt will be written out with its ports bit-blasted. W VHDL-2 '%s' is both a %s and a %s.\n\ \tThe %s is being renamed to '%s'. W VHDL-3 Design '%s' has invalid vhdl types.\n\ \tIt will be written out with its ports bit-blasted. E VHDL-4 Design '%s' is not linked. Use the link command on the design\n\ \tif you would like to write out vhdl for it. E VHDL-5 Could not process the types for the design. E VHDL-6 Could not process the types in the design. Try setting vhdlout_dont_write_types to TRUE. E VHDL-7 You must change 'vhdlout_bit_type' to a bit type that includes a\n\ \tthree-state value when writing out %s. E VHDL-8 This pre-v2.0 db file contains inconsistent type \ information.\n E VHDL-9 You tried to write out two designs ('%s' and '%s') that contained\n\ \t\tdifferent types with the same name ('%s').\n W VHDL-10 The type '%s' in design '%s' was renamed to '%s'. W VHDL-11 The bits in port '%s' in design '%s' have \ inconsistent '%s' constraints.\n\ \tSome constraint information is being lost. W VHDL-12 EQUAL and OPPOSITE attributes on multi-bit ports are being ignored. W VHDL-13 The '%s' '%s' is not a legal vhdl identifier.\n\ \tIt has been renamed to '%s'. E VHDL-14 Record '%s' has duplicate field names '%s' E VHDL-15 The variable '%s' should be a list of lists with each\n\ \tsub-list having exactly three strings in it. E VHDL-16 Unable to model inout ports '%s' and '%s', which are wired together. E VHDL-17 Unable to write a conversion function for the inout %s port '%s'. W VHDL-18 '%s' is not a legal simulator.\n\ \tVariable '%s' is being ignored. W VHDL-19 Target simulator '%s' is not supported when\n\ \t%s is set to "TRUE". W VHDL-20 There are inout ports of type '%s' that are\n\ \tmultiply driven. The type '%s' must be a resolved type or\n\ \tthe vhdl will not simulate. W VHDL-21 STD.TEXTIO package used by design '%s' in file '%s' is not supported for synthesis. E VHDL-22 Stop processing due to a corrupted db file (%s). E VHDL-23 Write command failed due to system error. E VHDL-24 Can not write out the assignment statement for this inout port %s. E VHDL-25 Can not write out this design '%s' with memory operations in it using non-levelized writer. E VHDL-100 Parameter '%s' multiply defined %s E VHDL-101 Variable or signal '%s' defined more than once %s E VHDL-102 Port '%s' defined more than once %s E VHDL-103 Entity '%s' defined more than once %s W VHDL-104 'SIGNAL' declaration for subprogram input port ignored %s E VHDL-105 Unknown type '%s' used %s E VHDL-106 Undefined function, variable or type '%s' %s E VHDL-107 Undefined variable '%s' %s W VHDL-108 'Transport' construct is not supported. It is ignored %s W VHDL-109 Signal assignment delays are not supported. They are ignored %s E VHDL-110 Invalid based integer %s %s W VHDL-111 GUARDED is not supported. It is ignored %s W VHDL-112 TRANSPORT is not supported. It is ignored %s W VHDL-113 GUARDED and TRANSPORT are not supported. They are ignored %s W VHDL-114 Beginning designator '%s' does not match end designator '%s' \n for construct %s W VHDL-115 Access types are not supported. They are ignored %s W VHDL-116 File types are not supported. They are ignored %s W VHDL-117 Record types are not supported. They are ignored %s W VHDL-118 Physical types are not supported. They are ignored %s W VHDL-119 Library clauses are not supported. They're ignored %s W VHDL-120 Bus-resolution function '%s' ignored %s E VHDL-121 Allocators are not supported %s E VHDL-122 Cannot index into scalar variable '%s' %s E VHDL-123 Cannot evaluate to expression or range %s E VHDL-124 Cannot evaluate to range %s E VHDL-125 Cannot cast expression to type '%s' %s E VHDL-126 Multiple 'others' clause in aggregate %s E VHDL-127 Cannot mix named and positional elements in same aggregate %s E VHDL-128 Expected named element in aggregate %s E VHDL-129 Illegal attribute or cast for '%s' %s E VHDL-130 Cannot open file '%s' E VHDL-131 Syntax error %s E VHDL-132 Can only assign to signals using '<=' %s E VHDL-133 Multiple waveform elements are not supported %s E VHDL-134 Cannot read from output port %s E VHDL-135 Cannot assign to input port %s E VHDL-136 Function parameters can only be of mode 'in' %s E VHDL-137 Procedure parameters cannot be of mode 'buf' or 'linkage' E VHDL-138 Cannot assign to signals using ':=' %s W VHDL-139 Label declarations are not valid VHDL %s E VHDL-140 Unexpected unconstrained range specification %s E VHDL-141 Unexpected paranthesised list %s E VHDL-142 Undefined variable %s %s E VHDL-143 Unexpected range specification %s E VHDL-144 Cannot constrain type %s E VHDL-145 Syntax error: identifier expected E VHDL-146 Syntax error: Illegal constraint %s E VHDL-147 Syntax error: Empty paranthesised list %s E VHDL-148 Cannot evaluate to expression %s E VHDL-149 Cannot use type '%s' as variable %s E VHDL-150 Port and generic names can only be simple identifiers %s E VHDL-151 Predefined attributes not supported for enumerated value '%s' %s E VHDL-152 Predefined attributes supported only for arrays and ranges %s E VHDL-153 Cannot evaluate expression to type %s E VHDL-154 Return statement attempts to return expression in a procedure E VHDL-155 Type '%s' multiply defined %s E VHDL-156 Package '%s' defined more than once %s E VHDL-157 Package '%s' not found %s E VHDL-158 Entity class must be 'type' for enumeration encoding %s E VHDL-159 Attributes not supported for operator symbols %s E VHDL-160 'OTHERS' and 'ALL' not supported for attribute specification %s E VHDL-161 Encoding for multiple types not supported in same specification %s E VHDL-162 Type '%s' has already been assigned default encoding %s E VHDL-163 Number of enumerations specified is not equal to the number of \nenumerations specified in the type %s E VHDL-164 All encodings must be of equal length in enumeration %s E VHDL-165 'while' statement not supported %s E VHDL-166 'NEXT' statement is not in loop %s E VHDL-167 'EXIT' statement is not in loop %s E VHDL-168 Cannot use OTHERS along with other choices in a choice expression %s E VHDL-169 Process name '%s' is not unique %s E VHDL-170 Constant '%s' defined more than once %s E VHDL-171 Cannot assign to constants %s E VHDL-172 Component '%s' defined more than once %s E VHDL-173 Attribute '%s' not supported %s E VHDL-174 Incorrect form of 'wait' statement %s E VHDL-175 Wait statements not allowed in processes with sensitivity lists %s E VHDL-176 Resource '%s' defined more than once %s E VHDL-177 Synthesis attribute '%s' must be scoped inside a design %s E VHDL-178 Undefined resource '%s' %s E VHDL-179 Iteration scheme required %s W VHDL-180 Configurations are not supported. They are ignored %s W VHDL-181 Disconnection specifications are not supported. They are ignored %s W VHDL-182 Aliases are not supported. They are ignored %s W VHDL-183 The REGISTER keyword is not supported. It is ignored %s W VHDL-184 The BUS keyword is not supported. It is ignored %s W VHDL-185 Files are not supported. They are ignored %s W VHDL-186 Incomplete type declarations are ignored %s W VHDL-187 Directive '%s' must be scoped inside a subprogram %s E VHDL-188 Error in manual resource binding syntax %s W VHDL-189 Attribute '%s' not supported %s W VHDL-190 Guard expression not supported for blocks %s W VHDL-191 Ports and generics not supported in block statements %s W VHDL-192 Entity statement parts are not supported. They are ignored %s W VHDL-193 Assertion statements are not supported. They are ignored %s W VHDL-194 Generics are not supported. They are ignored %s W VHDL-195 Timeout clause not supported in wait statement %s W VHDL-196 Sensitivity list not supported in wait statement %s W VHDL-197 %s assumed to be of type 'integer' %s E VHDL-198 Entity class must be 'type' for data_class attribute %s E VHDL-199 Type '%s' has already been assigned a data class %s W VHDL-200 Resource sharing attributes are effective only in processes and subprograms %s W VHDL-201 Sensitivity list for process not supported. It is ignored %s E VHDL-202 Enumeration literal '%s' defined more than once in same enumeration type %s W VHDL-203 Expected semicolon (;) at end of statement %s W VHDL-204 Expected "%s" %s W VHDL-205 'THEN' expected after condition following 'IF' keyword %s W VHDL-206 'SELECT' expected after expression following 'WITH' keyword %s W VHDL-207 'IS' expected after the expression following 'CASE' keyword %s W VHDL-208 Initial values for signals not supported %s E VHDL-210 '%s' declaration is not legal in a %s %s E VHDL-211 An 'if' statement is not a concurrent statement %s E VHDL-212 A loop statement is not a concurrent statement %s W VHDL-213 Dc script in %s '%s' ignored E VHDL-214 Signal '%s' illegally redefined %s E VHDL-215 End of file seen before %s block begun at line %d was ended E VHDL-216 Illegal reuse of '%s' %s E VHDL-218 Variable %s is not defined as a record %s E VHDL-219 Suffix of record is not a simple name %s W VHDL-220 Port '%s' does not exist %s\n\ \t"multiple_port" attribute ignored. E VHDL-221 Architecture '%s' defined more than once for same entity %s E VHDL-222 Constant records are not supported %s E VHDL-223 %s is supported only when it is of type 'integer'\n\ \t %s E VHDL-224 Cannot find declaration for component %s E VHDL-225 %s is not a formal port of component %s E VHDL-226 'others' is not legal as a formal name in a port map statement %s E VHDL-227 In a port map statement, formals that are not simple names \n\ \tor simple subelements are not supported %s W VHDL-228 Initial values are not supported for variables %s E VHDL-229 '%s' must be a procedure %s E VHDL-230 Compilation aborted. Too many errors. E VHDL-231 Identifier %s is reserved for internal use. Please use a different\n\ \tname for this entity %s E VHDL-232 Cannot find entity %s W VHDL-240 Dc_shell variable 'bin_path' has incorrect value. W VHDL-241 Cannot execute vhdl parser. Execution will continue with less error\n\ \t checking for the VHDL source. E VHDL-250 Cannot create work directory for VHDL parser E VHDL-251 Unable to initialize workspace for VHDL parser E VHDL-252 Abnormal exit of child process E VHDL-261 Component name is not a simple name %s W VHDL-262 Only simple configurations (specification of architecture for a top\n\ \tlevel entity) are supported. Nested block specifications and component\n\ \tconfigurations are ignored %s E VHDL-263 Expected simple name for architecture %s W VHDL-264 Configuration specifications are not supported. They are ignored %s W VHDL-265 The value '%s' of\n\ \t'vhdlout_preserve_hierarchical_types' is greater than\n\ \tthat of 'vhdlout_single_bit'.\n\ \t'vhdlout_preserve_hierarchical_types' is changed to be equal to\n\ \t'vhdlout_single_bit'. E VHDL-266 '%s' contains the invalid string '%s'. E VHDL-267 The current setting, '%s', of 'vhdlout_package_naming_style' does not produce a valid VHDL identifier. E VHDL-268 '%s' is not valid for 'vhdlout_package_naming_style'. W VHDL-269 The dc_script '%s' will be applied to all\ subsequent entities in this file. W VHDL-270 Configurations are written out only when the\n\ \t'vhdlout_single_bit' mode is 'vector'. E VHDL-271 Design %s contains a type with name matching\n\ \tthe current setting of 'vhdlout_bit_type' (%s), that is more\n\ \tthan one bit wide. Cannot write a VHDL description including this design. W VHDL-272 You must change 'vhdlout_bit_type' to a bit type that \ includes a three-state value when writing out three-state resolution functions. \ If left as is, this description may or may not simulate. E VHDL-273 There is a latch in this un-compiled design.\ Unfortunately, this release cannot write VHDL for latches pre-compile. W VHDL-274 Library cell %s has a pin of unsupported three-state\ driver type. It will be treated as a regular three-state driver type.\ The description may not simulate correctly. W VHDL-275 Library cell %s have three-state pins of different \ driver types, VHDLout cannot handle more than one type on same cell.\ All pins on this cell will be treated as regular three-state driver type.\ The description may not simulate correctly. W VHDL-276 The acceleratable VHDL description that you requested\ could not be written, because your design, '%s', cannot be described using the \ XP-supported VHDL subset. The VHDL description is being written without setting the\ BACKPLANE attribute. E VHDL-277 The VHDL PROCESS on line %d must be labelled. E VHDL-278 The port '%s' in design '%s' has unknown direction. W VHDL-279 STD.TEXTIO package is not supported for synthesis. E VHDL-280 Only global constants are supported as the index constraint for aliasing. E VHDL-281 You cannot take an index or slice of a non-vector alias %s. E VHDL-283 Aliased objects may only be a simple name, an index \ of a simple name, or a slice of a simple name. E VHDL-284 Arbitrary expression for bussed clock index is not supported. W VHDL-285 "BAD CONNECTION - primary input port %s of %s is driven by internal node. W VHDL-2001 Statements in an entity declaration are not supported for synthesis. They are ignored in entity %s %s W VHDL-2021 'BUS' and 'REGISTER' signal kinds are not supported for synthesis. They are ignored %s W VHDL-2022 Initial values for signals are not supported for synthesis. They are ignored %s W VHDL-2023 Type of the generic is assumed to be 'Integer' in synthesis %s E VHDL-2024 Only generics of type INTEGER are supported for synthesis. - %s\n W VHDL-2035 Type %s has already been assigned default encoding %s W VHDL-2040 Attribute %s not supported for synthesis %s W VHDL-2041 Alias declarations are not supported for synthesis. They are ignored %s W VHDL-2042 File declarations are not supported for synthesis. They are ignored %s W VHDL-2043 Disconnection specifications are not supported for synthesis. They are ignored %s W VHDL-2045 Guard conditions for blocks are not supported %s W VHDL-2046 Declaration and use of generics and ports in a block header is not supported %s E VHDL-2047 The attribute '%s' defined on line %d is not\n\ \tcontained within an architecture. Attribute '%s' only\n\ \tapplies to processes, and it must be defined inside of the\n\ \tarchitecture that contains the process. E VHDL-2048 Could not find process '%s' inside of the architecture%s\n\ \tat line %d. The process is referred to by the attribute\n\ \t'%s' defined on line %d. W VHDL-2049 The attribute '%s' is only valid when applied to\n\ \tone of the following:\n\ \t\t%s.\n\ \tOn line %d, the attribute is applied to a(n) %s.\n\ \tThe attribute will be ignored. W VHDL-2050 Timeout clause not supported for synthesis in wait statement %s E VHDL-2060 The translate_on/translate_off pragma has been incorrectly used here\n\ \tinside a construct %s. W VHDL-2090 Declarations in a configuration declaration statement are not supported for synthesis. They are ignored %s W VHDL-2091 Configuration specifications are not supported for synthesis %s W VHDL-2092 Only simple configurations (specification of architecture for a top\n\ \tlevel entity) are supported for synthesis. Nested block specifications and component\n\ \tconfigurations are ignored %s E VHDL-2093 Access types are not supported for synthesis %s W VHDL-2094 File types are not supported for synthesis. They are ignored %s W VHDL-2095 Physical types are not supported for synthesis. They are ignored %s W VHDL-2096 Incomplete type declarations are not supported for synthesis. They are ignored %s W VHDL-2097 Signal assignment delays are not supported for synthesis. They are ignored %s W VHDL-2098 'Transport' construct is not supported for synthesis. It is ignored %s W VHDL-2099 Assert and report statements are not supported for synthesis. They are ignored %s E VHDL-2100 Allocators are not supported for synthesis %s E VHDL-2103 %s E VHDL-2104 indexing of access-type line is not supported %s E VHDL-2105 The suffix all is not supported %s E VHDL-2106 generalized Wait statements are supported only in architectures that are attributed as TESTBENCH %s E VHDL-2107 generalized Wait statements are not supported in architectures whose TESTBENCH attribute is not set TRUE %s E VHDL-2108 Wait statements are not supported in subprograms %s E VHDL-2109 Event and Stable attributes are not supported in subprograms %s E VHDL-2110 An expression of this kind is supported for synthesis, when only one variable is used. This expression has two variables %s and %s %s E VHDL-2111 Aggregate assignment by name is not supported for the field names of a record. E VHDL-2112 %s E VHDL-2120 In a port map statement, formals that are not simple names or simple subelements are not supported for synthesis %s E VHDL-2121 Type conversion on formal associations is not supported for synthesis %s E VHDL-2130 Only simple configurations are supported for synthesis. This configuration declaration is not supported %s E VHDL-2131 Configurations are not supported for direct instantiation during synthesis %s. W VHDL-2132 Explicit architecture specification is not supported for direct instantiation during synthesis %s. E VHDL-2140 Multi-dimensional arrays are not supported for synthesis %s E VHDL-2141 Multiple waveform elements are not supported for synthesis %s E VHDL-2142 Attribute `RANGE or `REVERSE_RANGE can't have index with it %s. E VHDL-2150 This form of wait statement is not supported for synthesis %s E VHDL-2151 Attribute %s%s is not supported for synthesis %s E VHDL-2152 Literal '%s' is not supported for synthesis %s E VHDL-2153 Physical types are not supported for synthesis %s E VHDL-2154 Cannot mix named and positional elements in same aggregate for synthesis %s E VHDL-2155 Deferred constants are not supported for synthesis %s E VHDL-2156 Floating point types are not supported for synthesis %s E VHDL-2157 Type %s not found %s E VHDL-2158 Record types (%s) are not supported in generic\n\ \tdeclarations for synthesis %s E VHDL-2159 Empty string constants are not supported for synthesis %s. E VHDL-2160 The 'event or 'stable attribute (%s) is supported only when the attribute is used in conformance with the style described in the Synopsys manual for the VHDL compiler. W VHDL-2161 Synopsys attribute %s's value is not set to TRUE, \ the attribute is ignored %s E VHDL-2162 Usage of parameters or variables declared in parent \ subprogram is not supported %s E VHDL-2163 The rising_edge or falling_edge function (%s) is supported only when used in conformance with the style described in the VHDL Compiler Reference Manual. E VHDL-2201 An entity named '%s' already exists in this library. (It may be an internal Synopsys design). Please use a different name for your entity. E VHDL-2202 %s is the name of an internal Synopsys design. Please use a different name for your entity. E VHDL-2203 Cannot find entity %s %s E VHDL-2204 Could not find object %s %s. This error can occur if a\n\ \tpackage (%s) that exists in memory also exists in another library referred to\n\ \tin a Library statement. This error can also occur if the package uses\n\ \tsynthesis_off/synthesis_on directives around the object. W VHDL-2205 Package '%s' defined more than once %s E VHDL-2206 You have declared two architectures with the same \ name %s %s E VHDL-2207 You have declared a component inside a for generate\ loop. E VHDL-2221 Type %s is not defined %s E VHDL-2230 '%s' used more than once as the label for an instance. E VHDL-2231 Undefined resource %s %s E VHDL-2232 Entity class must be 'type' for data_class attribute %s E VHDL-2233 Type %s has already been assigned a data class %s E VHDL-2234 Object %s not found %s W VHDL-2235 Type %s not found %s W VHDL-2236 Pragma "out_port_type" must have exactly two arguments %s W VHDL-2237 The pragma '%s' on line %d is not a supported pragma\n\ \tIt will be ignored. E VHDL-2241 Cannot encode multiple types in same attribute specification %s E VHDL-2242 All encodings must be of equal length in enumeration %s E VHDL-2243 The value of Synopsys attribute %s is expected to be name of port, signal or variable %s E VHDL-2244 Synopsys attribute %s's value is expected to be name of\ a process label %s E VHDL-2245 Label %s already has a Synopsys set_reset attribute %s E VHDL-2246 More than one Synopsys attribute \ master_process_is and/or slave_process_is specified for same process label %s E VHDL-2247 Pragma translate_off inside an expression is not supported %s E VHDL-2248 Body of package %s seen before or without its declaration %s W VHDL-2249 The attribute '%s' requires a list of more than one signal %s. W VHDL-2250 Incorrect computation may result because range of the left hand side\n\ \tdoes not cover range of the right hand side for assignment %s. E VHDL-2251 Enabling expression not permitted outside wait statements %s I VHDL-2252 Make sure there is an assertion statement in the design\n\ \tfor attribute '%s' %s. E VHDL-2253 Unsupported type of value\n\ \t in attribute specification - %s. E VHDL-2254 "Time" is an unsupported type - %s\n E VHDL-2255 Generics of type string are not supported - %s\n E VHDL-2256 Range of enum types is not supported %s. E VHDL-2257 unsupported function call %s E VHDL-2260 Bit-slice is not supported in generic for '%s',\n\ \t%s. E VHDL-2262 Enumeration values may not be used as for or for-generate loop bounds E VHDL-2263 Number of enumeration encoding values does not match the number of enumeration values, line %d. E VHDL-2264 Incorrect way to use '%s attribute . E VHDL-2270 The alias declaration%sis invalid because object %s is an alias. Aliases to existing aliases are not supported for synthesis . E VHDL-2271 Cannot use predefined attributes with alias %s%s, as the alias's range is not locally static. E VHDL-2280 'IMAGE is used outside of an attribute statement in a for-generate loop. E VHDL-2281 The attribute RELATIVE_LOCATION does not have a value of the form & INTEGER'IMAGE() & E VHDL-2282 The argument to 'IMAGE is not a for-generate loop index variable. E VHDL-2283 Only the type INTEGER is supported for the prefix of the attribute 'IMAGE %s E VHDL-2284 Declarative regions of generate statements is not \ supported %s W VHDL-2285 VHDL-93 generates different concatenation results from VHDL-87 %s. E VHDL_217 Multiple definition of '%s' %s E VHE-1 Unknown package '%s'. E VHE-2 Entity '%s' was not previously defined. E VHE-3 Architecture '%s' of entity '%s' is already defined. E VHE-4 Generate statements are not supported. E VHE-6 Variable '%s' illegally or multiply defined. E VHE-7 Initial values are not supported for variables. E VHE-8 Instance name '%s' has already been used. E VHE-9 Label name '%s' has already been used. E VHE-10 Iteration ranges must be static. E VHE-11 Error in FOR loop iteration range.\nOnly from/to ranges are supported. E VHE-12 Return statements are not valid except in a procedure or function. E VHE-13 Multiple waveform elements are not supported. E VHE-14 Package '%s' has already been declared. E VHE-15 Component '%s' has already been declared. E VHE-16 Entity '%s' is already defined. E VHE-17 Signal '%s' illegally or multiply defined. E VHE-18 Initial values are not supported for signals. E VHE-19 Constant '%s' illegally or multiply defined. E VHE-20 Type '%s' has already been defined. E VHE-22 Allocators are not supported. E VHE-23 Discrete ranges are not supported in selected signal assignments. E VHE-24 Real numbers are not supported. E VHE-25 Based integers are not supported. E VHE-26 Based real numbers are not supported. E VHE-27 Physical Literals are not supported. E VHE-28 '%s' is not declared. E VHE-29 Block guards are not supported. E VHE-30 '%s' is not declared. E VHE-31 Nested parentheses in type reference. E VHE-32 '%s' is not an array type. E VHE-33 Couldn't open file: '%s'. E VHE-34 Parse error %s. E VHE-35 Only 'work.package_name.all' and 'package_name.all' are supported\nin use statements. E VHE-36 Unknown package '%s' referenced in use statement. E VHE-37 Malformed function declaration. E VHE-38 Error in return value specification. E VHE-39 Ports and generics are not supported in block statements. E VHE-40 Port '%s' is multiply defined. E VHE-41 Generic '%s' is multiply defined. E VHE-42 Unknown identifier: '%s'. E VHE-43 Undefined type '%s'. E VHE-44 This instance name has already been used: '%s'. E VHE-45 Type '%s' is not visible in the current_scope. E VHE-46 Ill-formed range specification. E VHE-47 Malformed qualified expression. E VHE-48 Label name '%s' does not reference a loop. E VHE-49 Can't find the loop for the %s statement. E VHE-50 Label '%s' is unknown. E VHE-51 Do you mean an entity class of 'type' instead of '%s'? E VHE-52 Only single literals are allowed in Synopsys attributes. E VHE-53 Only number and string literals are allowed in Synopsys attributes. E VHE-54 Invalid character in a bit string literal: '%c'. E VHE-55 Unsupported wait statement. Wait statements must be of the form:\n WAIT UNTIL clk = VALUE\n WAIT UNTIL not clk'stable and clk = VALUE ; or\n WAIT UNTIL clk'event and clk = VALUE ;\nWhere VALUE is '0', '1' or an enumeration whose encoding is 0 or 1. E VHE-56 Prefix of the 'BASE' attribute must be a type. E VHE-57 Base type '%s' is not visible. E VHE-58 The RANGE attribute is only supported for variables,\nsignals and types. E VHE-59 The '%s' attribute is unsupported or unknown. E VHE-60 Only array-type aggregates are supported. E VHE-61 Multi-dimensional arrays are not yet supported. E VHE-62 Ill-formed array or slice. E VHE-63 Could not encode '%s' automatically.\nYou must qualify its type explicitly. E VHE-64 Aggregates must be qualified explicitly. E VHE-65 Enumeration '%s' has already been used in enumerated type '%s'. E VHE-66 Unknown enumeration: '%s'. E VHE-67 '%s' is not an enumerated type. E VHE-68 Only constants are allowed in enumeration encoding attributes. E VHE-69 The number of enumeration encodings given does not\nmatch the number of enumerations in the type. E VHE-70 Error in enumeration encoding.\nAll encodings must be the same length. E VHE-71 Expecting a %s value for the '%s' attribute. E VHE-73 Invalid based integer. E VHE-74 The type of the right-hand side of an assignment to an aggregate\nmust be qualified explicitly. E VHE-75 Attempt to use type '%s' in expression or subprogram call. E VHE-76 Aggregates must be all positional or all named. E VHE-77 'OTHERS' must be the last choice in aggregates. E VHE-78 Attempt to use component or subprogram '%s'\nin expression or subprogram call. E VHE-79 Values cannot be returned from procedures. E VHE-80 Generics are not supported in entities and components. E VHE-81 Wait statement processes may have no sensitivity list,\nand wait must be the first statement. E VHE-82 iteration scheme is required E VHE-83 'while' iteration scheme is not supported W VHW-1 Entity statement parts are not supported. They're ignored. W VHW-2 GUARDED is not supported. It is ignored. W VHW-3 TRANSPORT is not supported. It is ignored. W VHW-4 GUARDED and TRANSPORT are not supported. They are ignored. W VHW-5 Guard expressions are not supported. They are ignored. W VHW-6 Sensitivity lists in process statements are not supported.\nThey are ignored. W VHW-7 Sensitivity clauses are not supported in wait statements.\nThey are ignored. W VHW-8 Timeout clauses are not supported in wait statements.\nThey are ignored. W VHW-9 The 'transport' construct is not supported, it's ignored. W VHW-10 Signal assignment delays are not supported. They are ignored. W VHW-11 Assertion statements are not supported, they're ignored. W VHW-12 Configurations are not supported. They're ignored. W VHW-13 Disconnection specifications are not supported.\nThey are ignored. W VHW-14 Aliases are not supported. They are ignored. W VHW-15 The REGISTER keyword is not supported. It is ignored. W VHW-16 The BUS keyword is not supported. It is ignored. W VHW-17 Files are not supported. They are ignored. W VHW-18 Incomplete type declarations are ignored. W VHW-19 Access types are not supported. They are ignored. W VHW-20 File types are not supported. They are ignored. W VHW-21 Record types are not supported. They are ignored. W VHW-22 Physical types are not supported. They are ignored. W VHW-23 Default values are only supported on generics. W VHW-24 The bus keyword is not supported. It is ignored. W VHW-25 The LINKAGE keyword is not supported.\nAssuming 'INOUT'. W VHW-26 Library clauses are not supported. They're ignored. W VHW-27 Multiple choices in aggregates are not supported.\nAll but the first choice are ignored. W VHW-28 Bus resolution functions are not supported.\nSignals will simply be wired together. W VHW-29 Label declarations are not valid VHDL. I VHW-30 Reading VHDL source from: %s. I VHW-31 Aborting due to previous errors. I VHW-32 No errors. W VHW-33 Interface mode '%s' is not supported! Assuming 'in'. W VHW-34 The '%s' attribute is not implemented yet. W VHW-35 Synopsys attribute defined in wrong place. W VHW-36 SYNOPSYS_TRANSLATE_ON comment seen when\ntranslating is already on. W VHW-37 SYNOPSYS_TRANSLATE_OFF comment seen when \ntranslating is already off. W VO-1 Changed instance name %s to %s in module %s. W VO-2 Changed wire name %s to %s in module %s. W VO-3 Net(s) of type 'tri' are written out. W VO-4 Verilog 'assign' or 'tran' statements are written out. E VO-5 The db file contains inconsistent information about the bussed port '%s'. Its width is %d, but the actually elements only have %d. E VO-6 Can not write out this design '%s' with memory operations\ in it using non-levelized writer. W VO-7 In design '%s', port '%s' has negative indeces [%d:%d] which will be converted into [%d:%d]. W VO-8 Unknown direction port '%s' is assumed to be inout in module '%s'. E VSS-0 Error - please report \fIerror string\fP E VSS-1 subscript out of bounds E VSS-2 error. E VSS-10 access value dereferenced. E VSS-12 arithmetic overflow E VSS-13 time overflow E VSS-16 returned without expression. E VSS-18 to read signal during elaboration or signal evaluation E VSS-19 range is not consistent with corresponding index subtype E VSS-33 Can not use type conversion functions in\ port association lists when the actual is of a resolved type\ Error occurred on Signal %s E VSS-34 There is an implementation error when using the result of a\ type converted INOUT port in another port association. Please call the hotline.\ Error occurred on Signal %s connected to %s", E VSS-35 is ambiguous. E VSS-46 is of the wrong type. E VSS-49 a valid name. E VSS-50 is ambiguous. E VSS-71 virtual memory limit exceeded (tried to allocate %u bytes)\ - more virtual memory must be made available. E VSS-74 Intermediate file - %s (%s) E VSS-80 literal unit smaller than resolution limit in :\