Command Reference2.  FPGA Express Shell Commands         add_file



_N_A_M_E
          add_file       Adds a source file to a library.


SYNTAX
          string add_file [-library _s_t_r_i_n_g]
                 [-format _s_t_r_i_n_g] _N_a_m_e _o_f _t_h_e _f_i_l_e _t_o _a_d_d.

         string    _s_t_r_i_n_g
         string    _s_t_r_i_n_g
         string    _N_a_m_e _o_f _t_h_e _f_i_l_e _t_o _a_d_d.


ARGUMENTS
          -library _s_t_r_i_n_g
                         Library name.  This library must exist
                         in the design project. The file is added
                         to this library if it does not already
                         exist. If this option is not specified,
                         the source file is added to the default
                         library WORK.


          -format _s_t_r_i_n_g File format (VHDL, Verilog, EDIF , XNF
                         ).

                         The format specifies the file type of
                         the source file. The format must be one
                         of the specified formats. The source
                         file format is automatically identified
                         ifit has the recognized extensions. For
                         all other extensions the -format option
                         has to be specified.


          _N_a_m_e _o_f        Source file pathname.  The pathname must
                         be the full path of the file. The
                         extension of the file depends on the
                         format. For VHDL format the file
                         extension can be vhdl or vhd. For
                         Verilog format, the file extensions can
                         be v, ver, ve and verilog. For EDIF
                         format, the file extension can be edf,
                         edif, edn and edo.  For XNF format, the
                         file extension is xnf.



DESCRIPTION
          Adds a source file to the project. Does nothing if the
          file already exists in the project.




v3.0      Synopsys Inc. 1988-1998. All rights reserved.       2-1






add_file        2.  FPGA Express Shell Commands Command Reference



          Returns 1 on error, 0 on success.


EXAMPLES
          All these examples are given assuming that a project is
          already open.

          This example adds a file test.v to the default library
          WORK.

          fe_shell>add_file -format Verilog /tmp/verilog/test.v
          fe_shell>list_files
          Verilog Unanalyzed /tmp/verilog/test.v (WORK)

          This example demonstrates that a file can be added
          without giving the -format option. The command checks
          the format from the file extension.

          fe_shell>add_file /tmp/verilog/test2.v
          fe_shell>list_files
          Verilog Unanalyzed /tmp/verilog/test.v (WORK)
          Verilog Unanalyzed /tmp/verilog/test2.v (WORK)

          This example adds a file test1.vhd to the library MYLIB
          in the design project. MYLIB already exists in the
          design project. If it is not present, it can be created
          using the create_library command.

          fe_shell>add_file -library MYLIB /tmp/vhdl/test1.vhd
          fe_shell>list_files
          Verilog Unanalyzed /tmp/verilog/test.v (WORK)
          Verilog Unanalyzed /tmp/verilog/test2.v (WORK)
          VHDL Unanalyzed /tmp/vhdl/test1.vhd (MYLIB)

          This example tries to add a file already existing in
          the project.

          fe_shell>add_file -format Verilog /tmp/verilog/test.v
          Error: file '/tmp/verilog/test.v' already exist


SEE ALSO
          create_library(2), create_project(2), list_files(2),
          open_project(2), remove_file(2)











2-2       Synopsys Inc. 1988-1998. All rights reserved.      v3.0