Command Reference2.  FPGA Express Shell Commands     analyze_file



_N_A_M_E
          analyze_file   Analyze source files in a library.


SYNTAX
          string analyze_file [-force]
                 [-progress] [_f_i_l_e_n_a_m_e]

         string  _f_i_l_e_n_a_m_e


ARGUMENTS
          -force         Force the analysis of source files.
                         Always analyze the file.


          -progress      Enable the progress report.  It gives
                         out information as the analysis runs.


          _f_i_l_e_n_a_m_e       Source file to be analyzed.

                         The files that are to be analyzed can be
                         only of the formats VHDL, Verilog, XNF
                         and EDIF. The valid file extensions for
                         each of the formats are vhd, vhdl
                         (VHDL), v, ver, verilog, ve (Verilog),
                         edif, edn, edf, edo (EDIF) , xnf (XNF) .



DESCRIPTION
          Analyzes the source files. To analyze a file, a project
          must be open, and the file specified must be readable.

          For VHDL and Verilog files, this analysis does syntax
          checking and synthesis policy checking, and converts
          the source files into intermediate representations
          ready for elaboration.

          For EDIF and XNF , analysis is to read the files.

          A file is analyzed if it is out of date with respect to
          its source. If force is used, always analyze the file.


EXAMPLES
          The designs are stored in the library specified by the
          add_file command.

          This example adds a design to the WORK library.




v3.0      Synopsys Inc. 1988-1998. All rights reserved.       2-1






analyze_file    2.  FPGA Express Shell Commands Command Reference



          fe_shell > analyze_file /tmp/verilog/test.v
          fe_shell > list_design -library WORK
          test_v (/tmp/verilog/test.v)

          This example adds a design to the MYLIB library.

          fe_shell > analyze_file /tmp/verilog/test1.vhd
          fe_shell > list_design -library MYLIB
          test1_vhd (/tmp/verilog/test1.vhd)

          This example shows the usage of -progress.

          fe_shell > analyze_file -progress /tmp/verilog/test2.v

          This example shows the effect of analyzing the files.
          When the file is added, but not analyzed the list_files
          displays the status as Unanalyzed.

          fe_shell > list_files
          Verilog OK /tmp/verilog/test.v (WORK)
          VHDL OK /tmp/vhdl/test1.vhd (MYLIB)
          Verilog OK /tmp/vhdl/test2.vhd (WORK)


SEE ALSO
          add_file (2), list_files (2) , list_design (2)





























2-2       Synopsys Inc. 1988-1998. All rights reserved.      v3.0